[deliverable/linux.git] / drivers / gpio / gpio-pxa.c

/*
 *  linux/arch/arm/plat-pxa/gpio.c
 *
 *  Generic PXA GPIO handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/slab.h>

/*
 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
 * one set of registers. The register offsets are organized below:
 *
 *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
 *
 * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
 *
 * NOTE:
 *   BANK 3 is only available on PXA27x and later processors.
 *   BANK 4 and 5 are only available on PXA935
 */

#define GPLR_OFFSET	0x00
#define GPDR_OFFSET	0x0C
#define GPSR_OFFSET	0x18
#define GPCR_OFFSET	0x24
#define GRER_OFFSET	0x30
#define GFER_OFFSET	0x3C
#define GEDR_OFFSET	0x48
#define GAFR_OFFSET	0x54
#define ED_MASK_OFFSET	0x9C	/* GPIO edge detection for AP side */

#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))

int pxa_last_gpio;

struct pxa_gpio_chip {
	struct gpio_chip chip;
	void __iomem	*regbase;
	char label[10];

	unsigned long	irq_mask;
	unsigned long	irq_edge_rise;
	unsigned long	irq_edge_fall;

#ifdef CONFIG_PM
	unsigned long	saved_gplr;
	unsigned long	saved_gpdr;
	unsigned long	saved_grer;
	unsigned long	saved_gfer;
#endif
};

enum {
	PXA25X_GPIO = 0,
	PXA26X_GPIO,
	PXA27X_GPIO,
	PXA3XX_GPIO,
	PXA93X_GPIO,
	MMP_GPIO = 0x10,
	MMP2_GPIO,
};

static DEFINE_SPINLOCK(gpio_lock);
static struct pxa_gpio_chip *pxa_gpio_chips;
static int gpio_type;
static void __iomem *gpio_reg_base;

#define for_each_gpio_chip(i, c)			\
	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)

static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
{
	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
}

static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
{
	return &pxa_gpio_chips[gpio_to_bank(gpio)];
}

static inline int gpio_is_pxa_type(int type)
{
	return (type & MMP_GPIO) == 0;
}

static inline int gpio_is_mmp_type(int type)
{
	return (type & MMP_GPIO) != 0;
}

/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 */
static inline int __gpio_is_inverted(int gpio)
{
	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
		return 1;
	return 0;
}

/*
 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 * function of a GPIO, and GPDRx cannot be altered once configured. It
 * is attributed as "occupied" here (I know this terminology isn't
 * accurate, you are welcome to propose a better one :-)
 */
static inline int __gpio_is_occupied(unsigned gpio)
{
	struct pxa_gpio_chip *pxachip;
	void __iomem *base;
	unsigned long gafr = 0, gpdr = 0;
	int ret, af = 0, dir = 0;

	pxachip = gpio_to_pxachip(gpio);
	base = gpio_chip_base(&pxachip->chip);
	gpdr = readl_relaxed(base + GPDR_OFFSET);

	switch (gpio_type) {
	case PXA25X_GPIO:
	case PXA26X_GPIO:
	case PXA27X_GPIO:
		gafr = readl_relaxed(base + GAFR_OFFSET);
		af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
		dir = gpdr & GPIO_bit(gpio);

		if (__gpio_is_inverted(gpio))
			ret = (af != 1) || (dir == 0);
		else
			ret = (af != 0) || (dir != 0);
		break;
	default:
		ret = gpdr & GPIO_bit(gpio);
		break;
	}
	return ret;
}

#ifdef CONFIG_ARCH_PXA
static inline int __pxa_gpio_to_irq(int gpio)
{
	if (gpio_is_pxa_type(gpio_type))
		return PXA_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __pxa_irq_to_gpio(int irq)
{
	if (gpio_is_pxa_type(gpio_type))
		return irq - PXA_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
static inline int __pxa_irq_to_gpio(int irq) { return -1; }
#endif

#ifdef CONFIG_ARCH_MMP
static inline int __mmp_gpio_to_irq(int gpio)
{
	if (gpio_is_mmp_type(gpio_type))
		return MMP_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __mmp_irq_to_gpio(int irq)
{
	if (gpio_is_mmp_type(gpio_type))
		return irq - MMP_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
static inline int __mmp_irq_to_gpio(int irq) { return -1; }
#endif

static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	int gpio, ret;

	gpio = chip->base + offset;
	ret = __pxa_gpio_to_irq(gpio);
	if (ret >= 0)
		return ret;
	return __mmp_gpio_to_irq(gpio);
}

int pxa_irq_to_gpio(int irq)
{
	int ret;

	ret = __pxa_irq_to_gpio(irq);
	if (ret >= 0)
		return ret;
	return __mmp_irq_to_gpio(irq);
}

static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t value, mask = 1 << offset;
	unsigned long flags;

	spin_lock_irqsave(&gpio_lock, flags);

	value = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		value |= mask;
	else
		value &= ~mask;
	writel_relaxed(value, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_direction_output(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t tmp, mask = 1 << offset;
	unsigned long flags;

	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));

	spin_lock_irqsave(&gpio_lock, flags);

	tmp = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		tmp &= ~mask;
	else
		tmp |= mask;
	writel_relaxed(tmp, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
}

static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	writel_relaxed(1 << offset, gpio_chip_base(chip) +
				(value ? GPSR_OFFSET : GPCR_OFFSET));
}

static int __devinit pxa_init_gpio_chip(int gpio_end)
{
	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
	struct pxa_gpio_chip *chips;

	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
	if (chips == NULL) {
		pr_err("%s: failed to allocate GPIO chips\n", __func__);
		return -ENOMEM;
	}

	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
		struct gpio_chip *c = &chips[i].chip;

		sprintf(chips[i].label, "gpio-%d", i);
		chips[i].regbase = gpio_reg_base + BANK_OFF(i);

		c->base  = gpio;
		c->label = chips[i].label;

		c->direction_input  = pxa_gpio_direction_input;
		c->direction_output = pxa_gpio_direction_output;
		c->get = pxa_gpio_get;
		c->set = pxa_gpio_set;
		c->to_irq = pxa_gpio_to_irq;

		/* number of GPIOs on last bank may be less than 32 */
		c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
		gpiochip_add(c);
	}
	pxa_gpio_chips = chips;
	return 0;
}

/* Update only those GRERx and GFERx edge detection register bits if those
 * bits are set in c->irq_mask
 */
static inline void update_edge_detect(struct pxa_gpio_chip *c)
{
	uint32_t grer, gfer;

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
	grer |= c->irq_edge_rise & c->irq_mask;
	gfer |= c->irq_edge_fall & c->irq_mask;
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct pxa_gpio_chip *c;
	int gpio = pxa_irq_to_gpio(d->irq);
	unsigned long gpdr, mask = GPIO_bit(gpio);

	c = gpio_to_pxachip(gpio);

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		 * GPIOs set to alternate function or to output during probe
		 */
		if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
			return 0;

		if (__gpio_is_occupied(gpio))
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);

	if (__gpio_is_inverted(gpio))
		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
	else
		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);

	if (type & IRQ_TYPE_EDGE_RISING)
		c->irq_edge_rise |= mask;
	else
		c->irq_edge_rise &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		c->irq_edge_fall |= mask;
	else
		c->irq_edge_fall &= ~mask;

	update_edge_detect(c);

	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	return 0;
}

static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pxa_gpio_chip *c;
	int loop, gpio, gpio_base, n;
	unsigned long gedr;

	do {
		loop = 0;
		for_each_gpio_chip(gpio, c) {
			gpio_base = c->chip.base;

			gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
			gedr = gedr & c->irq_mask;
			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);

			n = find_first_bit(&gedr, BITS_PER_LONG);
			while (n < BITS_PER_LONG) {
				loop = 1;

				generic_handle_irq(gpio_to_irq(gpio_base + n));
				n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
			}
		}
	} while (loop);
}

static void pxa_ack_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
}

static void pxa_mask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
	uint32_t grer, gfer;

	c->irq_mask &= ~GPIO_bit(gpio);

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static void pxa_unmask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	c->irq_mask |= GPIO_bit(gpio);
	update_edge_detect(c);
}

static struct irq_chip pxa_muxed_gpio_chip = {
	.name		= "GPIO",
	.irq_ack	= pxa_ack_muxed_gpio,
	.irq_mask	= pxa_mask_muxed_gpio,
	.irq_unmask	= pxa_unmask_muxed_gpio,
	.irq_set_type	= pxa_gpio_irq_type,
};

static int pxa_gpio_nums(void)
{
	int count = 0;

#ifdef CONFIG_ARCH_PXA
	if (cpu_is_pxa25x()) {
#ifdef CONFIG_CPU_PXA26x
		count = 89;
		gpio_type = PXA26X_GPIO;
#elif defined(CONFIG_PXA25x)
		count = 84;
		gpio_type = PXA26X_GPIO;
#endif /* CONFIG_CPU_PXA26x */
	} else if (cpu_is_pxa27x()) {
		count = 120;
		gpio_type = PXA27X_GPIO;
	} else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
		count = 191;
		gpio_type = PXA93X_GPIO;
	} else if (cpu_is_pxa3xx()) {
		count = 127;
		gpio_type = PXA3XX_GPIO;
	}
#endif /* CONFIG_ARCH_PXA */

#ifdef CONFIG_ARCH_MMP
	if (cpu_is_pxa168() || cpu_is_pxa910()) {
		count = 127;
		gpio_type = MMP_GPIO;
	} else if (cpu_is_mmp2()) {
		count = 191;
		gpio_type = MMP2_GPIO;
	}
#endif /* CONFIG_ARCH_MMP */
	return count;
}

static int __devinit pxa_gpio_probe(struct platform_device *pdev)
{
	struct pxa_gpio_chip *c;
	struct resource *res;
	struct clk *clk;
	int gpio, irq, ret;
	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;

	pxa_last_gpio = pxa_gpio_nums();
	if (!pxa_last_gpio)
		return -EINVAL;

	irq0 = platform_get_irq_byname(pdev, "gpio0");
	irq1 = platform_get_irq_byname(pdev, "gpio1");
	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
		|| (irq_mux <= 0))
		return -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;
	gpio_reg_base = ioremap(res->start, resource_size(res));
	if (!gpio_reg_base)
		return -EINVAL;

	if (irq0 > 0)
		gpio_offset = 2;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
			PTR_ERR(clk));
		iounmap(gpio_reg_base);
		return PTR_ERR(clk);
	}
	ret = clk_prepare(clk);
	if (ret) {
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}
	ret = clk_enable(clk);
	if (ret) {
		clk_unprepare(clk);
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}

	/* Initialize GPIO chips */
	pxa_init_gpio_chip(pxa_last_gpio);

	/* clear all GPIO edge detects */
	for_each_gpio_chip(gpio, c) {
		writel_relaxed(0, c->regbase + GFER_OFFSET);
		writel_relaxed(0, c->regbase + GRER_OFFSET);
		writel_relaxed(~0,c->regbase + GEDR_OFFSET);
		/* unmask GPIO edge detect for AP side */
		if (gpio_is_mmp_type(gpio_type))
			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
	}

#ifdef CONFIG_ARCH_PXA
	irq = gpio_to_irq(0);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);

	irq = gpio_to_irq(1);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
#endif

	for (irq  = gpio_to_irq(gpio_offset);
		irq <= gpio_to_irq(pxa_last_gpio); irq++) {
		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	return 0;
}

static struct platform_driver pxa_gpio_driver = {
	.probe		= pxa_gpio_probe,
	.driver		= {
		.name	= "pxa-gpio",
	},
};

static int __init pxa_gpio_init(void)
{
	return platform_driver_register(&pxa_gpio_driver);
}
postcore_initcall(pxa_gpio_init);

#ifdef CONFIG_PM
static int pxa_gpio_suspend(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
		c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
		c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
		c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);

		/* Clear GPIO transition detect bits */
		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
	}
	return 0;
}

static void pxa_gpio_resume(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		/* restore level with set/clear */
		writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);

		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
	}
}
#else
#define pxa_gpio_suspend	NULL
#define pxa_gpio_resume		NULL
#endif

struct syscore_ops pxa_gpio_syscore_ops = {
	.suspend	= pxa_gpio_suspend,
	.resume		= pxa_gpio_resume,
};

static int __init pxa_gpio_sysinit(void)
{
	register_syscore_ops(&pxa_gpio_syscore_ops);
	return 0;
}
postcore_initcall(pxa_gpio_sysinit);
Commit	Line	Data
1c44f5f1	1	/*
38f539a6	2	* linux/arch/arm/plat-pxa/gpio.c
1c44f5f1 PZ	3	*
	4	* Generic PXA GPIO handling
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Jun 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
389eda15 HZ	14	#include <linux/clk.h>
389eda15 HZ	15	#include <linux/err.h>
2f8163ba	16	#include <linux/gpio.h>
157d2644	17	#include <linux/gpio-pxa.h>
1c44f5f1	18	#include <linux/init.h>
e3630db1	19	#include <linux/irq.h>
fced80c7	20	#include <linux/io.h>
157d2644	21	#include <linux/platform_device.h>
2eaa03b5	22	#include <linux/syscore_ops.h>
4aa78264	23	#include <linux/slab.h>
1c44f5f1	24
157d2644 HZ	25	/*
	26	* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
	27	* one set of registers. The register offsets are organized below:
	28	*
	29	* GPLR GPDR GPSR GPCR GRER GFER GEDR
	30	* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
	31	* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
	32	* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
	33	*
	34	* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
	35	* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
	36	* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
	37	*
	38	* NOTE:
	39	* BANK 3 is only available on PXA27x and later processors.
	40	* BANK 4 and 5 are only available on PXA935
	41	*/
	42
	43	#define GPLR_OFFSET 0x00
	44	#define GPDR_OFFSET 0x0C
	45	#define GPSR_OFFSET 0x18
	46	#define GPCR_OFFSET 0x24
	47	#define GRER_OFFSET 0x30
	48	#define GFER_OFFSET 0x3C
	49	#define GEDR_OFFSET 0x48
	50	#define GAFR_OFFSET 0x54
be24168f	51	#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
157d2644 HZ	52
157d2644 HZ	53	#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
1c44f5f1	54
3b8e285c EM	55	int pxa_last_gpio;
3b8e285c EM	56
1c44f5f1 PZ	57	struct pxa_gpio_chip {
1c44f5f1 PZ	58	struct gpio_chip chip;
0807da59 EM	59	void __iomem *regbase;
	60	char label[10];
	61
	62	unsigned long irq_mask;
	63	unsigned long irq_edge_rise;
	64	unsigned long irq_edge_fall;
	65
	66	#ifdef CONFIG_PM
	67	unsigned long saved_gplr;
	68	unsigned long saved_gpdr;
	69	unsigned long saved_grer;
	70	unsigned long saved_gfer;
	71	#endif
1c44f5f1 PZ	72	};
1c44f5f1 PZ	73
4929f5a8 HZ	74	enum {
	75	PXA25X_GPIO = 0,
	76	PXA26X_GPIO,
	77	PXA27X_GPIO,
	78	PXA3XX_GPIO,
	79	PXA93X_GPIO,
	80	MMP_GPIO = 0x10,
	81	MMP2_GPIO,
	82	};
	83
0807da59 EM	84	static DEFINE_SPINLOCK(gpio_lock);
0807da59 EM	85	static struct pxa_gpio_chip *pxa_gpio_chips;
4929f5a8	86	static int gpio_type;
157d2644	87	static void __iomem *gpio_reg_base;
0807da59 EM	88
	89	#define for_each_gpio_chip(i, c) \
	90	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
	91
	92	static inline void __iomem gpio_chip_base(struct gpio_chip c)
	93	{
	94	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
	95	}
	96
a065685d	97	static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
0807da59 EM	98	{
	99	return &pxa_gpio_chips[gpio_to_bank(gpio)];
	100	}
	101
4929f5a8 HZ	102	static inline int gpio_is_pxa_type(int type)
	103	{
	104	return (type & MMP_GPIO) == 0;
	105	}
	106
	107	static inline int gpio_is_mmp_type(int type)
	108	{
	109	return (type & MMP_GPIO) != 0;
	110	}
	111
157d2644 HZ	112	/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
	113	* as well as their Alternate Function value being '1' for GPIO in GAFRx.
	114	*/
	115	static inline int __gpio_is_inverted(int gpio)
	116	{
	117	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
	118	return 1;
	119	return 0;
	120	}
	121
	122	/*
	123	* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
	124	* function of a GPIO, and GPDRx cannot be altered once configured. It
	125	* is attributed as "occupied" here (I know this terminology isn't
	126	* accurate, you are welcome to propose a better one :-)
	127	*/
	128	static inline int __gpio_is_occupied(unsigned gpio)
	129	{
	130	struct pxa_gpio_chip *pxachip;
	131	void __iomem *base;
	132	unsigned long gafr = 0, gpdr = 0;
	133	int ret, af = 0, dir = 0;
	134
	135	pxachip = gpio_to_pxachip(gpio);
	136	base = gpio_chip_base(&pxachip->chip);
	137	gpdr = readl_relaxed(base + GPDR_OFFSET);
	138
	139	switch (gpio_type) {
	140	case PXA25X_GPIO:
	141	case PXA26X_GPIO:
	142	case PXA27X_GPIO:
	143	gafr = readl_relaxed(base + GAFR_OFFSET);
	144	af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
	145	dir = gpdr & GPIO_bit(gpio);
	146
	147	if (__gpio_is_inverted(gpio))
	148	ret = (af != 1) \|\| (dir == 0);
	149	else
	150	ret = (af != 0) \|\| (dir != 0);
	151	break;
	152	default:
	153	ret = gpdr & GPIO_bit(gpio);
	154	break;
	155	}
	156	return ret;
	157	}
	158
4929f5a8 HZ	159	#ifdef CONFIG_ARCH_PXA
	160	static inline int __pxa_gpio_to_irq(int gpio)
	161	{
	162	if (gpio_is_pxa_type(gpio_type))
	163	return PXA_GPIO_TO_IRQ(gpio);
	164	return -1;
	165	}
	166
	167	static inline int __pxa_irq_to_gpio(int irq)
	168	{
	169	if (gpio_is_pxa_type(gpio_type))
	170	return irq - PXA_GPIO_TO_IRQ(0);
	171	return -1;
	172	}
	173	#else
	174	static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
	175	static inline int __pxa_irq_to_gpio(int irq) { return -1; }
	176	#endif
	177
	178	#ifdef CONFIG_ARCH_MMP
	179	static inline int __mmp_gpio_to_irq(int gpio)
	180	{
	181	if (gpio_is_mmp_type(gpio_type))
	182	return MMP_GPIO_TO_IRQ(gpio);
	183	return -1;
	184	}
	185
	186	static inline int __mmp_irq_to_gpio(int irq)
	187	{
	188	if (gpio_is_mmp_type(gpio_type))
	189	return irq - MMP_GPIO_TO_IRQ(0);
	190	return -1;
	191	}
	192	#else
	193	static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
	194	static inline int __mmp_irq_to_gpio(int irq) { return -1; }
	195	#endif
	196
	197	static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	198	{
	199	int gpio, ret;
	200
	201	gpio = chip->base + offset;
	202	ret = __pxa_gpio_to_irq(gpio);
	203	if (ret >= 0)
	204	return ret;
	205	return __mmp_gpio_to_irq(gpio);
	206	}
	207
	208	int pxa_irq_to_gpio(int irq)
	209	{
	210	int ret;
	211
	212	ret = __pxa_irq_to_gpio(irq);
	213	if (ret >= 0)
	214	return ret;
	215	return __mmp_irq_to_gpio(irq);
	216	}
	217
1c44f5f1 PZ	218	static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	219	{
0807da59 EM	220	void __iomem *base = gpio_chip_base(chip);
	221	uint32_t value, mask = 1 << offset;
	222	unsigned long flags;
	223
	224	spin_lock_irqsave(&gpio_lock, flags);
	225
df664d20	226	value = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	227	if (__gpio_is_inverted(chip->base + offset))
	228	value \|= mask;
	229	else
	230	value &= ~mask;
df664d20	231	writel_relaxed(value, base + GPDR_OFFSET);
1c44f5f1	232
0807da59	233	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	234	return 0;
	235	}
	236
	237	static int pxa_gpio_direction_output(struct gpio_chip *chip,
0807da59	238	unsigned offset, int value)
1c44f5f1	239	{
0807da59 EM	240	void __iomem *base = gpio_chip_base(chip);
	241	uint32_t tmp, mask = 1 << offset;
	242	unsigned long flags;
	243
df664d20	244	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0807da59 EM	245
	246	spin_lock_irqsave(&gpio_lock, flags);
	247
df664d20	248	tmp = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	249	if (__gpio_is_inverted(chip->base + offset))
	250	tmp &= ~mask;
	251	else
	252	tmp \|= mask;
df664d20	253	writel_relaxed(tmp, base + GPDR_OFFSET);
1c44f5f1	254
0807da59	255	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	256	return 0;
	257	}
	258
1c44f5f1 PZ	259	static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	260	{
df664d20	261	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
1c44f5f1 PZ	262	}
1c44f5f1 PZ	263
1c44f5f1 PZ	264	static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1c44f5f1 PZ	265	{
df664d20	266	writel_relaxed(1 << offset, gpio_chip_base(chip) +
0807da59	267	(value ? GPSR_OFFSET : GPCR_OFFSET));
1c44f5f1 PZ	268	}
1c44f5f1 PZ	269
157d2644	270	static int __devinit pxa_init_gpio_chip(int gpio_end)
a58fbcd8	271	{
0807da59 EM	272	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
0807da59 EM	273	struct pxa_gpio_chip *chips;
a58fbcd8	274
4aa78264	275	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
0807da59 EM	276	if (chips == NULL) {
	277	pr_err("%s: failed to allocate GPIO chips\n", __func__);
	278	return -ENOMEM;
a58fbcd8	279	}
a58fbcd8	280
0807da59 EM	281	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
0807da59 EM	282	struct gpio_chip *c = &chips[i].chip;
e3630db1	283
0807da59	284	sprintf(chips[i].label, "gpio-%d", i);
157d2644	285	chips[i].regbase = gpio_reg_base + BANK_OFF(i);
0807da59 EM	286
	287	c->base = gpio;
	288	c->label = chips[i].label;
	289
	290	c->direction_input = pxa_gpio_direction_input;
	291	c->direction_output = pxa_gpio_direction_output;
	292	c->get = pxa_gpio_get;
	293	c->set = pxa_gpio_set;
4929f5a8	294	c->to_irq = pxa_gpio_to_irq;
0807da59 EM	295
	296	/* number of GPIOs on last bank may be less than 32 */
	297	c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
	298	gpiochip_add(c);
	299	}
	300	pxa_gpio_chips = chips;
	301	return 0;
	302	}
e3630db1	303
a8f6faeb EM	304	/* Update only those GRERx and GFERx edge detection register bits if those
	305	* bits are set in c->irq_mask
	306	*/
	307	static inline void update_edge_detect(struct pxa_gpio_chip *c)
	308	{
	309	uint32_t grer, gfer;
	310
df664d20 HZ	311	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
df664d20 HZ	312	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
a8f6faeb EM	313	grer \|= c->irq_edge_rise & c->irq_mask;
a8f6faeb EM	314	gfer \|= c->irq_edge_fall & c->irq_mask;
df664d20 HZ	315	writel_relaxed(grer, c->regbase + GRER_OFFSET);
df664d20 HZ	316	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
a8f6faeb EM	317	}
a8f6faeb EM	318
a3f4c927	319	static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
e3630db1	320	{
0807da59	321	struct pxa_gpio_chip *c;
4929f5a8	322	int gpio = pxa_irq_to_gpio(d->irq);
0807da59	323	unsigned long gpdr, mask = GPIO_bit(gpio);
e3630db1	324
a065685d	325	c = gpio_to_pxachip(gpio);
e3630db1	326
	327	if (type == IRQ_TYPE_PROBE) {
	328	/* Don't mess with enabled GPIOs using preconfigured edges or
	329	* GPIOs set to alternate function or to output during probe
	330	*/
0807da59	331	if ((c->irq_edge_rise \| c->irq_edge_fall) & GPIO_bit(gpio))
e3630db1	332	return 0;
689c04a3	333
689c04a3	334	if (__gpio_is_occupied(gpio))
e3630db1	335	return 0;
689c04a3	336
e3630db1	337	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	338	}
	339
df664d20	340	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0807da59	341
067455aa	342	if (__gpio_is_inverted(gpio))
df664d20	343	writel_relaxed(gpdr \| mask, c->regbase + GPDR_OFFSET);
067455aa	344	else
df664d20	345	writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
e3630db1	346
e3630db1	347	if (type & IRQ_TYPE_EDGE_RISING)
0807da59	348	c->irq_edge_rise \|= mask;
e3630db1	349	else
0807da59	350	c->irq_edge_rise &= ~mask;
e3630db1	351
e3630db1	352	if (type & IRQ_TYPE_EDGE_FALLING)
0807da59	353	c->irq_edge_fall \|= mask;
e3630db1	354	else
0807da59	355	c->irq_edge_fall &= ~mask;
e3630db1	356
a8f6faeb	357	update_edge_detect(c);
e3630db1	358
a3f4c927	359	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
e3630db1	360	((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
	361	((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	362	return 0;
	363	}
	364
e3630db1	365	static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
e3630db1	366	{
0807da59 EM	367	struct pxa_gpio_chip *c;
	368	int loop, gpio, gpio_base, n;
	369	unsigned long gedr;
e3630db1	370
e3630db1	371	do {
e3630db1	372	loop = 0;
0807da59 EM	373	for_each_gpio_chip(gpio, c) {
	374	gpio_base = c->chip.base;
	375
df664d20	376	gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0807da59	377	gedr = gedr & c->irq_mask;
df664d20	378	writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
e3630db1	379
0807da59 EM	380	n = find_first_bit(&gedr, BITS_PER_LONG);
	381	while (n < BITS_PER_LONG) {
	382	loop = 1;
e3630db1	383
0807da59 EM	384	generic_handle_irq(gpio_to_irq(gpio_base + n));
	385	n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
	386	}
e3630db1	387	}
	388	} while (loop);
	389	}
	390
a3f4c927	391	static void pxa_ack_muxed_gpio(struct irq_data *d)
e3630db1	392	{
4929f5a8	393	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	394	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59	395
df664d20	396	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
e3630db1	397	}
e3630db1	398
a3f4c927	399	static void pxa_mask_muxed_gpio(struct irq_data *d)
e3630db1	400	{
4929f5a8	401	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	402	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	403	uint32_t grer, gfer;
	404
	405	c->irq_mask &= ~GPIO_bit(gpio);
	406
df664d20 HZ	407	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	408	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	409	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	410	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
e3630db1	411	}
e3630db1	412
a3f4c927	413	static void pxa_unmask_muxed_gpio(struct irq_data *d)
e3630db1	414	{
4929f5a8	415	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	416	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	417
0807da59 EM	418	c->irq_mask \|= GPIO_bit(gpio);
a8f6faeb	419	update_edge_detect(c);
e3630db1	420	}
	421
	422	static struct irq_chip pxa_muxed_gpio_chip = {
	423	.name = "GPIO",
a3f4c927 LB	424	.irq_ack = pxa_ack_muxed_gpio,
	425	.irq_mask = pxa_mask_muxed_gpio,
	426	.irq_unmask = pxa_unmask_muxed_gpio,
	427	.irq_set_type = pxa_gpio_irq_type,
e3630db1	428	};
e3630db1	429
478e223c HZ	430	static int pxa_gpio_nums(void)
	431	{
	432	int count = 0;
	433
	434	#ifdef CONFIG_ARCH_PXA
	435	if (cpu_is_pxa25x()) {
	436	#ifdef CONFIG_CPU_PXA26x
	437	count = 89;
	438	gpio_type = PXA26X_GPIO;
	439	#elif defined(CONFIG_PXA25x)
	440	count = 84;
	441	gpio_type = PXA26X_GPIO;
	442	#endif /* CONFIG_CPU_PXA26x */
	443	} else if (cpu_is_pxa27x()) {
	444	count = 120;
	445	gpio_type = PXA27X_GPIO;
	446	} else if (cpu_is_pxa93x() \|\| cpu_is_pxa95x()) {
	447	count = 191;
	448	gpio_type = PXA93X_GPIO;
	449	} else if (cpu_is_pxa3xx()) {
	450	count = 127;
	451	gpio_type = PXA3XX_GPIO;
	452	}
	453	#endif /* CONFIG_ARCH_PXA */
	454
	455	#ifdef CONFIG_ARCH_MMP
	456	if (cpu_is_pxa168() \|\| cpu_is_pxa910()) {
	457	count = 127;
	458	gpio_type = MMP_GPIO;
	459	} else if (cpu_is_mmp2()) {
	460	count = 191;
	461	gpio_type = MMP2_GPIO;
	462	}
	463	#endif /* CONFIG_ARCH_MMP */
	464	return count;
	465	}
	466
157d2644	467	static int __devinit pxa_gpio_probe(struct platform_device *pdev)
e3630db1	468	{
0807da59	469	struct pxa_gpio_chip *c;
157d2644	470	struct resource *res;
389eda15 HZ	471	struct clk *clk;
389eda15 HZ	472	int gpio, irq, ret;
157d2644	473	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
e3630db1	474
478e223c HZ	475	pxa_last_gpio = pxa_gpio_nums();
478e223c HZ	476	if (!pxa_last_gpio)
157d2644 HZ	477	return -EINVAL;
	478
	479	irq0 = platform_get_irq_byname(pdev, "gpio0");
	480	irq1 = platform_get_irq_byname(pdev, "gpio1");
	481	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	482	if ((irq0 > 0 && irq1 <= 0) \|\| (irq0 <= 0 && irq1 > 0)
	483	\|\| (irq_mux <= 0))
	484	return -EINVAL;
	485	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	486	if (!res)
	487	return -EINVAL;
	488	gpio_reg_base = ioremap(res->start, resource_size(res));
	489	if (!gpio_reg_base)
	490	return -EINVAL;
	491
	492	if (irq0 > 0)
	493	gpio_offset = 2;
e3630db1	494
389eda15 HZ	495	clk = clk_get(&pdev->dev, NULL);
	496	if (IS_ERR(clk)) {
	497	dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
	498	PTR_ERR(clk));
	499	iounmap(gpio_reg_base);
	500	return PTR_ERR(clk);
	501	}
	502	ret = clk_prepare(clk);
	503	if (ret) {
	504	clk_put(clk);
	505	iounmap(gpio_reg_base);
	506	return ret;
	507	}
	508	ret = clk_enable(clk);
	509	if (ret) {
	510	clk_unprepare(clk);
	511	clk_put(clk);
	512	iounmap(gpio_reg_base);
	513	return ret;
	514	}
	515
0807da59	516	/* Initialize GPIO chips */
157d2644	517	pxa_init_gpio_chip(pxa_last_gpio);
0807da59	518
e3630db1	519	/* clear all GPIO edge detects */
0807da59	520	for_each_gpio_chip(gpio, c) {
df664d20 HZ	521	writel_relaxed(0, c->regbase + GFER_OFFSET);
	522	writel_relaxed(0, c->regbase + GRER_OFFSET);
	523	writel_relaxed(~0,c->regbase + GEDR_OFFSET);
be24168f HZ	524	/* unmask GPIO edge detect for AP side */
	525	if (gpio_is_mmp_type(gpio_type))
	526	writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
e3630db1	527	}
e3630db1	528
87c49e20 HZ	529	#ifdef CONFIG_ARCH_PXA
	530	irq = gpio_to_irq(0);
	531	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	532	handle_edge_irq);
	533	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	534	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
	535
	536	irq = gpio_to_irq(1);
	537	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	538	handle_edge_irq);
	539	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	540	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
	541	#endif
	542
157d2644 HZ	543	for (irq = gpio_to_irq(gpio_offset);
157d2644 HZ	544	irq <= gpio_to_irq(pxa_last_gpio); irq++) {
f38c02f3 TG	545	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
f38c02f3 TG	546	handle_edge_irq);
e3630db1	547	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	548	}
	549
157d2644 HZ	550	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	551	return 0;
	552	}
	553
	554	static struct platform_driver pxa_gpio_driver = {
	555	.probe = pxa_gpio_probe,
	556	.driver = {
	557	.name = "pxa-gpio",
	558	},
	559	};
	560
	561	static int __init pxa_gpio_init(void)
	562	{
	563	return platform_driver_register(&pxa_gpio_driver);
e3630db1	564	}
157d2644	565	postcore_initcall(pxa_gpio_init);
663707c1	566
663707c1	567	#ifdef CONFIG_PM
2eaa03b5	568	static int pxa_gpio_suspend(void)
663707c1	569	{
0807da59 EM	570	struct pxa_gpio_chip *c;
0807da59 EM	571	int gpio;
663707c1	572
0807da59	573	for_each_gpio_chip(gpio, c) {
df664d20 HZ	574	c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
	575	c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
	576	c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
	577	c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
663707c1	578
663707c1	579	/* Clear GPIO transition detect bits */
df664d20	580	writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
663707c1	581	}
	582	return 0;
	583	}
	584
2eaa03b5	585	static void pxa_gpio_resume(void)
663707c1	586	{
0807da59 EM	587	struct pxa_gpio_chip *c;
0807da59 EM	588	int gpio;
663707c1	589
0807da59	590	for_each_gpio_chip(gpio, c) {
663707c1	591	/* restore level with set/clear */
df664d20 HZ	592	writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
df664d20 HZ	593	writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
663707c1	594
df664d20 HZ	595	writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
	596	writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
	597	writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
663707c1	598	}
663707c1	599	}
	600	#else
	601	#define pxa_gpio_suspend NULL
	602	#define pxa_gpio_resume NULL
	603	#endif
	604
2eaa03b5	605	struct syscore_ops pxa_gpio_syscore_ops = {
663707c1	606	.suspend = pxa_gpio_suspend,
	607	.resume = pxa_gpio_resume,
	608	};
157d2644 HZ	609
	610	static int __init pxa_gpio_sysinit(void)
	611	{
	612	register_syscore_ops(&pxa_gpio_syscore_ops);
	613	return 0;
	614	}
	615	postcore_initcall(pxa_gpio_sysinit);