Commit | Line | Data |
---|---|---|
1c44f5f1 | 1 | /* |
38f539a6 | 2 | * linux/arch/arm/plat-pxa/gpio.c |
1c44f5f1 PZ |
3 | * |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
389eda15 HZ |
14 | #include <linux/clk.h> |
15 | #include <linux/err.h> | |
2f8163ba | 16 | #include <linux/gpio.h> |
157d2644 | 17 | #include <linux/gpio-pxa.h> |
1c44f5f1 | 18 | #include <linux/init.h> |
e3630db1 | 19 | #include <linux/irq.h> |
fced80c7 | 20 | #include <linux/io.h> |
157d2644 | 21 | #include <linux/platform_device.h> |
2eaa03b5 | 22 | #include <linux/syscore_ops.h> |
4aa78264 | 23 | #include <linux/slab.h> |
1c44f5f1 | 24 | |
feefe73f RH |
25 | #include <mach/irqs.h> |
26 | ||
157d2644 HZ |
27 | /* |
28 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | |
29 | * one set of registers. The register offsets are organized below: | |
30 | * | |
31 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | |
32 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | |
33 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | |
34 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | |
35 | * | |
36 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | |
37 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | |
38 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | |
39 | * | |
40 | * NOTE: | |
41 | * BANK 3 is only available on PXA27x and later processors. | |
42 | * BANK 4 and 5 are only available on PXA935 | |
43 | */ | |
44 | ||
45 | #define GPLR_OFFSET 0x00 | |
46 | #define GPDR_OFFSET 0x0C | |
47 | #define GPSR_OFFSET 0x18 | |
48 | #define GPCR_OFFSET 0x24 | |
49 | #define GRER_OFFSET 0x30 | |
50 | #define GFER_OFFSET 0x3C | |
51 | #define GEDR_OFFSET 0x48 | |
52 | #define GAFR_OFFSET 0x54 | |
be24168f | 53 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
157d2644 HZ |
54 | |
55 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | |
1c44f5f1 | 56 | |
3b8e285c EM |
57 | int pxa_last_gpio; |
58 | ||
1c44f5f1 PZ |
59 | struct pxa_gpio_chip { |
60 | struct gpio_chip chip; | |
0807da59 EM |
61 | void __iomem *regbase; |
62 | char label[10]; | |
63 | ||
64 | unsigned long irq_mask; | |
65 | unsigned long irq_edge_rise; | |
66 | unsigned long irq_edge_fall; | |
b95ace54 | 67 | int (*set_wake)(unsigned int gpio, unsigned int on); |
0807da59 EM |
68 | |
69 | #ifdef CONFIG_PM | |
70 | unsigned long saved_gplr; | |
71 | unsigned long saved_gpdr; | |
72 | unsigned long saved_grer; | |
73 | unsigned long saved_gfer; | |
74 | #endif | |
1c44f5f1 PZ |
75 | }; |
76 | ||
4929f5a8 HZ |
77 | enum { |
78 | PXA25X_GPIO = 0, | |
79 | PXA26X_GPIO, | |
80 | PXA27X_GPIO, | |
81 | PXA3XX_GPIO, | |
82 | PXA93X_GPIO, | |
83 | MMP_GPIO = 0x10, | |
84 | MMP2_GPIO, | |
85 | }; | |
86 | ||
0807da59 EM |
87 | static DEFINE_SPINLOCK(gpio_lock); |
88 | static struct pxa_gpio_chip *pxa_gpio_chips; | |
4929f5a8 | 89 | static int gpio_type; |
157d2644 | 90 | static void __iomem *gpio_reg_base; |
0807da59 EM |
91 | |
92 | #define for_each_gpio_chip(i, c) \ | |
93 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) | |
94 | ||
95 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) | |
96 | { | |
97 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; | |
98 | } | |
99 | ||
a065685d | 100 | static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) |
0807da59 EM |
101 | { |
102 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; | |
103 | } | |
104 | ||
4929f5a8 HZ |
105 | static inline int gpio_is_pxa_type(int type) |
106 | { | |
107 | return (type & MMP_GPIO) == 0; | |
108 | } | |
109 | ||
110 | static inline int gpio_is_mmp_type(int type) | |
111 | { | |
112 | return (type & MMP_GPIO) != 0; | |
113 | } | |
114 | ||
157d2644 HZ |
115 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
116 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | |
117 | */ | |
118 | static inline int __gpio_is_inverted(int gpio) | |
119 | { | |
120 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) | |
121 | return 1; | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* | |
126 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | |
127 | * function of a GPIO, and GPDRx cannot be altered once configured. It | |
128 | * is attributed as "occupied" here (I know this terminology isn't | |
129 | * accurate, you are welcome to propose a better one :-) | |
130 | */ | |
131 | static inline int __gpio_is_occupied(unsigned gpio) | |
132 | { | |
133 | struct pxa_gpio_chip *pxachip; | |
134 | void __iomem *base; | |
135 | unsigned long gafr = 0, gpdr = 0; | |
136 | int ret, af = 0, dir = 0; | |
137 | ||
138 | pxachip = gpio_to_pxachip(gpio); | |
139 | base = gpio_chip_base(&pxachip->chip); | |
140 | gpdr = readl_relaxed(base + GPDR_OFFSET); | |
141 | ||
142 | switch (gpio_type) { | |
143 | case PXA25X_GPIO: | |
144 | case PXA26X_GPIO: | |
145 | case PXA27X_GPIO: | |
146 | gafr = readl_relaxed(base + GAFR_OFFSET); | |
147 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; | |
148 | dir = gpdr & GPIO_bit(gpio); | |
149 | ||
150 | if (__gpio_is_inverted(gpio)) | |
151 | ret = (af != 1) || (dir == 0); | |
152 | else | |
153 | ret = (af != 0) || (dir != 0); | |
154 | break; | |
155 | default: | |
156 | ret = gpdr & GPIO_bit(gpio); | |
157 | break; | |
158 | } | |
159 | return ret; | |
160 | } | |
161 | ||
4929f5a8 HZ |
162 | #ifdef CONFIG_ARCH_PXA |
163 | static inline int __pxa_gpio_to_irq(int gpio) | |
164 | { | |
165 | if (gpio_is_pxa_type(gpio_type)) | |
166 | return PXA_GPIO_TO_IRQ(gpio); | |
167 | return -1; | |
168 | } | |
169 | ||
170 | static inline int __pxa_irq_to_gpio(int irq) | |
171 | { | |
172 | if (gpio_is_pxa_type(gpio_type)) | |
173 | return irq - PXA_GPIO_TO_IRQ(0); | |
174 | return -1; | |
175 | } | |
176 | #else | |
177 | static inline int __pxa_gpio_to_irq(int gpio) { return -1; } | |
178 | static inline int __pxa_irq_to_gpio(int irq) { return -1; } | |
179 | #endif | |
180 | ||
181 | #ifdef CONFIG_ARCH_MMP | |
182 | static inline int __mmp_gpio_to_irq(int gpio) | |
183 | { | |
184 | if (gpio_is_mmp_type(gpio_type)) | |
185 | return MMP_GPIO_TO_IRQ(gpio); | |
186 | return -1; | |
187 | } | |
188 | ||
189 | static inline int __mmp_irq_to_gpio(int irq) | |
190 | { | |
191 | if (gpio_is_mmp_type(gpio_type)) | |
192 | return irq - MMP_GPIO_TO_IRQ(0); | |
193 | return -1; | |
194 | } | |
195 | #else | |
196 | static inline int __mmp_gpio_to_irq(int gpio) { return -1; } | |
197 | static inline int __mmp_irq_to_gpio(int irq) { return -1; } | |
198 | #endif | |
199 | ||
200 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
201 | { | |
202 | int gpio, ret; | |
203 | ||
204 | gpio = chip->base + offset; | |
205 | ret = __pxa_gpio_to_irq(gpio); | |
206 | if (ret >= 0) | |
207 | return ret; | |
208 | return __mmp_gpio_to_irq(gpio); | |
209 | } | |
210 | ||
211 | int pxa_irq_to_gpio(int irq) | |
212 | { | |
213 | int ret; | |
214 | ||
215 | ret = __pxa_irq_to_gpio(irq); | |
216 | if (ret >= 0) | |
217 | return ret; | |
218 | return __mmp_irq_to_gpio(irq); | |
219 | } | |
220 | ||
1c44f5f1 PZ |
221 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
222 | { | |
0807da59 EM |
223 | void __iomem *base = gpio_chip_base(chip); |
224 | uint32_t value, mask = 1 << offset; | |
225 | unsigned long flags; | |
226 | ||
227 | spin_lock_irqsave(&gpio_lock, flags); | |
228 | ||
df664d20 | 229 | value = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
230 | if (__gpio_is_inverted(chip->base + offset)) |
231 | value |= mask; | |
232 | else | |
233 | value &= ~mask; | |
df664d20 | 234 | writel_relaxed(value, base + GPDR_OFFSET); |
1c44f5f1 | 235 | |
0807da59 | 236 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
237 | return 0; |
238 | } | |
239 | ||
240 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
0807da59 | 241 | unsigned offset, int value) |
1c44f5f1 | 242 | { |
0807da59 EM |
243 | void __iomem *base = gpio_chip_base(chip); |
244 | uint32_t tmp, mask = 1 << offset; | |
245 | unsigned long flags; | |
246 | ||
df664d20 | 247 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
0807da59 EM |
248 | |
249 | spin_lock_irqsave(&gpio_lock, flags); | |
250 | ||
df664d20 | 251 | tmp = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
252 | if (__gpio_is_inverted(chip->base + offset)) |
253 | tmp &= ~mask; | |
254 | else | |
255 | tmp |= mask; | |
df664d20 | 256 | writel_relaxed(tmp, base + GPDR_OFFSET); |
1c44f5f1 | 257 | |
0807da59 | 258 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
259 | return 0; |
260 | } | |
261 | ||
1c44f5f1 PZ |
262 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
263 | { | |
df664d20 | 264 | return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
1c44f5f1 PZ |
265 | } |
266 | ||
1c44f5f1 PZ |
267 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
268 | { | |
df664d20 | 269 | writel_relaxed(1 << offset, gpio_chip_base(chip) + |
0807da59 | 270 | (value ? GPSR_OFFSET : GPCR_OFFSET)); |
1c44f5f1 PZ |
271 | } |
272 | ||
b95ace54 RJ |
273 | static int __devinit pxa_init_gpio_chip(int gpio_end, |
274 | int (*set_wake)(unsigned int, unsigned int)) | |
a58fbcd8 | 275 | { |
0807da59 EM |
276 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
277 | struct pxa_gpio_chip *chips; | |
a58fbcd8 | 278 | |
4aa78264 | 279 | chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); |
0807da59 EM |
280 | if (chips == NULL) { |
281 | pr_err("%s: failed to allocate GPIO chips\n", __func__); | |
282 | return -ENOMEM; | |
a58fbcd8 | 283 | } |
a58fbcd8 | 284 | |
0807da59 EM |
285 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
286 | struct gpio_chip *c = &chips[i].chip; | |
e3630db1 | 287 | |
0807da59 | 288 | sprintf(chips[i].label, "gpio-%d", i); |
157d2644 | 289 | chips[i].regbase = gpio_reg_base + BANK_OFF(i); |
b95ace54 | 290 | chips[i].set_wake = set_wake; |
0807da59 EM |
291 | |
292 | c->base = gpio; | |
293 | c->label = chips[i].label; | |
294 | ||
295 | c->direction_input = pxa_gpio_direction_input; | |
296 | c->direction_output = pxa_gpio_direction_output; | |
297 | c->get = pxa_gpio_get; | |
298 | c->set = pxa_gpio_set; | |
4929f5a8 | 299 | c->to_irq = pxa_gpio_to_irq; |
0807da59 EM |
300 | |
301 | /* number of GPIOs on last bank may be less than 32 */ | |
302 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; | |
303 | gpiochip_add(c); | |
304 | } | |
305 | pxa_gpio_chips = chips; | |
306 | return 0; | |
307 | } | |
e3630db1 | 308 | |
a8f6faeb EM |
309 | /* Update only those GRERx and GFERx edge detection register bits if those |
310 | * bits are set in c->irq_mask | |
311 | */ | |
312 | static inline void update_edge_detect(struct pxa_gpio_chip *c) | |
313 | { | |
314 | uint32_t grer, gfer; | |
315 | ||
df664d20 HZ |
316 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
317 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; | |
a8f6faeb EM |
318 | grer |= c->irq_edge_rise & c->irq_mask; |
319 | gfer |= c->irq_edge_fall & c->irq_mask; | |
df664d20 HZ |
320 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
321 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
a8f6faeb EM |
322 | } |
323 | ||
a3f4c927 | 324 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
e3630db1 | 325 | { |
0807da59 | 326 | struct pxa_gpio_chip *c; |
4929f5a8 | 327 | int gpio = pxa_irq_to_gpio(d->irq); |
0807da59 | 328 | unsigned long gpdr, mask = GPIO_bit(gpio); |
e3630db1 | 329 | |
a065685d | 330 | c = gpio_to_pxachip(gpio); |
e3630db1 | 331 | |
332 | if (type == IRQ_TYPE_PROBE) { | |
333 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
334 | * GPIOs set to alternate function or to output during probe | |
335 | */ | |
0807da59 | 336 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
e3630db1 | 337 | return 0; |
689c04a3 | 338 | |
339 | if (__gpio_is_occupied(gpio)) | |
e3630db1 | 340 | return 0; |
689c04a3 | 341 | |
e3630db1 | 342 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
343 | } | |
344 | ||
df664d20 | 345 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
0807da59 | 346 | |
067455aa | 347 | if (__gpio_is_inverted(gpio)) |
df664d20 | 348 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
067455aa | 349 | else |
df664d20 | 350 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
e3630db1 | 351 | |
352 | if (type & IRQ_TYPE_EDGE_RISING) | |
0807da59 | 353 | c->irq_edge_rise |= mask; |
e3630db1 | 354 | else |
0807da59 | 355 | c->irq_edge_rise &= ~mask; |
e3630db1 | 356 | |
357 | if (type & IRQ_TYPE_EDGE_FALLING) | |
0807da59 | 358 | c->irq_edge_fall |= mask; |
e3630db1 | 359 | else |
0807da59 | 360 | c->irq_edge_fall &= ~mask; |
e3630db1 | 361 | |
a8f6faeb | 362 | update_edge_detect(c); |
e3630db1 | 363 | |
a3f4c927 | 364 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
e3630db1 | 365 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
366 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
367 | return 0; | |
368 | } | |
369 | ||
e3630db1 | 370 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
371 | { | |
0807da59 EM |
372 | struct pxa_gpio_chip *c; |
373 | int loop, gpio, gpio_base, n; | |
374 | unsigned long gedr; | |
e3630db1 | 375 | |
376 | do { | |
e3630db1 | 377 | loop = 0; |
0807da59 EM |
378 | for_each_gpio_chip(gpio, c) { |
379 | gpio_base = c->chip.base; | |
380 | ||
df664d20 | 381 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
0807da59 | 382 | gedr = gedr & c->irq_mask; |
df664d20 | 383 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
e3630db1 | 384 | |
0807da59 EM |
385 | n = find_first_bit(&gedr, BITS_PER_LONG); |
386 | while (n < BITS_PER_LONG) { | |
387 | loop = 1; | |
e3630db1 | 388 | |
0807da59 EM |
389 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
390 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); | |
391 | } | |
e3630db1 | 392 | } |
393 | } while (loop); | |
394 | } | |
395 | ||
a3f4c927 | 396 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
e3630db1 | 397 | { |
4929f5a8 | 398 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 399 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 | 400 | |
df664d20 | 401 | writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); |
e3630db1 | 402 | } |
403 | ||
a3f4c927 | 404 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
e3630db1 | 405 | { |
4929f5a8 | 406 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 407 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 EM |
408 | uint32_t grer, gfer; |
409 | ||
410 | c->irq_mask &= ~GPIO_bit(gpio); | |
411 | ||
df664d20 HZ |
412 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); |
413 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); | |
414 | writel_relaxed(grer, c->regbase + GRER_OFFSET); | |
415 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
e3630db1 | 416 | } |
417 | ||
b95ace54 RJ |
418 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
419 | { | |
420 | int gpio = pxa_irq_to_gpio(d->irq); | |
421 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); | |
422 | ||
423 | if (c->set_wake) | |
424 | return c->set_wake(gpio, on); | |
425 | else | |
426 | return 0; | |
427 | } | |
428 | ||
a3f4c927 | 429 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
e3630db1 | 430 | { |
4929f5a8 | 431 | int gpio = pxa_irq_to_gpio(d->irq); |
a065685d | 432 | struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); |
0807da59 EM |
433 | |
434 | c->irq_mask |= GPIO_bit(gpio); | |
a8f6faeb | 435 | update_edge_detect(c); |
e3630db1 | 436 | } |
437 | ||
438 | static struct irq_chip pxa_muxed_gpio_chip = { | |
439 | .name = "GPIO", | |
a3f4c927 LB |
440 | .irq_ack = pxa_ack_muxed_gpio, |
441 | .irq_mask = pxa_mask_muxed_gpio, | |
442 | .irq_unmask = pxa_unmask_muxed_gpio, | |
443 | .irq_set_type = pxa_gpio_irq_type, | |
b95ace54 | 444 | .irq_set_wake = pxa_gpio_set_wake, |
e3630db1 | 445 | }; |
446 | ||
478e223c HZ |
447 | static int pxa_gpio_nums(void) |
448 | { | |
449 | int count = 0; | |
450 | ||
451 | #ifdef CONFIG_ARCH_PXA | |
452 | if (cpu_is_pxa25x()) { | |
453 | #ifdef CONFIG_CPU_PXA26x | |
454 | count = 89; | |
455 | gpio_type = PXA26X_GPIO; | |
456 | #elif defined(CONFIG_PXA25x) | |
457 | count = 84; | |
458 | gpio_type = PXA26X_GPIO; | |
459 | #endif /* CONFIG_CPU_PXA26x */ | |
460 | } else if (cpu_is_pxa27x()) { | |
461 | count = 120; | |
462 | gpio_type = PXA27X_GPIO; | |
463 | } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) { | |
464 | count = 191; | |
465 | gpio_type = PXA93X_GPIO; | |
466 | } else if (cpu_is_pxa3xx()) { | |
467 | count = 127; | |
468 | gpio_type = PXA3XX_GPIO; | |
469 | } | |
470 | #endif /* CONFIG_ARCH_PXA */ | |
471 | ||
472 | #ifdef CONFIG_ARCH_MMP | |
473 | if (cpu_is_pxa168() || cpu_is_pxa910()) { | |
474 | count = 127; | |
475 | gpio_type = MMP_GPIO; | |
476 | } else if (cpu_is_mmp2()) { | |
477 | count = 191; | |
478 | gpio_type = MMP2_GPIO; | |
479 | } | |
480 | #endif /* CONFIG_ARCH_MMP */ | |
481 | return count; | |
482 | } | |
483 | ||
157d2644 | 484 | static int __devinit pxa_gpio_probe(struct platform_device *pdev) |
e3630db1 | 485 | { |
0807da59 | 486 | struct pxa_gpio_chip *c; |
157d2644 | 487 | struct resource *res; |
389eda15 | 488 | struct clk *clk; |
b95ace54 | 489 | struct pxa_gpio_platform_data *info; |
389eda15 | 490 | int gpio, irq, ret; |
157d2644 | 491 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
e3630db1 | 492 | |
478e223c HZ |
493 | pxa_last_gpio = pxa_gpio_nums(); |
494 | if (!pxa_last_gpio) | |
157d2644 HZ |
495 | return -EINVAL; |
496 | ||
497 | irq0 = platform_get_irq_byname(pdev, "gpio0"); | |
498 | irq1 = platform_get_irq_byname(pdev, "gpio1"); | |
499 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); | |
500 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) | |
501 | || (irq_mux <= 0)) | |
502 | return -EINVAL; | |
503 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
504 | if (!res) | |
505 | return -EINVAL; | |
506 | gpio_reg_base = ioremap(res->start, resource_size(res)); | |
507 | if (!gpio_reg_base) | |
508 | return -EINVAL; | |
509 | ||
510 | if (irq0 > 0) | |
511 | gpio_offset = 2; | |
e3630db1 | 512 | |
389eda15 HZ |
513 | clk = clk_get(&pdev->dev, NULL); |
514 | if (IS_ERR(clk)) { | |
515 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", | |
516 | PTR_ERR(clk)); | |
517 | iounmap(gpio_reg_base); | |
518 | return PTR_ERR(clk); | |
519 | } | |
520 | ret = clk_prepare(clk); | |
521 | if (ret) { | |
522 | clk_put(clk); | |
523 | iounmap(gpio_reg_base); | |
524 | return ret; | |
525 | } | |
526 | ret = clk_enable(clk); | |
527 | if (ret) { | |
528 | clk_unprepare(clk); | |
529 | clk_put(clk); | |
530 | iounmap(gpio_reg_base); | |
531 | return ret; | |
532 | } | |
533 | ||
0807da59 | 534 | /* Initialize GPIO chips */ |
b95ace54 RJ |
535 | info = dev_get_platdata(&pdev->dev); |
536 | pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); | |
0807da59 | 537 | |
e3630db1 | 538 | /* clear all GPIO edge detects */ |
0807da59 | 539 | for_each_gpio_chip(gpio, c) { |
df664d20 HZ |
540 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
541 | writel_relaxed(0, c->regbase + GRER_OFFSET); | |
542 | writel_relaxed(~0,c->regbase + GEDR_OFFSET); | |
be24168f HZ |
543 | /* unmask GPIO edge detect for AP side */ |
544 | if (gpio_is_mmp_type(gpio_type)) | |
545 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); | |
e3630db1 | 546 | } |
547 | ||
87c49e20 HZ |
548 | #ifdef CONFIG_ARCH_PXA |
549 | irq = gpio_to_irq(0); | |
550 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
551 | handle_edge_irq); | |
552 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
553 | irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); | |
554 | ||
555 | irq = gpio_to_irq(1); | |
556 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
557 | handle_edge_irq); | |
558 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
559 | irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); | |
560 | #endif | |
561 | ||
157d2644 HZ |
562 | for (irq = gpio_to_irq(gpio_offset); |
563 | irq <= gpio_to_irq(pxa_last_gpio); irq++) { | |
f38c02f3 TG |
564 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
565 | handle_edge_irq); | |
e3630db1 | 566 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
567 | } | |
568 | ||
157d2644 HZ |
569 | irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); |
570 | return 0; | |
571 | } | |
572 | ||
573 | static struct platform_driver pxa_gpio_driver = { | |
574 | .probe = pxa_gpio_probe, | |
575 | .driver = { | |
576 | .name = "pxa-gpio", | |
577 | }, | |
578 | }; | |
579 | ||
580 | static int __init pxa_gpio_init(void) | |
581 | { | |
582 | return platform_driver_register(&pxa_gpio_driver); | |
e3630db1 | 583 | } |
157d2644 | 584 | postcore_initcall(pxa_gpio_init); |
663707c1 | 585 | |
586 | #ifdef CONFIG_PM | |
2eaa03b5 | 587 | static int pxa_gpio_suspend(void) |
663707c1 | 588 | { |
0807da59 EM |
589 | struct pxa_gpio_chip *c; |
590 | int gpio; | |
663707c1 | 591 | |
0807da59 | 592 | for_each_gpio_chip(gpio, c) { |
df664d20 HZ |
593 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
594 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); | |
595 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); | |
596 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); | |
663707c1 | 597 | |
598 | /* Clear GPIO transition detect bits */ | |
df664d20 | 599 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
663707c1 | 600 | } |
601 | return 0; | |
602 | } | |
603 | ||
2eaa03b5 | 604 | static void pxa_gpio_resume(void) |
663707c1 | 605 | { |
0807da59 EM |
606 | struct pxa_gpio_chip *c; |
607 | int gpio; | |
663707c1 | 608 | |
0807da59 | 609 | for_each_gpio_chip(gpio, c) { |
663707c1 | 610 | /* restore level with set/clear */ |
df664d20 HZ |
611 | writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET); |
612 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); | |
663707c1 | 613 | |
df664d20 HZ |
614 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
615 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); | |
616 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); | |
663707c1 | 617 | } |
663707c1 | 618 | } |
619 | #else | |
620 | #define pxa_gpio_suspend NULL | |
621 | #define pxa_gpio_resume NULL | |
622 | #endif | |
623 | ||
2eaa03b5 | 624 | struct syscore_ops pxa_gpio_syscore_ops = { |
663707c1 | 625 | .suspend = pxa_gpio_suspend, |
626 | .resume = pxa_gpio_resume, | |
627 | }; | |
157d2644 HZ |
628 | |
629 | static int __init pxa_gpio_sysinit(void) | |
630 | { | |
631 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
632 | return 0; | |
633 | } | |
634 | postcore_initcall(pxa_gpio_sysinit); |