[deliverable/linux.git] / drivers / gpio / gpio-pxa.c

/*
 *  linux/arch/arm/plat-pxa/gpio.c
 *
 *  Generic PXA GPIO handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/slab.h>

#include <mach/irqs.h>

/*
 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
 * one set of registers. The register offsets are organized below:
 *
 *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
 *
 * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
 *
 * NOTE:
 *   BANK 3 is only available on PXA27x and later processors.
 *   BANK 4 and 5 are only available on PXA935
 */

#define GPLR_OFFSET	0x00
#define GPDR_OFFSET	0x0C
#define GPSR_OFFSET	0x18
#define GPCR_OFFSET	0x24
#define GRER_OFFSET	0x30
#define GFER_OFFSET	0x3C
#define GEDR_OFFSET	0x48
#define GAFR_OFFSET	0x54
#define ED_MASK_OFFSET	0x9C	/* GPIO edge detection for AP side */

#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))

int pxa_last_gpio;
static int irq_base;

#ifdef CONFIG_OF
static struct irq_domain *domain;
#endif

struct pxa_gpio_chip {
	struct gpio_chip chip;
	void __iomem	*regbase;
	char label[10];

	unsigned long	irq_mask;
	unsigned long	irq_edge_rise;
	unsigned long	irq_edge_fall;
	int (*set_wake)(unsigned int gpio, unsigned int on);

#ifdef CONFIG_PM
	unsigned long	saved_gplr;
	unsigned long	saved_gpdr;
	unsigned long	saved_grer;
	unsigned long	saved_gfer;
#endif
};

enum {
	PXA25X_GPIO = 0,
	PXA26X_GPIO,
	PXA27X_GPIO,
	PXA3XX_GPIO,
	PXA93X_GPIO,
	MMP_GPIO = 0x10,
};

static DEFINE_SPINLOCK(gpio_lock);
static struct pxa_gpio_chip *pxa_gpio_chips;
static int gpio_type;
static void __iomem *gpio_reg_base;

#define for_each_gpio_chip(i, c)			\
	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)

static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
{
	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
}

static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
{
	return &pxa_gpio_chips[gpio_to_bank(gpio)];
}

static inline int gpio_is_pxa_type(int type)
{
	return (type & MMP_GPIO) == 0;
}

static inline int gpio_is_mmp_type(int type)
{
	return (type & MMP_GPIO) != 0;
}

/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 */
static inline int __gpio_is_inverted(int gpio)
{
	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
		return 1;
	return 0;
}

/*
 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 * function of a GPIO, and GPDRx cannot be altered once configured. It
 * is attributed as "occupied" here (I know this terminology isn't
 * accurate, you are welcome to propose a better one :-)
 */
static inline int __gpio_is_occupied(unsigned gpio)
{
	struct pxa_gpio_chip *pxachip;
	void __iomem *base;
	unsigned long gafr = 0, gpdr = 0;
	int ret, af = 0, dir = 0;

	pxachip = gpio_to_pxachip(gpio);
	base = gpio_chip_base(&pxachip->chip);
	gpdr = readl_relaxed(base + GPDR_OFFSET);

	switch (gpio_type) {
	case PXA25X_GPIO:
	case PXA26X_GPIO:
	case PXA27X_GPIO:
		gafr = readl_relaxed(base + GAFR_OFFSET);
		af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
		dir = gpdr & GPIO_bit(gpio);

		if (__gpio_is_inverted(gpio))
			ret = (af != 1) || (dir == 0);
		else
			ret = (af != 0) || (dir != 0);
		break;
	default:
		ret = gpdr & GPIO_bit(gpio);
		break;
	}
	return ret;
}

static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return chip->base + offset + irq_base;
}

int pxa_irq_to_gpio(int irq)
{
	return irq - irq_base;
}

static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t value, mask = 1 << offset;
	unsigned long flags;

	spin_lock_irqsave(&gpio_lock, flags);

	value = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		value |= mask;
	else
		value &= ~mask;
	writel_relaxed(value, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_direction_output(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t tmp, mask = 1 << offset;
	unsigned long flags;

	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));

	spin_lock_irqsave(&gpio_lock, flags);

	tmp = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		tmp &= ~mask;
	else
		tmp |= mask;
	writel_relaxed(tmp, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
}

static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	writel_relaxed(1 << offset, gpio_chip_base(chip) +
				(value ? GPSR_OFFSET : GPCR_OFFSET));
}

static int __devinit pxa_init_gpio_chip(int gpio_end,
					int (*set_wake)(unsigned int, unsigned int))
{
	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
	struct pxa_gpio_chip *chips;

	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
	if (chips == NULL) {
		pr_err("%s: failed to allocate GPIO chips\n", __func__);
		return -ENOMEM;
	}

	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
		struct gpio_chip *c = &chips[i].chip;

		sprintf(chips[i].label, "gpio-%d", i);
		chips[i].regbase = gpio_reg_base + BANK_OFF(i);
		chips[i].set_wake = set_wake;

		c->base  = gpio;
		c->label = chips[i].label;

		c->direction_input  = pxa_gpio_direction_input;
		c->direction_output = pxa_gpio_direction_output;
		c->get = pxa_gpio_get;
		c->set = pxa_gpio_set;
		c->to_irq = pxa_gpio_to_irq;

		/* number of GPIOs on last bank may be less than 32 */
		c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
		gpiochip_add(c);
	}
	pxa_gpio_chips = chips;
	return 0;
}

/* Update only those GRERx and GFERx edge detection register bits if those
 * bits are set in c->irq_mask
 */
static inline void update_edge_detect(struct pxa_gpio_chip *c)
{
	uint32_t grer, gfer;

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
	grer |= c->irq_edge_rise & c->irq_mask;
	gfer |= c->irq_edge_fall & c->irq_mask;
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct pxa_gpio_chip *c;
	int gpio = pxa_irq_to_gpio(d->irq);
	unsigned long gpdr, mask = GPIO_bit(gpio);

	c = gpio_to_pxachip(gpio);

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		 * GPIOs set to alternate function or to output during probe
		 */
		if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
			return 0;

		if (__gpio_is_occupied(gpio))
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);

	if (__gpio_is_inverted(gpio))
		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
	else
		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);

	if (type & IRQ_TYPE_EDGE_RISING)
		c->irq_edge_rise |= mask;
	else
		c->irq_edge_rise &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		c->irq_edge_fall |= mask;
	else
		c->irq_edge_fall &= ~mask;

	update_edge_detect(c);

	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	return 0;
}

static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pxa_gpio_chip *c;
	int loop, gpio, gpio_base, n;
	unsigned long gedr;

	do {
		loop = 0;
		for_each_gpio_chip(gpio, c) {
			gpio_base = c->chip.base;

			gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
			gedr = gedr & c->irq_mask;
			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);

			n = find_first_bit(&gedr, BITS_PER_LONG);
			while (n < BITS_PER_LONG) {
				loop = 1;

				generic_handle_irq(gpio_to_irq(gpio_base + n));
				n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
			}
		}
	} while (loop);
}

static void pxa_ack_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
}

static void pxa_mask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
	uint32_t grer, gfer;

	c->irq_mask &= ~GPIO_bit(gpio);

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	if (c->set_wake)
		return c->set_wake(gpio, on);
	else
		return 0;
}

static void pxa_unmask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	c->irq_mask |= GPIO_bit(gpio);
	update_edge_detect(c);
}

static struct irq_chip pxa_muxed_gpio_chip = {
	.name		= "GPIO",
	.irq_ack	= pxa_ack_muxed_gpio,
	.irq_mask	= pxa_mask_muxed_gpio,
	.irq_unmask	= pxa_unmask_muxed_gpio,
	.irq_set_type	= pxa_gpio_irq_type,
	.irq_set_wake	= pxa_gpio_set_wake,
};

static int pxa_gpio_nums(void)
{
	int count = 0;

#ifdef CONFIG_ARCH_PXA
	if (cpu_is_pxa25x()) {
#ifdef CONFIG_CPU_PXA26x
		count = 89;
		gpio_type = PXA26X_GPIO;
#elif defined(CONFIG_PXA25x)
		count = 84;
		gpio_type = PXA26X_GPIO;
#endif /* CONFIG_CPU_PXA26x */
	} else if (cpu_is_pxa27x()) {
		count = 120;
		gpio_type = PXA27X_GPIO;
	} else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
		count = 191;
		gpio_type = PXA93X_GPIO;
	} else if (cpu_is_pxa3xx()) {
		count = 127;
		gpio_type = PXA3XX_GPIO;
	}
#endif /* CONFIG_ARCH_PXA */

#ifdef CONFIG_ARCH_MMP
	if (cpu_is_pxa168() || cpu_is_pxa910()) {
		count = 127;
		gpio_type = MMP_GPIO;
	} else if (cpu_is_mmp2()) {
		count = 191;
		gpio_type = MMP_GPIO;
	}
#endif /* CONFIG_ARCH_MMP */
	return count;
}

static struct of_device_id pxa_gpio_dt_ids[] = {
	{ .compatible = "mrvl,pxa-gpio" },
	{ .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
	{}
};

static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	return 0;
}

const struct irq_domain_ops pxa_irq_domain_ops = {
	.map	= pxa_irq_domain_map,
};

#ifdef CONFIG_OF
static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
{
	int ret, nr_banks, nr_gpios;
	struct device_node *prev, *next, *np = pdev->dev.of_node;
	const struct of_device_id *of_id =
				of_match_device(pxa_gpio_dt_ids, &pdev->dev);

	if (!of_id) {
		dev_err(&pdev->dev, "Failed to find gpio controller\n");
		return -EFAULT;
	}
	gpio_type = (int)of_id->data;

	next = of_get_next_child(np, NULL);
	prev = next;
	if (!next) {
		dev_err(&pdev->dev, "Failed to find child gpio node\n");
		ret = -EINVAL;
		goto err;
	}
	for (nr_banks = 1; ; nr_banks++) {
		next = of_get_next_child(np, prev);
		if (!next)
			break;
		prev = next;
	}
	of_node_put(prev);
	nr_gpios = nr_banks << 5;
	pxa_last_gpio = nr_gpios - 1;

	irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
	if (irq_base < 0) {
		dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
		goto err;
	}
	domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
				       &pxa_irq_domain_ops, NULL);
	return 0;
err:
	iounmap(gpio_reg_base);
	return ret;
}
#else
#define pxa_gpio_probe_dt(pdev)		(-1)
#endif

static int __devinit pxa_gpio_probe(struct platform_device *pdev)
{
	struct pxa_gpio_chip *c;
	struct resource *res;
	struct clk *clk;
	struct pxa_gpio_platform_data *info;
	int gpio, irq, ret, use_of = 0;
	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;

	ret = pxa_gpio_probe_dt(pdev);
	if (ret < 0) {
		pxa_last_gpio = pxa_gpio_nums();
#ifdef CONFIG_ARCH_PXA
		if (gpio_is_pxa_type(gpio_type))
			irq_base = PXA_GPIO_TO_IRQ(0);
#endif
#ifdef CONFIG_ARCH_MMP
		if (gpio_is_mmp_type(gpio_type))
			irq_base = MMP_GPIO_TO_IRQ(0);
#endif
	} else {
		use_of = 1;
	}

	if (!pxa_last_gpio)
		return -EINVAL;

	irq0 = platform_get_irq_byname(pdev, "gpio0");
	irq1 = platform_get_irq_byname(pdev, "gpio1");
	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
		|| (irq_mux <= 0))
		return -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;
	gpio_reg_base = ioremap(res->start, resource_size(res));
	if (!gpio_reg_base)
		return -EINVAL;

	if (irq0 > 0)
		gpio_offset = 2;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
			PTR_ERR(clk));
		iounmap(gpio_reg_base);
		return PTR_ERR(clk);
	}
	ret = clk_prepare(clk);
	if (ret) {
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}
	ret = clk_enable(clk);
	if (ret) {
		clk_unprepare(clk);
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}

	/* Initialize GPIO chips */
	info = dev_get_platdata(&pdev->dev);
	pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);

	/* clear all GPIO edge detects */
	for_each_gpio_chip(gpio, c) {
		writel_relaxed(0, c->regbase + GFER_OFFSET);
		writel_relaxed(0, c->regbase + GRER_OFFSET);
		writel_relaxed(~0,c->regbase + GEDR_OFFSET);
		/* unmask GPIO edge detect for AP side */
		if (gpio_is_mmp_type(gpio_type))
			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
	}

	if (!use_of) {
#ifdef CONFIG_ARCH_PXA
		irq = gpio_to_irq(0);
		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);

		irq = gpio_to_irq(1);
		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
#endif

		for (irq  = gpio_to_irq(gpio_offset);
			irq <= gpio_to_irq(pxa_last_gpio); irq++) {
			irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
						 handle_edge_irq);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}

	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	return 0;
}

static struct platform_driver pxa_gpio_driver = {
	.probe		= pxa_gpio_probe,
	.driver		= {
		.name	= "pxa-gpio",
		.of_match_table = pxa_gpio_dt_ids,
	},
};

static int __init pxa_gpio_init(void)
{
	return platform_driver_register(&pxa_gpio_driver);
}
postcore_initcall(pxa_gpio_init);

#ifdef CONFIG_PM
static int pxa_gpio_suspend(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
		c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
		c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
		c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);

		/* Clear GPIO transition detect bits */
		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
	}
	return 0;
}

static void pxa_gpio_resume(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		/* restore level with set/clear */
		writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);

		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
	}
}
#else
#define pxa_gpio_suspend	NULL
#define pxa_gpio_resume		NULL
#endif

struct syscore_ops pxa_gpio_syscore_ops = {
	.suspend	= pxa_gpio_suspend,
	.resume		= pxa_gpio_resume,
};

static int __init pxa_gpio_sysinit(void)
{
	register_syscore_ops(&pxa_gpio_syscore_ops);
	return 0;
}
postcore_initcall(pxa_gpio_sysinit);
Commit	Line	Data
1c44f5f1	1	/*
38f539a6	2	* linux/arch/arm/plat-pxa/gpio.c
1c44f5f1 PZ	3	*
	4	* Generic PXA GPIO handling
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Jun 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
7a4d5079	14	#include <linux/module.h>
389eda15 HZ	15	#include <linux/clk.h>
389eda15 HZ	16	#include <linux/err.h>
2f8163ba	17	#include <linux/gpio.h>
157d2644	18	#include <linux/gpio-pxa.h>
1c44f5f1	19	#include <linux/init.h>
e3630db1	20	#include <linux/irq.h>
7a4d5079	21	#include <linux/irqdomain.h>
fced80c7	22	#include <linux/io.h>
7a4d5079 HZ	23	#include <linux/of.h>
7a4d5079 HZ	24	#include <linux/of_device.h>
157d2644	25	#include <linux/platform_device.h>
2eaa03b5	26	#include <linux/syscore_ops.h>
4aa78264	27	#include <linux/slab.h>
1c44f5f1	28
feefe73f RH	29	#include <mach/irqs.h>
feefe73f RH	30
157d2644 HZ	31	/*
	32	* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
	33	* one set of registers. The register offsets are organized below:
	34	*
	35	* GPLR GPDR GPSR GPCR GRER GFER GEDR
	36	* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
	37	* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
	38	* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
	39	*
	40	* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
	41	* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
	42	* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
	43	*
	44	* NOTE:
	45	* BANK 3 is only available on PXA27x and later processors.
	46	* BANK 4 and 5 are only available on PXA935
	47	*/
	48
	49	#define GPLR_OFFSET 0x00
	50	#define GPDR_OFFSET 0x0C
	51	#define GPSR_OFFSET 0x18
	52	#define GPCR_OFFSET 0x24
	53	#define GRER_OFFSET 0x30
	54	#define GFER_OFFSET 0x3C
	55	#define GEDR_OFFSET 0x48
	56	#define GAFR_OFFSET 0x54
be24168f	57	#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
157d2644 HZ	58
157d2644 HZ	59	#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
1c44f5f1	60
3b8e285c	61	int pxa_last_gpio;
9450be76	62	static int irq_base;
3b8e285c	63
7a4d5079 HZ	64	#ifdef CONFIG_OF
	65	static struct irq_domain *domain;
	66	#endif
	67
1c44f5f1 PZ	68	struct pxa_gpio_chip {
1c44f5f1 PZ	69	struct gpio_chip chip;
0807da59 EM	70	void __iomem *regbase;
	71	char label[10];
	72
	73	unsigned long irq_mask;
	74	unsigned long irq_edge_rise;
	75	unsigned long irq_edge_fall;
b95ace54	76	int (*set_wake)(unsigned int gpio, unsigned int on);
0807da59 EM	77
	78	#ifdef CONFIG_PM
	79	unsigned long saved_gplr;
	80	unsigned long saved_gpdr;
	81	unsigned long saved_grer;
	82	unsigned long saved_gfer;
	83	#endif
1c44f5f1 PZ	84	};
1c44f5f1 PZ	85
4929f5a8 HZ	86	enum {
	87	PXA25X_GPIO = 0,
	88	PXA26X_GPIO,
	89	PXA27X_GPIO,
	90	PXA3XX_GPIO,
	91	PXA93X_GPIO,
	92	MMP_GPIO = 0x10,
4929f5a8 HZ	93	};
4929f5a8 HZ	94
0807da59 EM	95	static DEFINE_SPINLOCK(gpio_lock);
0807da59 EM	96	static struct pxa_gpio_chip *pxa_gpio_chips;
4929f5a8	97	static int gpio_type;
157d2644	98	static void __iomem *gpio_reg_base;
0807da59 EM	99
	100	#define for_each_gpio_chip(i, c) \
	101	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
	102
	103	static inline void __iomem gpio_chip_base(struct gpio_chip c)
	104	{
	105	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
	106	}
	107
a065685d	108	static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
0807da59 EM	109	{
	110	return &pxa_gpio_chips[gpio_to_bank(gpio)];
	111	}
	112
4929f5a8 HZ	113	static inline int gpio_is_pxa_type(int type)
	114	{
	115	return (type & MMP_GPIO) == 0;
	116	}
	117
	118	static inline int gpio_is_mmp_type(int type)
	119	{
	120	return (type & MMP_GPIO) != 0;
	121	}
	122
157d2644 HZ	123	/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
	124	* as well as their Alternate Function value being '1' for GPIO in GAFRx.
	125	*/
	126	static inline int __gpio_is_inverted(int gpio)
	127	{
	128	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
	129	return 1;
	130	return 0;
	131	}
	132
	133	/*
	134	* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
	135	* function of a GPIO, and GPDRx cannot be altered once configured. It
	136	* is attributed as "occupied" here (I know this terminology isn't
	137	* accurate, you are welcome to propose a better one :-)
	138	*/
	139	static inline int __gpio_is_occupied(unsigned gpio)
	140	{
	141	struct pxa_gpio_chip *pxachip;
	142	void __iomem *base;
	143	unsigned long gafr = 0, gpdr = 0;
	144	int ret, af = 0, dir = 0;
	145
	146	pxachip = gpio_to_pxachip(gpio);
	147	base = gpio_chip_base(&pxachip->chip);
	148	gpdr = readl_relaxed(base + GPDR_OFFSET);
	149
	150	switch (gpio_type) {
	151	case PXA25X_GPIO:
	152	case PXA26X_GPIO:
	153	case PXA27X_GPIO:
	154	gafr = readl_relaxed(base + GAFR_OFFSET);
	155	af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
	156	dir = gpdr & GPIO_bit(gpio);
	157
	158	if (__gpio_is_inverted(gpio))
	159	ret = (af != 1) \|\| (dir == 0);
	160	else
	161	ret = (af != 0) \|\| (dir != 0);
	162	break;
	163	default:
	164	ret = gpdr & GPIO_bit(gpio);
	165	break;
	166	}
	167	return ret;
	168	}
	169
4929f5a8 HZ	170	static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
4929f5a8 HZ	171	{
9450be76	172	return chip->base + offset + irq_base;
4929f5a8 HZ	173	}
	174
	175	int pxa_irq_to_gpio(int irq)
	176	{
9450be76	177	return irq - irq_base;
4929f5a8 HZ	178	}
4929f5a8 HZ	179
1c44f5f1 PZ	180	static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	181	{
0807da59 EM	182	void __iomem *base = gpio_chip_base(chip);
	183	uint32_t value, mask = 1 << offset;
	184	unsigned long flags;
	185
	186	spin_lock_irqsave(&gpio_lock, flags);
	187
df664d20	188	value = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	189	if (__gpio_is_inverted(chip->base + offset))
	190	value \|= mask;
	191	else
	192	value &= ~mask;
df664d20	193	writel_relaxed(value, base + GPDR_OFFSET);
1c44f5f1	194
0807da59	195	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	196	return 0;
	197	}
	198
	199	static int pxa_gpio_direction_output(struct gpio_chip *chip,
0807da59	200	unsigned offset, int value)
1c44f5f1	201	{
0807da59 EM	202	void __iomem *base = gpio_chip_base(chip);
	203	uint32_t tmp, mask = 1 << offset;
	204	unsigned long flags;
	205
df664d20	206	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0807da59 EM	207
	208	spin_lock_irqsave(&gpio_lock, flags);
	209
df664d20	210	tmp = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	211	if (__gpio_is_inverted(chip->base + offset))
	212	tmp &= ~mask;
	213	else
	214	tmp \|= mask;
df664d20	215	writel_relaxed(tmp, base + GPDR_OFFSET);
1c44f5f1	216
0807da59	217	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	218	return 0;
	219	}
	220
1c44f5f1 PZ	221	static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	222	{
df664d20	223	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
1c44f5f1 PZ	224	}
1c44f5f1 PZ	225
1c44f5f1 PZ	226	static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1c44f5f1 PZ	227	{
df664d20	228	writel_relaxed(1 << offset, gpio_chip_base(chip) +
0807da59	229	(value ? GPSR_OFFSET : GPCR_OFFSET));
1c44f5f1 PZ	230	}
1c44f5f1 PZ	231
b95ace54 RJ	232	static int __devinit pxa_init_gpio_chip(int gpio_end,
b95ace54 RJ	233	int (*set_wake)(unsigned int, unsigned int))
a58fbcd8	234	{
0807da59 EM	235	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
0807da59 EM	236	struct pxa_gpio_chip *chips;
a58fbcd8	237
4aa78264	238	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
0807da59 EM	239	if (chips == NULL) {
	240	pr_err("%s: failed to allocate GPIO chips\n", __func__);
	241	return -ENOMEM;
a58fbcd8	242	}
a58fbcd8	243
0807da59 EM	244	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
0807da59 EM	245	struct gpio_chip *c = &chips[i].chip;
e3630db1	246
0807da59	247	sprintf(chips[i].label, "gpio-%d", i);
157d2644	248	chips[i].regbase = gpio_reg_base + BANK_OFF(i);
b95ace54	249	chips[i].set_wake = set_wake;
0807da59 EM	250
	251	c->base = gpio;
	252	c->label = chips[i].label;
	253
	254	c->direction_input = pxa_gpio_direction_input;
	255	c->direction_output = pxa_gpio_direction_output;
	256	c->get = pxa_gpio_get;
	257	c->set = pxa_gpio_set;
4929f5a8	258	c->to_irq = pxa_gpio_to_irq;
0807da59 EM	259
	260	/* number of GPIOs on last bank may be less than 32 */
	261	c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
	262	gpiochip_add(c);
	263	}
	264	pxa_gpio_chips = chips;
	265	return 0;
	266	}
e3630db1	267
a8f6faeb EM	268	/* Update only those GRERx and GFERx edge detection register bits if those
	269	* bits are set in c->irq_mask
	270	*/
	271	static inline void update_edge_detect(struct pxa_gpio_chip *c)
	272	{
	273	uint32_t grer, gfer;
	274
df664d20 HZ	275	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
df664d20 HZ	276	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
a8f6faeb EM	277	grer \|= c->irq_edge_rise & c->irq_mask;
a8f6faeb EM	278	gfer \|= c->irq_edge_fall & c->irq_mask;
df664d20 HZ	279	writel_relaxed(grer, c->regbase + GRER_OFFSET);
df664d20 HZ	280	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
a8f6faeb EM	281	}
a8f6faeb EM	282
a3f4c927	283	static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
e3630db1	284	{
0807da59	285	struct pxa_gpio_chip *c;
4929f5a8	286	int gpio = pxa_irq_to_gpio(d->irq);
0807da59	287	unsigned long gpdr, mask = GPIO_bit(gpio);
e3630db1	288
a065685d	289	c = gpio_to_pxachip(gpio);
e3630db1	290
	291	if (type == IRQ_TYPE_PROBE) {
	292	/* Don't mess with enabled GPIOs using preconfigured edges or
	293	* GPIOs set to alternate function or to output during probe
	294	*/
0807da59	295	if ((c->irq_edge_rise \| c->irq_edge_fall) & GPIO_bit(gpio))
e3630db1	296	return 0;
689c04a3	297
689c04a3	298	if (__gpio_is_occupied(gpio))
e3630db1	299	return 0;
689c04a3	300
e3630db1	301	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	302	}
	303
df664d20	304	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0807da59	305
067455aa	306	if (__gpio_is_inverted(gpio))
df664d20	307	writel_relaxed(gpdr \| mask, c->regbase + GPDR_OFFSET);
067455aa	308	else
df664d20	309	writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
e3630db1	310
e3630db1	311	if (type & IRQ_TYPE_EDGE_RISING)
0807da59	312	c->irq_edge_rise \|= mask;
e3630db1	313	else
0807da59	314	c->irq_edge_rise &= ~mask;
e3630db1	315
e3630db1	316	if (type & IRQ_TYPE_EDGE_FALLING)
0807da59	317	c->irq_edge_fall \|= mask;
e3630db1	318	else
0807da59	319	c->irq_edge_fall &= ~mask;
e3630db1	320
a8f6faeb	321	update_edge_detect(c);
e3630db1	322
a3f4c927	323	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
e3630db1	324	((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
	325	((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	326	return 0;
	327	}
	328
e3630db1	329	static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
e3630db1	330	{
0807da59 EM	331	struct pxa_gpio_chip *c;
	332	int loop, gpio, gpio_base, n;
	333	unsigned long gedr;
e3630db1	334
e3630db1	335	do {
e3630db1	336	loop = 0;
0807da59 EM	337	for_each_gpio_chip(gpio, c) {
	338	gpio_base = c->chip.base;
	339
df664d20	340	gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0807da59	341	gedr = gedr & c->irq_mask;
df664d20	342	writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
e3630db1	343
0807da59 EM	344	n = find_first_bit(&gedr, BITS_PER_LONG);
	345	while (n < BITS_PER_LONG) {
	346	loop = 1;
e3630db1	347
0807da59 EM	348	generic_handle_irq(gpio_to_irq(gpio_base + n));
	349	n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
	350	}
e3630db1	351	}
	352	} while (loop);
	353	}
	354
a3f4c927	355	static void pxa_ack_muxed_gpio(struct irq_data *d)
e3630db1	356	{
4929f5a8	357	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	358	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59	359
df664d20	360	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
e3630db1	361	}
e3630db1	362
a3f4c927	363	static void pxa_mask_muxed_gpio(struct irq_data *d)
e3630db1	364	{
4929f5a8	365	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	366	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	367	uint32_t grer, gfer;
	368
	369	c->irq_mask &= ~GPIO_bit(gpio);
	370
df664d20 HZ	371	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	372	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	373	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	374	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
e3630db1	375	}
e3630db1	376
b95ace54 RJ	377	static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
	378	{
	379	int gpio = pxa_irq_to_gpio(d->irq);
	380	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
	381
	382	if (c->set_wake)
	383	return c->set_wake(gpio, on);
	384	else
	385	return 0;
	386	}
	387
a3f4c927	388	static void pxa_unmask_muxed_gpio(struct irq_data *d)
e3630db1	389	{
4929f5a8	390	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	391	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	392
0807da59 EM	393	c->irq_mask \|= GPIO_bit(gpio);
a8f6faeb	394	update_edge_detect(c);
e3630db1	395	}
	396
	397	static struct irq_chip pxa_muxed_gpio_chip = {
	398	.name = "GPIO",
a3f4c927 LB	399	.irq_ack = pxa_ack_muxed_gpio,
	400	.irq_mask = pxa_mask_muxed_gpio,
	401	.irq_unmask = pxa_unmask_muxed_gpio,
	402	.irq_set_type = pxa_gpio_irq_type,
b95ace54	403	.irq_set_wake = pxa_gpio_set_wake,
e3630db1	404	};
e3630db1	405
478e223c HZ	406	static int pxa_gpio_nums(void)
	407	{
	408	int count = 0;
	409
	410	#ifdef CONFIG_ARCH_PXA
	411	if (cpu_is_pxa25x()) {
	412	#ifdef CONFIG_CPU_PXA26x
	413	count = 89;
	414	gpio_type = PXA26X_GPIO;
	415	#elif defined(CONFIG_PXA25x)
	416	count = 84;
	417	gpio_type = PXA26X_GPIO;
	418	#endif /* CONFIG_CPU_PXA26x */
	419	} else if (cpu_is_pxa27x()) {
	420	count = 120;
	421	gpio_type = PXA27X_GPIO;
	422	} else if (cpu_is_pxa93x() \|\| cpu_is_pxa95x()) {
	423	count = 191;
	424	gpio_type = PXA93X_GPIO;
	425	} else if (cpu_is_pxa3xx()) {
	426	count = 127;
	427	gpio_type = PXA3XX_GPIO;
	428	}
	429	#endif /* CONFIG_ARCH_PXA */
	430
	431	#ifdef CONFIG_ARCH_MMP
	432	if (cpu_is_pxa168() \|\| cpu_is_pxa910()) {
	433	count = 127;
	434	gpio_type = MMP_GPIO;
	435	} else if (cpu_is_mmp2()) {
	436	count = 191;
7a4d5079	437	gpio_type = MMP_GPIO;
478e223c HZ	438	}
	439	#endif /* CONFIG_ARCH_MMP */
	440	return count;
	441	}
	442
7a4d5079 HZ	443	static struct of_device_id pxa_gpio_dt_ids[] = {
	444	{ .compatible = "mrvl,pxa-gpio" },
	445	{ .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
	446	{}
	447	};
	448
	449	static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
	450	irq_hw_number_t hw)
	451	{
	452	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	453	handle_edge_irq);
	454	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	455	return 0;
	456	}
	457
	458	const struct irq_domain_ops pxa_irq_domain_ops = {
	459	.map = pxa_irq_domain_map,
	460	};
	461
	462	#ifdef CONFIG_OF
	463	static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
	464	{
9450be76	465	int ret, nr_banks, nr_gpios;
7a4d5079 HZ	466	struct device_node prev, next, *np = pdev->dev.of_node;
	467	const struct of_device_id *of_id =
	468	of_match_device(pxa_gpio_dt_ids, &pdev->dev);
	469
	470	if (!of_id) {
	471	dev_err(&pdev->dev, "Failed to find gpio controller\n");
	472	return -EFAULT;
	473	}
	474	gpio_type = (int)of_id->data;
	475
	476	next = of_get_next_child(np, NULL);
	477	prev = next;
	478	if (!next) {
	479	dev_err(&pdev->dev, "Failed to find child gpio node\n");
	480	ret = -EINVAL;
	481	goto err;
	482	}
	483	for (nr_banks = 1; ; nr_banks++) {
	484	next = of_get_next_child(np, prev);
	485	if (!next)
	486	break;
	487	prev = next;
	488	}
	489	of_node_put(prev);
	490	nr_gpios = nr_banks << 5;
	491	pxa_last_gpio = nr_gpios - 1;
	492
	493	irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
	494	if (irq_base < 0) {
	495	dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
	496	goto err;
	497	}
	498	domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
	499	&pxa_irq_domain_ops, NULL);
	500	return 0;
	501	err:
	502	iounmap(gpio_reg_base);
	503	return ret;
	504	}
	505	#else
	506	#define pxa_gpio_probe_dt(pdev) (-1)
	507	#endif
	508
157d2644	509	static int __devinit pxa_gpio_probe(struct platform_device *pdev)
e3630db1	510	{
0807da59	511	struct pxa_gpio_chip *c;
157d2644	512	struct resource *res;
389eda15	513	struct clk *clk;
b95ace54	514	struct pxa_gpio_platform_data *info;
7a4d5079	515	int gpio, irq, ret, use_of = 0;
157d2644	516	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
e3630db1	517
7a4d5079	518	ret = pxa_gpio_probe_dt(pdev);
9450be76	519	if (ret < 0) {
7a4d5079	520	pxa_last_gpio = pxa_gpio_nums();
9450be76 DM	521	#ifdef CONFIG_ARCH_PXA
	522	if (gpio_is_pxa_type(gpio_type))
	523	irq_base = PXA_GPIO_TO_IRQ(0);
	524	#endif
	525	#ifdef CONFIG_ARCH_MMP
	526	if (gpio_is_mmp_type(gpio_type))
	527	irq_base = MMP_GPIO_TO_IRQ(0);
	528	#endif
	529	} else {
7a4d5079	530	use_of = 1;
9450be76 DM	531	}
9450be76 DM	532
478e223c	533	if (!pxa_last_gpio)
157d2644 HZ	534	return -EINVAL;
	535
	536	irq0 = platform_get_irq_byname(pdev, "gpio0");
	537	irq1 = platform_get_irq_byname(pdev, "gpio1");
	538	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	539	if ((irq0 > 0 && irq1 <= 0) \|\| (irq0 <= 0 && irq1 > 0)
	540	\|\| (irq_mux <= 0))
	541	return -EINVAL;
	542	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	543	if (!res)
	544	return -EINVAL;
	545	gpio_reg_base = ioremap(res->start, resource_size(res));
	546	if (!gpio_reg_base)
	547	return -EINVAL;
	548
	549	if (irq0 > 0)
	550	gpio_offset = 2;
e3630db1	551
389eda15 HZ	552	clk = clk_get(&pdev->dev, NULL);
	553	if (IS_ERR(clk)) {
	554	dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
	555	PTR_ERR(clk));
	556	iounmap(gpio_reg_base);
	557	return PTR_ERR(clk);
	558	}
	559	ret = clk_prepare(clk);
	560	if (ret) {
	561	clk_put(clk);
	562	iounmap(gpio_reg_base);
	563	return ret;
	564	}
	565	ret = clk_enable(clk);
	566	if (ret) {
	567	clk_unprepare(clk);
	568	clk_put(clk);
	569	iounmap(gpio_reg_base);
	570	return ret;
	571	}
	572
0807da59	573	/* Initialize GPIO chips */
b95ace54 RJ	574	info = dev_get_platdata(&pdev->dev);
b95ace54 RJ	575	pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
0807da59	576
e3630db1	577	/* clear all GPIO edge detects */
0807da59	578	for_each_gpio_chip(gpio, c) {
df664d20 HZ	579	writel_relaxed(0, c->regbase + GFER_OFFSET);
	580	writel_relaxed(0, c->regbase + GRER_OFFSET);
	581	writel_relaxed(~0,c->regbase + GEDR_OFFSET);
be24168f HZ	582	/* unmask GPIO edge detect for AP side */
	583	if (gpio_is_mmp_type(gpio_type))
	584	writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
e3630db1	585	}
e3630db1	586
7a4d5079	587	if (!use_of) {
87c49e20	588	#ifdef CONFIG_ARCH_PXA
7a4d5079 HZ	589	irq = gpio_to_irq(0);
	590	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	591	handle_edge_irq);
	592	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	593	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
87c49e20	594
7a4d5079	595	irq = gpio_to_irq(1);
f38c02f3 TG	596	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
f38c02f3 TG	597	handle_edge_irq);
e3630db1	598	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
7a4d5079 HZ	599	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
	600	#endif
	601
	602	for (irq = gpio_to_irq(gpio_offset);
	603	irq <= gpio_to_irq(pxa_last_gpio); irq++) {
	604	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	605	handle_edge_irq);
	606	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	607	}
e3630db1	608	}
e3630db1	609
157d2644 HZ	610	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	611	return 0;
	612	}
	613
	614	static struct platform_driver pxa_gpio_driver = {
	615	.probe = pxa_gpio_probe,
	616	.driver = {
	617	.name = "pxa-gpio",
7a4d5079	618	.of_match_table = pxa_gpio_dt_ids,
157d2644 HZ	619	},
	620	};
	621
	622	static int __init pxa_gpio_init(void)
	623	{
	624	return platform_driver_register(&pxa_gpio_driver);
e3630db1	625	}
157d2644	626	postcore_initcall(pxa_gpio_init);
663707c1	627
663707c1	628	#ifdef CONFIG_PM
2eaa03b5	629	static int pxa_gpio_suspend(void)
663707c1	630	{
0807da59 EM	631	struct pxa_gpio_chip *c;
0807da59 EM	632	int gpio;
663707c1	633
0807da59	634	for_each_gpio_chip(gpio, c) {
df664d20 HZ	635	c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
	636	c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
	637	c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
	638	c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
663707c1	639
663707c1	640	/* Clear GPIO transition detect bits */
df664d20	641	writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
663707c1	642	}
	643	return 0;
	644	}
	645
2eaa03b5	646	static void pxa_gpio_resume(void)
663707c1	647	{
0807da59 EM	648	struct pxa_gpio_chip *c;
0807da59 EM	649	int gpio;
663707c1	650
0807da59	651	for_each_gpio_chip(gpio, c) {
663707c1	652	/* restore level with set/clear */
df664d20 HZ	653	writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
df664d20 HZ	654	writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
663707c1	655
df664d20 HZ	656	writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
	657	writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
	658	writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
663707c1	659	}
663707c1	660	}
	661	#else
	662	#define pxa_gpio_suspend NULL
	663	#define pxa_gpio_resume NULL
	664	#endif
	665
2eaa03b5	666	struct syscore_ops pxa_gpio_syscore_ops = {
663707c1	667	.suspend = pxa_gpio_suspend,
	668	.resume = pxa_gpio_resume,
	669	};
157d2644 HZ	670
	671	static int __init pxa_gpio_sysinit(void)
	672	{
	673	register_syscore_ops(&pxa_gpio_syscore_ops);
	674	return 0;
	675	}
	676	postcore_initcall(pxa_gpio_sysinit);