Commit | Line | Data |
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119f5e44 MD |
1 | /* |
2 | * Renesas R-Car GPIO Support | |
3 | * | |
1fd2b49d | 4 | * Copyright (C) 2014 Renesas Electronics Corporation |
119f5e44 MD |
5 | * Copyright (C) 2013 Magnus Damm |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
ab82fa7d | 17 | #include <linux/clk.h> |
119f5e44 MD |
18 | #include <linux/err.h> |
19 | #include <linux/gpio.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/irq.h> | |
119f5e44 | 25 | #include <linux/module.h> |
bd0bf468 | 26 | #include <linux/of.h> |
dc3465a9 | 27 | #include <linux/pinctrl/consumer.h> |
119f5e44 MD |
28 | #include <linux/platform_data/gpio-rcar.h> |
29 | #include <linux/platform_device.h> | |
df0c6c80 | 30 | #include <linux/pm_runtime.h> |
119f5e44 MD |
31 | #include <linux/spinlock.h> |
32 | #include <linux/slab.h> | |
33 | ||
34 | struct gpio_rcar_priv { | |
35 | void __iomem *base; | |
36 | spinlock_t lock; | |
37 | struct gpio_rcar_config config; | |
38 | struct platform_device *pdev; | |
39 | struct gpio_chip gpio_chip; | |
40 | struct irq_chip irq_chip; | |
ab82fa7d GU |
41 | unsigned int irq_parent; |
42 | struct clk *clk; | |
119f5e44 MD |
43 | }; |
44 | ||
3dc1e685 GU |
45 | #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ |
46 | #define INOUTSEL 0x04 /* General Input/Output Switching Register */ | |
47 | #define OUTDT 0x08 /* General Output Register */ | |
48 | #define INDT 0x0c /* General Input Register */ | |
49 | #define INTDT 0x10 /* Interrupt Display Register */ | |
50 | #define INTCLR 0x14 /* Interrupt Clear Register */ | |
51 | #define INTMSK 0x18 /* Interrupt Mask Register */ | |
52 | #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ | |
53 | #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ | |
54 | #define EDGLEVEL 0x24 /* Edge/level Select Register */ | |
55 | #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ | |
56 | #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ | |
119f5e44 | 57 | |
159f8a02 LP |
58 | #define RCAR_MAX_GPIO_PER_BANK 32 |
59 | ||
119f5e44 MD |
60 | static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) |
61 | { | |
62 | return ioread32(p->base + offs); | |
63 | } | |
64 | ||
65 | static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, | |
66 | u32 value) | |
67 | { | |
68 | iowrite32(value, p->base + offs); | |
69 | } | |
70 | ||
71 | static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, | |
72 | int bit, bool value) | |
73 | { | |
74 | u32 tmp = gpio_rcar_read(p, offs); | |
75 | ||
76 | if (value) | |
77 | tmp |= BIT(bit); | |
78 | else | |
79 | tmp &= ~BIT(bit); | |
80 | ||
81 | gpio_rcar_write(p, offs, tmp); | |
82 | } | |
83 | ||
84 | static void gpio_rcar_irq_disable(struct irq_data *d) | |
85 | { | |
c7f3c5d3 GU |
86 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
87 | struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, | |
88 | gpio_chip); | |
119f5e44 MD |
89 | |
90 | gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); | |
91 | } | |
92 | ||
93 | static void gpio_rcar_irq_enable(struct irq_data *d) | |
94 | { | |
c7f3c5d3 GU |
95 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
96 | struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, | |
97 | gpio_chip); | |
119f5e44 MD |
98 | |
99 | gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); | |
100 | } | |
101 | ||
102 | static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, | |
103 | unsigned int hwirq, | |
104 | bool active_high_rising_edge, | |
7e1092b5 SH |
105 | bool level_trigger, |
106 | bool both) | |
119f5e44 MD |
107 | { |
108 | unsigned long flags; | |
109 | ||
110 | /* follow steps in the GPIO documentation for | |
111 | * "Setting Edge-Sensitive Interrupt Input Mode" and | |
112 | * "Setting Level-Sensitive Interrupt Input Mode" | |
113 | */ | |
114 | ||
115 | spin_lock_irqsave(&p->lock, flags); | |
116 | ||
117 | /* Configure postive or negative logic in POSNEG */ | |
118 | gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); | |
119 | ||
120 | /* Configure edge or level trigger in EDGLEVEL */ | |
121 | gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); | |
122 | ||
7e1092b5 SH |
123 | /* Select one edge or both edges in BOTHEDGE */ |
124 | if (p->config.has_both_edge_trigger) | |
125 | gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); | |
126 | ||
119f5e44 MD |
127 | /* Select "Interrupt Input Mode" in IOINTSEL */ |
128 | gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); | |
129 | ||
130 | /* Write INTCLR in case of edge trigger */ | |
131 | if (!level_trigger) | |
132 | gpio_rcar_write(p, INTCLR, BIT(hwirq)); | |
133 | ||
134 | spin_unlock_irqrestore(&p->lock, flags); | |
135 | } | |
136 | ||
137 | static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) | |
138 | { | |
c7f3c5d3 GU |
139 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
140 | struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, | |
141 | gpio_chip); | |
119f5e44 MD |
142 | unsigned int hwirq = irqd_to_hwirq(d); |
143 | ||
144 | dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); | |
145 | ||
146 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
147 | case IRQ_TYPE_LEVEL_HIGH: | |
7e1092b5 SH |
148 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, |
149 | false); | |
119f5e44 MD |
150 | break; |
151 | case IRQ_TYPE_LEVEL_LOW: | |
7e1092b5 SH |
152 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, |
153 | false); | |
119f5e44 MD |
154 | break; |
155 | case IRQ_TYPE_EDGE_RISING: | |
7e1092b5 SH |
156 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, |
157 | false); | |
119f5e44 MD |
158 | break; |
159 | case IRQ_TYPE_EDGE_FALLING: | |
7e1092b5 SH |
160 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, |
161 | false); | |
162 | break; | |
163 | case IRQ_TYPE_EDGE_BOTH: | |
164 | if (!p->config.has_both_edge_trigger) | |
165 | return -EINVAL; | |
166 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, | |
167 | true); | |
119f5e44 MD |
168 | break; |
169 | default: | |
170 | return -EINVAL; | |
171 | } | |
172 | return 0; | |
173 | } | |
174 | ||
ab82fa7d GU |
175 | static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) |
176 | { | |
177 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
178 | struct gpio_rcar_priv *p = container_of(gc, struct gpio_rcar_priv, | |
179 | gpio_chip); | |
501ef0f9 GU |
180 | int error; |
181 | ||
182 | if (p->irq_parent) { | |
183 | error = irq_set_irq_wake(p->irq_parent, on); | |
184 | if (error) { | |
185 | dev_dbg(&p->pdev->dev, | |
186 | "irq %u doesn't support irq_set_wake\n", | |
187 | p->irq_parent); | |
188 | p->irq_parent = 0; | |
189 | } | |
190 | } | |
ab82fa7d GU |
191 | |
192 | if (!p->clk) | |
193 | return 0; | |
194 | ||
195 | if (on) | |
196 | clk_enable(p->clk); | |
197 | else | |
198 | clk_disable(p->clk); | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
119f5e44 MD |
203 | static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) |
204 | { | |
205 | struct gpio_rcar_priv *p = dev_id; | |
206 | u32 pending; | |
207 | unsigned int offset, irqs_handled = 0; | |
208 | ||
8808b64d VB |
209 | while ((pending = gpio_rcar_read(p, INTDT) & |
210 | gpio_rcar_read(p, INTMSK))) { | |
119f5e44 MD |
211 | offset = __ffs(pending); |
212 | gpio_rcar_write(p, INTCLR, BIT(offset)); | |
c7f3c5d3 GU |
213 | generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain, |
214 | offset)); | |
119f5e44 MD |
215 | irqs_handled++; |
216 | } | |
217 | ||
218 | return irqs_handled ? IRQ_HANDLED : IRQ_NONE; | |
219 | } | |
220 | ||
221 | static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) | |
222 | { | |
223 | return container_of(chip, struct gpio_rcar_priv, gpio_chip); | |
224 | } | |
225 | ||
226 | static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, | |
227 | unsigned int gpio, | |
228 | bool output) | |
229 | { | |
230 | struct gpio_rcar_priv *p = gpio_to_priv(chip); | |
231 | unsigned long flags; | |
232 | ||
233 | /* follow steps in the GPIO documentation for | |
234 | * "Setting General Output Mode" and | |
235 | * "Setting General Input Mode" | |
236 | */ | |
237 | ||
238 | spin_lock_irqsave(&p->lock, flags); | |
239 | ||
240 | /* Configure postive logic in POSNEG */ | |
241 | gpio_rcar_modify_bit(p, POSNEG, gpio, false); | |
242 | ||
243 | /* Select "General Input/Output Mode" in IOINTSEL */ | |
244 | gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); | |
245 | ||
246 | /* Select Input Mode or Output Mode in INOUTSEL */ | |
247 | gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); | |
248 | ||
249 | spin_unlock_irqrestore(&p->lock, flags); | |
250 | } | |
251 | ||
dc3465a9 LP |
252 | static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) |
253 | { | |
65194cb1 GU |
254 | struct gpio_rcar_priv *p = gpio_to_priv(chip); |
255 | int error; | |
256 | ||
257 | error = pm_runtime_get_sync(&p->pdev->dev); | |
258 | if (error < 0) | |
259 | return error; | |
260 | ||
261 | error = pinctrl_request_gpio(chip->base + offset); | |
262 | if (error) | |
263 | pm_runtime_put(&p->pdev->dev); | |
264 | ||
265 | return error; | |
dc3465a9 LP |
266 | } |
267 | ||
268 | static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) | |
269 | { | |
65194cb1 GU |
270 | struct gpio_rcar_priv *p = gpio_to_priv(chip); |
271 | ||
dc3465a9 LP |
272 | pinctrl_free_gpio(chip->base + offset); |
273 | ||
274 | /* Set the GPIO as an input to ensure that the next GPIO request won't | |
275 | * drive the GPIO pin as an output. | |
276 | */ | |
277 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
65194cb1 GU |
278 | |
279 | pm_runtime_put(&p->pdev->dev); | |
dc3465a9 LP |
280 | } |
281 | ||
119f5e44 MD |
282 | static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) |
283 | { | |
284 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) | |
289 | { | |
ae9550f6 MD |
290 | u32 bit = BIT(offset); |
291 | ||
292 | /* testing on r8a7790 shows that INDT does not show correct pin state | |
293 | * when configured as output, so use OUTDT in case of output pins */ | |
294 | if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit) | |
7cb5409b | 295 | return !!(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit); |
ae9550f6 | 296 | else |
7cb5409b | 297 | return !!(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit); |
119f5e44 MD |
298 | } |
299 | ||
300 | static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) | |
301 | { | |
302 | struct gpio_rcar_priv *p = gpio_to_priv(chip); | |
303 | unsigned long flags; | |
304 | ||
305 | spin_lock_irqsave(&p->lock, flags); | |
306 | gpio_rcar_modify_bit(p, OUTDT, offset, value); | |
307 | spin_unlock_irqrestore(&p->lock, flags); | |
308 | } | |
309 | ||
310 | static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, | |
311 | int value) | |
312 | { | |
313 | /* write GPIO value to output before selecting output mode of pin */ | |
314 | gpio_rcar_set(chip, offset, value); | |
315 | gpio_rcar_config_general_input_output_mode(chip, offset, true); | |
316 | return 0; | |
317 | } | |
318 | ||
850dfe17 LP |
319 | struct gpio_rcar_info { |
320 | bool has_both_edge_trigger; | |
321 | }; | |
322 | ||
1fd2b49d HN |
323 | static const struct gpio_rcar_info gpio_rcar_info_gen1 = { |
324 | .has_both_edge_trigger = false, | |
325 | }; | |
326 | ||
327 | static const struct gpio_rcar_info gpio_rcar_info_gen2 = { | |
328 | .has_both_edge_trigger = true, | |
329 | }; | |
330 | ||
850dfe17 LP |
331 | static const struct of_device_id gpio_rcar_of_table[] = { |
332 | { | |
333 | .compatible = "renesas,gpio-r8a7790", | |
1fd2b49d | 334 | .data = &gpio_rcar_info_gen2, |
850dfe17 LP |
335 | }, { |
336 | .compatible = "renesas,gpio-r8a7791", | |
1fd2b49d HN |
337 | .data = &gpio_rcar_info_gen2, |
338 | }, { | |
339 | .compatible = "renesas,gpio-r8a7793", | |
340 | .data = &gpio_rcar_info_gen2, | |
341 | }, { | |
342 | .compatible = "renesas,gpio-r8a7794", | |
343 | .data = &gpio_rcar_info_gen2, | |
8cd14702 UH |
344 | }, { |
345 | .compatible = "renesas,gpio-r8a7795", | |
346 | /* Gen3 GPIO is identical to Gen2. */ | |
347 | .data = &gpio_rcar_info_gen2, | |
850dfe17 LP |
348 | }, { |
349 | .compatible = "renesas,gpio-rcar", | |
1fd2b49d | 350 | .data = &gpio_rcar_info_gen1, |
850dfe17 LP |
351 | }, { |
352 | /* Terminator */ | |
353 | }, | |
354 | }; | |
355 | ||
356 | MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); | |
357 | ||
358 | static int gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) | |
159f8a02 | 359 | { |
e56aee18 | 360 | struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev); |
159f8a02 LP |
361 | struct device_node *np = p->pdev->dev.of_node; |
362 | struct of_phandle_args args; | |
363 | int ret; | |
159f8a02 | 364 | |
e305062e | 365 | if (pdata) { |
159f8a02 | 366 | p->config = *pdata; |
e305062e | 367 | } else if (IS_ENABLED(CONFIG_OF) && np) { |
850dfe17 LP |
368 | const struct of_device_id *match; |
369 | const struct gpio_rcar_info *info; | |
370 | ||
371 | match = of_match_node(gpio_rcar_of_table, np); | |
372 | if (!match) | |
373 | return -EINVAL; | |
374 | ||
375 | info = match->data; | |
376 | ||
01eb2d18 LP |
377 | ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, |
378 | &args); | |
379 | p->config.number_of_pins = ret == 0 ? args.args[2] | |
159f8a02 LP |
380 | : RCAR_MAX_GPIO_PER_BANK; |
381 | p->config.gpio_base = -1; | |
850dfe17 | 382 | p->config.has_both_edge_trigger = info->has_both_edge_trigger; |
159f8a02 | 383 | } |
159f8a02 LP |
384 | |
385 | if (p->config.number_of_pins == 0 || | |
386 | p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { | |
387 | dev_warn(&p->pdev->dev, | |
388 | "Invalid number of gpio lines %u, using %u\n", | |
389 | p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); | |
390 | p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; | |
391 | } | |
850dfe17 LP |
392 | |
393 | return 0; | |
159f8a02 LP |
394 | } |
395 | ||
119f5e44 MD |
396 | static int gpio_rcar_probe(struct platform_device *pdev) |
397 | { | |
119f5e44 MD |
398 | struct gpio_rcar_priv *p; |
399 | struct resource *io, *irq; | |
400 | struct gpio_chip *gpio_chip; | |
401 | struct irq_chip *irq_chip; | |
b22978fc GU |
402 | struct device *dev = &pdev->dev; |
403 | const char *name = dev_name(dev); | |
119f5e44 MD |
404 | int ret; |
405 | ||
b22978fc | 406 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
7d82bf34 GU |
407 | if (!p) |
408 | return -ENOMEM; | |
119f5e44 | 409 | |
119f5e44 | 410 | p->pdev = pdev; |
119f5e44 MD |
411 | spin_lock_init(&p->lock); |
412 | ||
159f8a02 | 413 | /* Get device configuration from DT node or platform data. */ |
850dfe17 LP |
414 | ret = gpio_rcar_parse_pdata(p); |
415 | if (ret < 0) | |
416 | return ret; | |
159f8a02 LP |
417 | |
418 | platform_set_drvdata(pdev, p); | |
419 | ||
ab82fa7d GU |
420 | p->clk = devm_clk_get(dev, NULL); |
421 | if (IS_ERR(p->clk)) { | |
422 | dev_warn(dev, "unable to get clock\n"); | |
423 | p->clk = NULL; | |
424 | } | |
425 | ||
df0c6c80 | 426 | pm_runtime_enable(dev); |
df0c6c80 | 427 | |
119f5e44 MD |
428 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
429 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
430 | ||
431 | if (!io || !irq) { | |
b22978fc | 432 | dev_err(dev, "missing IRQ or IOMEM\n"); |
119f5e44 MD |
433 | ret = -EINVAL; |
434 | goto err0; | |
435 | } | |
436 | ||
b22978fc | 437 | p->base = devm_ioremap_nocache(dev, io->start, resource_size(io)); |
119f5e44 | 438 | if (!p->base) { |
b22978fc | 439 | dev_err(dev, "failed to remap I/O memory\n"); |
119f5e44 MD |
440 | ret = -ENXIO; |
441 | goto err0; | |
442 | } | |
443 | ||
444 | gpio_chip = &p->gpio_chip; | |
dc3465a9 LP |
445 | gpio_chip->request = gpio_rcar_request; |
446 | gpio_chip->free = gpio_rcar_free; | |
119f5e44 MD |
447 | gpio_chip->direction_input = gpio_rcar_direction_input; |
448 | gpio_chip->get = gpio_rcar_get; | |
449 | gpio_chip->direction_output = gpio_rcar_direction_output; | |
450 | gpio_chip->set = gpio_rcar_set; | |
119f5e44 | 451 | gpio_chip->label = name; |
b22978fc | 452 | gpio_chip->dev = dev; |
119f5e44 MD |
453 | gpio_chip->owner = THIS_MODULE; |
454 | gpio_chip->base = p->config.gpio_base; | |
455 | gpio_chip->ngpio = p->config.number_of_pins; | |
456 | ||
457 | irq_chip = &p->irq_chip; | |
458 | irq_chip->name = name; | |
459 | irq_chip->irq_mask = gpio_rcar_irq_disable; | |
460 | irq_chip->irq_unmask = gpio_rcar_irq_enable; | |
119f5e44 | 461 | irq_chip->irq_set_type = gpio_rcar_irq_set_type; |
ab82fa7d GU |
462 | irq_chip->irq_set_wake = gpio_rcar_irq_set_wake; |
463 | irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; | |
119f5e44 | 464 | |
c7f3c5d3 GU |
465 | ret = gpiochip_add(gpio_chip); |
466 | if (ret) { | |
467 | dev_err(dev, "failed to add GPIO controller\n"); | |
0c8aab8e | 468 | goto err0; |
119f5e44 MD |
469 | } |
470 | ||
4d84b9e4 | 471 | ret = gpiochip_irqchip_add(gpio_chip, irq_chip, p->config.irq_base, |
c7f3c5d3 GU |
472 | handle_level_irq, IRQ_TYPE_NONE); |
473 | if (ret) { | |
474 | dev_err(dev, "cannot add irqchip\n"); | |
475 | goto err1; | |
476 | } | |
477 | ||
ab82fa7d | 478 | p->irq_parent = irq->start; |
b22978fc GU |
479 | if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, |
480 | IRQF_SHARED, name, p)) { | |
481 | dev_err(dev, "failed to request IRQ\n"); | |
119f5e44 MD |
482 | ret = -ENOENT; |
483 | goto err1; | |
484 | } | |
485 | ||
b22978fc | 486 | dev_info(dev, "driving %d GPIOs\n", p->config.number_of_pins); |
119f5e44 MD |
487 | |
488 | /* warn in case of mismatch if irq base is specified */ | |
489 | if (p->config.irq_base) { | |
4d84b9e4 | 490 | ret = irq_find_mapping(gpio_chip->irqdomain, 0); |
119f5e44 | 491 | if (p->config.irq_base != ret) |
b22978fc | 492 | dev_warn(dev, "irq base mismatch (%u/%u)\n", |
119f5e44 MD |
493 | p->config.irq_base, ret); |
494 | } | |
495 | ||
159f8a02 LP |
496 | if (p->config.pctl_name) { |
497 | ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, | |
498 | gpio_chip->base, gpio_chip->ngpio); | |
499 | if (ret < 0) | |
b22978fc | 500 | dev_warn(dev, "failed to add pin range\n"); |
159f8a02 | 501 | } |
dc3465a9 | 502 | |
119f5e44 MD |
503 | return 0; |
504 | ||
505 | err1: | |
4d84b9e4 | 506 | gpiochip_remove(gpio_chip); |
119f5e44 | 507 | err0: |
df0c6c80 | 508 | pm_runtime_disable(dev); |
119f5e44 MD |
509 | return ret; |
510 | } | |
511 | ||
512 | static int gpio_rcar_remove(struct platform_device *pdev) | |
513 | { | |
514 | struct gpio_rcar_priv *p = platform_get_drvdata(pdev); | |
119f5e44 | 515 | |
9f5132ae | 516 | gpiochip_remove(&p->gpio_chip); |
119f5e44 | 517 | |
df0c6c80 | 518 | pm_runtime_disable(&pdev->dev); |
119f5e44 MD |
519 | return 0; |
520 | } | |
521 | ||
522 | static struct platform_driver gpio_rcar_device_driver = { | |
523 | .probe = gpio_rcar_probe, | |
524 | .remove = gpio_rcar_remove, | |
525 | .driver = { | |
526 | .name = "gpio_rcar", | |
159f8a02 | 527 | .of_match_table = of_match_ptr(gpio_rcar_of_table), |
119f5e44 MD |
528 | } |
529 | }; | |
530 | ||
531 | module_platform_driver(gpio_rcar_device_driver); | |
532 | ||
533 | MODULE_AUTHOR("Magnus Damm"); | |
534 | MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); | |
535 | MODULE_LICENSE("GPL v2"); |