[deliverable/linux.git] / drivers / gpio / gpio-rcar.c

/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct gpio_rcar_config config;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
};

#define IOINTSEL 0x00
#define INOUTSEL 0x04
#define OUTDT 0x08
#define INDT 0x0c
#define INTDT 0x10
#define INTCLR 0x14
#define INTMSK 0x18
#define MSKCLR 0x1c
#define POSNEG 0x20
#define EDGLEVEL 0x24
#define FILONOFF 0x28
#define BOTHEDGE 0x4c

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->config.has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->config.has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
{
	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(chip->base + offset);
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(chip->base + offset);

	/* Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
		return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
	else
		return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
}

static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
				 irq_hw_number_t hw)
{
	struct gpio_rcar_priv *p = h->host_data;

	dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);

	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
	.map	= gpio_rcar_irq_domain_map,
};

static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
{
	struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
	struct device_node *np = p->pdev->dev.of_node;
	struct of_phandle_args args;
	int ret;

	if (pdata) {
		p->config = *pdata;
	} else if (IS_ENABLED(CONFIG_OF) && np) {
		ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
						       &args);
		p->config.number_of_pins = ret == 0 ? args.args[2]
					 : RCAR_MAX_GPIO_PER_BANK;
		p->config.gpio_base = -1;
	}

	if (p->config.number_of_pins == 0 ||
	    p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(&p->pdev->dev,
			 "Invalid number of gpio lines %u, using %u\n",
			 p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
		p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
	}
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	const char *name = dev_name(&pdev->dev);
	int ret;

	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		ret = -ENOMEM;
		goto err0;
	}

	p->pdev = pdev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node or platform data. */
	gpio_rcar_parse_pdata(p);

	platform_set_drvdata(pdev, p);

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);

	if (!io || !irq) {
		dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base = devm_ioremap_nocache(&pdev->dev, io->start,
				       resource_size(io));
	if (!p->base) {
		dev_err(&pdev->dev, "failed to remap I/O memory\n");
		ret = -ENXIO;
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->to_irq = gpio_rcar_to_irq;
	gpio_chip->label = name;
	gpio_chip->dev = &pdev->dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = p->config.gpio_base;
	gpio_chip->ngpio = p->config.number_of_pins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_enable = gpio_rcar_irq_enable;
	irq_chip->irq_disable = gpio_rcar_irq_disable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;

	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
					      p->config.number_of_pins,
					      p->config.irq_base,
					      &gpio_rcar_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(&pdev->dev, "cannot initialize irq domain\n");
		goto err1;
	}

	if (devm_request_irq(&pdev->dev, irq->start,
			     gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
		dev_err(&pdev->dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	ret = gpiochip_add(gpio_chip);
	if (ret) {
		dev_err(&pdev->dev, "failed to add GPIO controller\n");
		goto err1;
	}

	dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);

	/* warn in case of mismatch if irq base is specified */
	if (p->config.irq_base) {
		ret = irq_find_mapping(p->irq_domain, 0);
		if (p->config.irq_base != ret)
			dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
				 p->config.irq_base, ret);
	}

	if (p->config.pctl_name) {
		ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
					     gpio_chip->base, gpio_chip->ngpio);
		if (ret < 0)
			dev_warn(&pdev->dev, "failed to add pin range\n");
	}

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
	int ret;

	ret = gpiochip_remove(&p->gpio_chip);
	if (ret)
		return ret;

	irq_domain_remove(p->irq_domain);
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-rcar",
	},
	{ },
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
#endif

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
119f5e44 MD	1	/*
	2	* Renesas R-Car GPIO Support
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/err.h>
	17	#include <linux/gpio.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/io.h>
	21	#include <linux/ioport.h>
	22	#include <linux/irq.h>
	23	#include <linux/irqdomain.h>
	24	#include <linux/module.h>
dc3465a9	25	#include <linux/pinctrl/consumer.h>
119f5e44 MD	26	#include <linux/platform_data/gpio-rcar.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/spinlock.h>
	29	#include <linux/slab.h>
	30
	31	struct gpio_rcar_priv {
	32	void __iomem *base;
	33	spinlock_t lock;
	34	struct gpio_rcar_config config;
	35	struct platform_device *pdev;
	36	struct gpio_chip gpio_chip;
	37	struct irq_chip irq_chip;
	38	struct irq_domain *irq_domain;
	39	};
	40
	41	#define IOINTSEL 0x00
	42	#define INOUTSEL 0x04
	43	#define OUTDT 0x08
	44	#define INDT 0x0c
	45	#define INTDT 0x10
	46	#define INTCLR 0x14
	47	#define INTMSK 0x18
	48	#define MSKCLR 0x1c
	49	#define POSNEG 0x20
	50	#define EDGLEVEL 0x24
	51	#define FILONOFF 0x28
7e1092b5	52	#define BOTHEDGE 0x4c
119f5e44	53
159f8a02 LP	54	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	55
119f5e44 MD	56	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	57	{
	58	return ioread32(p->base + offs);
	59	}
	60
	61	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	62	u32 value)
	63	{
	64	iowrite32(value, p->base + offs);
	65	}
	66
	67	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	68	int bit, bool value)
	69	{
	70	u32 tmp = gpio_rcar_read(p, offs);
	71
	72	if (value)
	73	tmp \|= BIT(bit);
	74	else
	75	tmp &= ~BIT(bit);
	76
	77	gpio_rcar_write(p, offs, tmp);
	78	}
	79
	80	static void gpio_rcar_irq_disable(struct irq_data *d)
	81	{
	82	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	83
	84	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	85	}
	86
	87	static void gpio_rcar_irq_enable(struct irq_data *d)
	88	{
	89	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	90
	91	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	92	}
	93
	94	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	95	unsigned int hwirq,
	96	bool active_high_rising_edge,
7e1092b5 SH	97	bool level_trigger,
7e1092b5 SH	98	bool both)
119f5e44 MD	99	{
	100	unsigned long flags;
	101
	102	/* follow steps in the GPIO documentation for
	103	* "Setting Edge-Sensitive Interrupt Input Mode" and
	104	* "Setting Level-Sensitive Interrupt Input Mode"
	105	*/
	106
	107	spin_lock_irqsave(&p->lock, flags);
	108
	109	/* Configure postive or negative logic in POSNEG */
	110	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	111
	112	/* Configure edge or level trigger in EDGLEVEL */
	113	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	114
7e1092b5 SH	115	/* Select one edge or both edges in BOTHEDGE */
	116	if (p->config.has_both_edge_trigger)
	117	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
	118
119f5e44 MD	119	/* Select "Interrupt Input Mode" in IOINTSEL */
	120	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	121
	122	/* Write INTCLR in case of edge trigger */
	123	if (!level_trigger)
	124	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	125
	126	spin_unlock_irqrestore(&p->lock, flags);
	127	}
	128
	129	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	130	{
	131	struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
	132	unsigned int hwirq = irqd_to_hwirq(d);
	133
	134	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
	135
	136	switch (type & IRQ_TYPE_SENSE_MASK) {
	137	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	138	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	139	false);
119f5e44 MD	140	break;
119f5e44 MD	141	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	142	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	143	false);
119f5e44 MD	144	break;
119f5e44 MD	145	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	146	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	147	false);
119f5e44 MD	148	break;
119f5e44 MD	149	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	150	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	151	false);
	152	break;
	153	case IRQ_TYPE_EDGE_BOTH:
	154	if (!p->config.has_both_edge_trigger)
	155	return -EINVAL;
	156	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	157	true);
119f5e44 MD	158	break;
	159	default:
	160	return -EINVAL;
	161	}
	162	return 0;
	163	}
	164
	165	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	166	{
	167	struct gpio_rcar_priv *p = dev_id;
	168	u32 pending;
	169	unsigned int offset, irqs_handled = 0;
	170
	171	while ((pending = gpio_rcar_read(p, INTDT))) {
	172	offset = __ffs(pending);
	173	gpio_rcar_write(p, INTCLR, BIT(offset));
	174	generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
	175	irqs_handled++;
	176	}
	177
	178	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	179	}
	180
	181	static inline struct gpio_rcar_priv gpio_to_priv(struct gpio_chip chip)
	182	{
	183	return container_of(chip, struct gpio_rcar_priv, gpio_chip);
	184	}
	185
	186	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	187	unsigned int gpio,
	188	bool output)
	189	{
	190	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	191	unsigned long flags;
	192
	193	/* follow steps in the GPIO documentation for
	194	* "Setting General Output Mode" and
	195	* "Setting General Input Mode"
	196	*/
	197
	198	spin_lock_irqsave(&p->lock, flags);
	199
	200	/* Configure postive logic in POSNEG */
	201	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	202
	203	/* Select "General Input/Output Mode" in IOINTSEL */
	204	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	205
	206	/* Select Input Mode or Output Mode in INOUTSEL */
	207	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	208
	209	spin_unlock_irqrestore(&p->lock, flags);
	210	}
	211
dc3465a9 LP	212	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
	213	{
	214	return pinctrl_request_gpio(chip->base + offset);
	215	}
	216
	217	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	218	{
	219	pinctrl_free_gpio(chip->base + offset);
	220
	221	/* Set the GPIO as an input to ensure that the next GPIO request won't
	222	* drive the GPIO pin as an output.
	223	*/
	224	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	225	}
	226
119f5e44 MD	227	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	228	{
	229	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	230	return 0;
	231	}
	232
	233	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	234	{
ae9550f6 MD	235	u32 bit = BIT(offset);
	236
	237	/* testing on r8a7790 shows that INDT does not show correct pin state
	238	* when configured as output, so use OUTDT in case of output pins */
	239	if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit)
	240	return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit);
	241	else
	242	return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit);
119f5e44 MD	243	}
	244
	245	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	246	{
	247	struct gpio_rcar_priv *p = gpio_to_priv(chip);
	248	unsigned long flags;
	249
	250	spin_lock_irqsave(&p->lock, flags);
	251	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	252	spin_unlock_irqrestore(&p->lock, flags);
	253	}
	254
	255	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	256	int value)
	257	{
	258	/* write GPIO value to output before selecting output mode of pin */
	259	gpio_rcar_set(chip, offset, value);
	260	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	261	return 0;
	262	}
	263
	264	static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
	265	{
	266	return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
	267	}
	268
	269	static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
	270	irq_hw_number_t hw)
	271	{
	272	struct gpio_rcar_priv *p = h->host_data;
	273
	274	dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
	275
	276	irq_set_chip_data(virq, h->host_data);
	277	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	278	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	279	return 0;
	280	}
	281
	282	static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
	283	.map = gpio_rcar_irq_domain_map,
	284	};
	285
159f8a02 LP	286	static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
159f8a02 LP	287	{
e56aee18	288	struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev);
159f8a02 LP	289	struct device_node *np = p->pdev->dev.of_node;
	290	struct of_phandle_args args;
	291	int ret;
159f8a02	292
e305062e	293	if (pdata) {
159f8a02	294	p->config = *pdata;
e305062e	295	} else if (IS_ENABLED(CONFIG_OF) && np) {
01eb2d18 LP	296	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
	297	&args);
	298	p->config.number_of_pins = ret == 0 ? args.args[2]
159f8a02 LP	299	: RCAR_MAX_GPIO_PER_BANK;
	300	p->config.gpio_base = -1;
	301	}
159f8a02 LP	302
	303	if (p->config.number_of_pins == 0 \|\|
	304	p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) {
	305	dev_warn(&p->pdev->dev,
	306	"Invalid number of gpio lines %u, using %u\n",
	307	p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK);
	308	p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK;
	309	}
	310	}
	311
119f5e44 MD	312	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	313	{
119f5e44 MD	314	struct gpio_rcar_priv *p;
	315	struct resource io, irq;
	316	struct gpio_chip *gpio_chip;
	317	struct irq_chip *irq_chip;
	318	const char *name = dev_name(&pdev->dev);
	319	int ret;
	320
	321	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
	322	if (!p) {
	323	dev_err(&pdev->dev, "failed to allocate driver data\n");
	324	ret = -ENOMEM;
	325	goto err0;
	326	}
	327
119f5e44	328	p->pdev = pdev;
119f5e44 MD	329	spin_lock_init(&p->lock);
119f5e44 MD	330
159f8a02 LP	331	/* Get device configuration from DT node or platform data. */
	332	gpio_rcar_parse_pdata(p);
	333
	334	platform_set_drvdata(pdev, p);
	335
119f5e44 MD	336	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	337	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	338
	339	if (!io \|\| !irq) {
	340	dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
	341	ret = -EINVAL;
	342	goto err0;
	343	}
	344
	345	p->base = devm_ioremap_nocache(&pdev->dev, io->start,
	346	resource_size(io));
	347	if (!p->base) {
	348	dev_err(&pdev->dev, "failed to remap I/O memory\n");
	349	ret = -ENXIO;
	350	goto err0;
	351	}
	352
	353	gpio_chip = &p->gpio_chip;
dc3465a9 LP	354	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	355	gpio_chip->free = gpio_rcar_free;
119f5e44 MD	356	gpio_chip->direction_input = gpio_rcar_direction_input;
	357	gpio_chip->get = gpio_rcar_get;
	358	gpio_chip->direction_output = gpio_rcar_direction_output;
	359	gpio_chip->set = gpio_rcar_set;
	360	gpio_chip->to_irq = gpio_rcar_to_irq;
	361	gpio_chip->label = name;
159f8a02	362	gpio_chip->dev = &pdev->dev;
119f5e44 MD	363	gpio_chip->owner = THIS_MODULE;
	364	gpio_chip->base = p->config.gpio_base;
	365	gpio_chip->ngpio = p->config.number_of_pins;
	366
	367	irq_chip = &p->irq_chip;
	368	irq_chip->name = name;
	369	irq_chip->irq_mask = gpio_rcar_irq_disable;
	370	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	371	irq_chip->irq_enable = gpio_rcar_irq_enable;
	372	irq_chip->irq_disable = gpio_rcar_irq_disable;
	373	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	374	irq_chip->flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_SET_TYPE_MASKED;
	375
	376	p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
	377	p->config.number_of_pins,
	378	p->config.irq_base,
	379	&gpio_rcar_irq_domain_ops, p);
	380	if (!p->irq_domain) {
	381	ret = -ENXIO;
	382	dev_err(&pdev->dev, "cannot initialize irq domain\n");
	383	goto err1;
	384	}
	385
	386	if (devm_request_irq(&pdev->dev, irq->start,
c234962b	387	gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
119f5e44 MD	388	dev_err(&pdev->dev, "failed to request IRQ\n");
	389	ret = -ENOENT;
	390	goto err1;
	391	}
	392
	393	ret = gpiochip_add(gpio_chip);
	394	if (ret) {
	395	dev_err(&pdev->dev, "failed to add GPIO controller\n");
	396	goto err1;
	397	}
	398
	399	dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
	400
	401	/* warn in case of mismatch if irq base is specified */
	402	if (p->config.irq_base) {
	403	ret = irq_find_mapping(p->irq_domain, 0);
	404	if (p->config.irq_base != ret)
	405	dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
	406	p->config.irq_base, ret);
	407	}
	408
159f8a02 LP	409	if (p->config.pctl_name) {
	410	ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
	411	gpio_chip->base, gpio_chip->ngpio);
	412	if (ret < 0)
	413	dev_warn(&pdev->dev, "failed to add pin range\n");
	414	}
dc3465a9	415
119f5e44 MD	416	return 0;
	417
	418	err1:
	419	irq_domain_remove(p->irq_domain);
	420	err0:
	421	return ret;
	422	}
	423
	424	static int gpio_rcar_remove(struct platform_device *pdev)
	425	{
	426	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
	427	int ret;
	428
	429	ret = gpiochip_remove(&p->gpio_chip);
	430	if (ret)
	431	return ret;
	432
	433	irq_domain_remove(p->irq_domain);
	434	return 0;
	435	}
	436
159f8a02 LP	437	#ifdef CONFIG_OF
	438	static const struct of_device_id gpio_rcar_of_table[] = {
	439	{
	440	.compatible = "renesas,gpio-rcar",
	441	},
30d2266c	442	{ },
159f8a02 LP	443	};
	444
	445	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	446	#endif
	447
119f5e44 MD	448	static struct platform_driver gpio_rcar_device_driver = {
	449	.probe = gpio_rcar_probe,
	450	.remove = gpio_rcar_remove,
	451	.driver = {
	452	.name = "gpio_rcar",
159f8a02	453	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	454	}
	455	};
	456
	457	module_platform_driver(gpio_rcar_device_driver);
	458
	459	MODULE_AUTHOR("Magnus Damm");
	460	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	461	MODULE_LICENSE("GPL v2");