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1b39d5f2 KK |
1 | /* |
2 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com/ | |
4 | * | |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * SAMSUNG - GPIOlib support | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
edbaa603 | 25 | #include <linux/device.h> |
1b39d5f2 | 26 | #include <linux/ioport.h> |
659d73ad TA |
27 | #include <linux/of.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/of_address.h> | |
1b39d5f2 KK |
30 | |
31 | #include <asm/irq.h> | |
32 | ||
1b39d5f2 | 33 | #include <mach/map.h> |
1b39d5f2 | 34 | #include <mach/regs-gpio.h> |
785acec3 SK |
35 | |
36 | #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX) | |
b0161caa | 37 | #include <mach/gpio-samsung.h> |
785acec3 | 38 | #endif |
1b39d5f2 KK |
39 | |
40 | #include <plat/cpu.h> | |
41 | #include <plat/gpio-core.h> | |
42 | #include <plat/gpio-cfg.h> | |
43 | #include <plat/gpio-cfg-helpers.h> | |
1b39d5f2 KK |
44 | #include <plat/pm.h> |
45 | ||
1b39d5f2 KK |
46 | int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, |
47 | unsigned int off, samsung_gpio_pull_t pull) | |
48 | { | |
49 | void __iomem *reg = chip->base + 0x08; | |
50 | int shift = off * 2; | |
51 | u32 pup; | |
52 | ||
53 | pup = __raw_readl(reg); | |
54 | pup &= ~(3 << shift); | |
55 | pup |= pull << shift; | |
56 | __raw_writel(pup, reg); | |
57 | ||
58 | return 0; | |
59 | } | |
60 | ||
61 | samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, | |
62 | unsigned int off) | |
63 | { | |
64 | void __iomem *reg = chip->base + 0x08; | |
65 | int shift = off * 2; | |
66 | u32 pup = __raw_readl(reg); | |
67 | ||
68 | pup >>= shift; | |
69 | pup &= 0x3; | |
70 | ||
71 | return (__force samsung_gpio_pull_t)pup; | |
72 | } | |
73 | ||
74 | int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, | |
75 | unsigned int off, samsung_gpio_pull_t pull) | |
76 | { | |
77 | switch (pull) { | |
78 | case S3C_GPIO_PULL_NONE: | |
79 | pull = 0x01; | |
80 | break; | |
81 | case S3C_GPIO_PULL_UP: | |
82 | pull = 0x00; | |
83 | break; | |
84 | case S3C_GPIO_PULL_DOWN: | |
85 | pull = 0x02; | |
86 | break; | |
87 | } | |
88 | return samsung_gpio_setpull_updown(chip, off, pull); | |
89 | } | |
90 | ||
91 | samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, | |
92 | unsigned int off) | |
93 | { | |
94 | samsung_gpio_pull_t pull; | |
95 | ||
96 | pull = samsung_gpio_getpull_updown(chip, off); | |
97 | ||
98 | switch (pull) { | |
99 | case 0x00: | |
100 | pull = S3C_GPIO_PULL_UP; | |
101 | break; | |
102 | case 0x01: | |
103 | case 0x03: | |
104 | pull = S3C_GPIO_PULL_NONE; | |
105 | break; | |
106 | case 0x02: | |
107 | pull = S3C_GPIO_PULL_DOWN; | |
108 | break; | |
109 | } | |
110 | ||
111 | return pull; | |
112 | } | |
113 | ||
114 | static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip, | |
115 | unsigned int off, samsung_gpio_pull_t pull, | |
116 | samsung_gpio_pull_t updown) | |
117 | { | |
118 | void __iomem *reg = chip->base + 0x08; | |
119 | u32 pup = __raw_readl(reg); | |
120 | ||
121 | if (pull == updown) | |
122 | pup &= ~(1 << off); | |
123 | else if (pull == S3C_GPIO_PULL_NONE) | |
124 | pup |= (1 << off); | |
125 | else | |
126 | return -EINVAL; | |
127 | ||
128 | __raw_writel(pup, reg); | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip, | |
133 | unsigned int off, | |
134 | samsung_gpio_pull_t updown) | |
135 | { | |
136 | void __iomem *reg = chip->base + 0x08; | |
137 | u32 pup = __raw_readl(reg); | |
138 | ||
139 | pup &= (1 << off); | |
140 | return pup ? S3C_GPIO_PULL_NONE : updown; | |
141 | } | |
142 | ||
143 | samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, | |
144 | unsigned int off) | |
145 | { | |
146 | return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP); | |
147 | } | |
148 | ||
149 | int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, | |
150 | unsigned int off, samsung_gpio_pull_t pull) | |
151 | { | |
152 | return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP); | |
153 | } | |
154 | ||
155 | samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, | |
156 | unsigned int off) | |
157 | { | |
158 | return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN); | |
159 | } | |
160 | ||
161 | int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, | |
162 | unsigned int off, samsung_gpio_pull_t pull) | |
163 | { | |
164 | return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); | |
165 | } | |
166 | ||
1b39d5f2 KK |
167 | /* |
168 | * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration. | |
169 | * @chip: The gpio chip that is being configured. | |
170 | * @off: The offset for the GPIO being configured. | |
171 | * @cfg: The configuration value to set. | |
172 | * | |
173 | * This helper deal with the GPIO cases where the control register | |
174 | * has two bits of configuration per gpio, which have the following | |
175 | * functions: | |
176 | * 00 = input | |
177 | * 01 = output | |
178 | * 1x = special function | |
179 | */ | |
180 | ||
181 | static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip, | |
182 | unsigned int off, unsigned int cfg) | |
183 | { | |
184 | void __iomem *reg = chip->base; | |
185 | unsigned int shift = off * 2; | |
186 | u32 con; | |
187 | ||
188 | if (samsung_gpio_is_cfg_special(cfg)) { | |
189 | cfg &= 0xf; | |
190 | if (cfg > 3) | |
191 | return -EINVAL; | |
192 | ||
193 | cfg <<= shift; | |
194 | } | |
195 | ||
196 | con = __raw_readl(reg); | |
197 | con &= ~(0x3 << shift); | |
198 | con |= cfg; | |
199 | __raw_writel(con, reg); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | /* | |
205 | * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read. | |
206 | * @chip: The gpio chip that is being configured. | |
207 | * @off: The offset for the GPIO being configured. | |
208 | * | |
f1347599 | 209 | * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which |
1b39d5f2 KK |
210 | * could be directly passed back to samsung_gpio_setcfg_2bit(), from the |
211 | * S3C_GPIO_SPECIAL() macro. | |
212 | */ | |
213 | ||
214 | static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip, | |
215 | unsigned int off) | |
216 | { | |
217 | u32 con; | |
218 | ||
219 | con = __raw_readl(chip->base); | |
220 | con >>= off * 2; | |
221 | con &= 3; | |
222 | ||
223 | /* this conversion works for IN and OUT as well as special mode */ | |
224 | return S3C_GPIO_SPECIAL(con); | |
225 | } | |
226 | ||
227 | /* | |
228 | * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config. | |
229 | * @chip: The gpio chip that is being configured. | |
230 | * @off: The offset for the GPIO being configured. | |
231 | * @cfg: The configuration value to set. | |
232 | * | |
233 | * This helper deal with the GPIO cases where the control register has 4 bits | |
234 | * of control per GPIO, generally in the form of: | |
235 | * 0000 = Input | |
236 | * 0001 = Output | |
237 | * others = Special functions (dependent on bank) | |
238 | * | |
239 | * Note, since the code to deal with the case where there are two control | |
240 | * registers instead of one, we do not have a separate set of functions for | |
241 | * each case. | |
242 | */ | |
243 | ||
244 | static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip, | |
245 | unsigned int off, unsigned int cfg) | |
246 | { | |
247 | void __iomem *reg = chip->base; | |
248 | unsigned int shift = (off & 7) * 4; | |
249 | u32 con; | |
250 | ||
251 | if (off < 8 && chip->chip.ngpio > 8) | |
252 | reg -= 4; | |
253 | ||
254 | if (samsung_gpio_is_cfg_special(cfg)) { | |
255 | cfg &= 0xf; | |
256 | cfg <<= shift; | |
257 | } | |
258 | ||
259 | con = __raw_readl(reg); | |
260 | con &= ~(0xf << shift); | |
261 | con |= cfg; | |
262 | __raw_writel(con, reg); | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | /* | |
268 | * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read. | |
269 | * @chip: The gpio chip that is being configured. | |
270 | * @off: The offset for the GPIO being configured. | |
271 | * | |
272 | * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration | |
273 | * register setting into a value the software can use, such as could be passed | |
274 | * to samsung_gpio_setcfg_4bit(). | |
275 | * | |
276 | * @sa samsung_gpio_getcfg_2bit | |
277 | */ | |
278 | ||
279 | static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip, | |
280 | unsigned int off) | |
281 | { | |
282 | void __iomem *reg = chip->base; | |
283 | unsigned int shift = (off & 7) * 4; | |
284 | u32 con; | |
285 | ||
286 | if (off < 8 && chip->chip.ngpio > 8) | |
287 | reg -= 4; | |
288 | ||
289 | con = __raw_readl(reg); | |
290 | con >>= shift; | |
291 | con &= 0xf; | |
292 | ||
293 | /* this conversion works for IN and OUT as well as special mode */ | |
294 | return S3C_GPIO_SPECIAL(con); | |
295 | } | |
296 | ||
c034b184 | 297 | #ifdef CONFIG_PLAT_S3C24XX |
1b39d5f2 KK |
298 | /* |
299 | * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A) | |
300 | * @chip: The gpio chip that is being configured. | |
301 | * @off: The offset for the GPIO being configured. | |
302 | * @cfg: The configuration value to set. | |
303 | * | |
304 | * This helper deal with the GPIO cases where the control register | |
305 | * has one bit of configuration for the gpio, where setting the bit | |
306 | * means the pin is in special function mode and unset means output. | |
307 | */ | |
308 | ||
309 | static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip, | |
310 | unsigned int off, unsigned int cfg) | |
311 | { | |
312 | void __iomem *reg = chip->base; | |
313 | unsigned int shift = off; | |
314 | u32 con; | |
315 | ||
316 | if (samsung_gpio_is_cfg_special(cfg)) { | |
317 | cfg &= 0xf; | |
318 | ||
319 | /* Map output to 0, and SFN2 to 1 */ | |
320 | cfg -= 1; | |
321 | if (cfg > 1) | |
322 | return -EINVAL; | |
323 | ||
324 | cfg <<= shift; | |
325 | } | |
326 | ||
327 | con = __raw_readl(reg); | |
328 | con &= ~(0x1 << shift); | |
329 | con |= cfg; | |
330 | __raw_writel(con, reg); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
335 | /* | |
336 | * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A) | |
337 | * @chip: The gpio chip that is being configured. | |
338 | * @off: The offset for the GPIO being configured. | |
339 | * | |
340 | * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable | |
341 | * GPIO configuration value. | |
342 | * | |
343 | * @sa samsung_gpio_getcfg_2bit | |
344 | * @sa samsung_gpio_getcfg_4bit | |
345 | */ | |
346 | ||
347 | static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip, | |
348 | unsigned int off) | |
349 | { | |
350 | u32 con; | |
351 | ||
352 | con = __raw_readl(chip->base); | |
353 | con >>= off; | |
354 | con &= 1; | |
355 | con++; | |
356 | ||
357 | return S3C_GPIO_SFN(con); | |
358 | } | |
c034b184 | 359 | #endif |
1b39d5f2 | 360 | |
1b39d5f2 KK |
361 | static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg, |
362 | int nr_chips) | |
363 | { | |
364 | for (; nr_chips > 0; nr_chips--, chipcfg++) { | |
365 | if (!chipcfg->set_config) | |
366 | chipcfg->set_config = samsung_gpio_setcfg_4bit; | |
367 | if (!chipcfg->get_config) | |
368 | chipcfg->get_config = samsung_gpio_getcfg_4bit; | |
369 | if (!chipcfg->set_pull) | |
370 | chipcfg->set_pull = samsung_gpio_setpull_updown; | |
371 | if (!chipcfg->get_pull) | |
372 | chipcfg->get_pull = samsung_gpio_getpull_updown; | |
373 | } | |
374 | } | |
375 | ||
376 | struct samsung_gpio_cfg s3c24xx_gpiocfg_default = { | |
377 | .set_config = samsung_gpio_setcfg_2bit, | |
378 | .get_config = samsung_gpio_getcfg_2bit, | |
379 | }; | |
380 | ||
c034b184 | 381 | #ifdef CONFIG_PLAT_S3C24XX |
1b39d5f2 KK |
382 | static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = { |
383 | .set_config = s3c24xx_gpio_setcfg_abank, | |
384 | .get_config = s3c24xx_gpio_getcfg_abank, | |
385 | }; | |
c034b184 | 386 | #endif |
1b39d5f2 | 387 | |
1b39d5f2 | 388 | static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { |
2985479f | 389 | [0] = { |
1b39d5f2 | 390 | .cfg_eint = 0x0, |
2985479f MB |
391 | }, |
392 | [1] = { | |
1b39d5f2 | 393 | .cfg_eint = 0x3, |
2985479f MB |
394 | }, |
395 | [2] = { | |
1b39d5f2 | 396 | .cfg_eint = 0x7, |
2985479f MB |
397 | }, |
398 | [3] = { | |
1b39d5f2 | 399 | .cfg_eint = 0xF, |
2985479f MB |
400 | }, |
401 | [4] = { | |
1b39d5f2 KK |
402 | .cfg_eint = 0x0, |
403 | .set_config = samsung_gpio_setcfg_2bit, | |
404 | .get_config = samsung_gpio_getcfg_2bit, | |
2985479f MB |
405 | }, |
406 | [5] = { | |
1b39d5f2 KK |
407 | .cfg_eint = 0x2, |
408 | .set_config = samsung_gpio_setcfg_2bit, | |
409 | .get_config = samsung_gpio_getcfg_2bit, | |
2985479f MB |
410 | }, |
411 | [6] = { | |
1b39d5f2 KK |
412 | .cfg_eint = 0x3, |
413 | .set_config = samsung_gpio_setcfg_2bit, | |
414 | .get_config = samsung_gpio_getcfg_2bit, | |
2985479f MB |
415 | }, |
416 | [7] = { | |
1b39d5f2 KK |
417 | .set_config = samsung_gpio_setcfg_2bit, |
418 | .get_config = samsung_gpio_getcfg_2bit, | |
2985479f | 419 | }, |
1b39d5f2 KK |
420 | }; |
421 | ||
422 | /* | |
423 | * Default routines for controlling GPIO, based on the original S3C24XX | |
424 | * GPIO functions which deal with the case where each gpio bank of the | |
425 | * chip is as following: | |
426 | * | |
427 | * base + 0x00: Control register, 2 bits per gpio | |
428 | * gpio n: 2 bits starting at (2*n) | |
429 | * 00 = input, 01 = output, others mean special-function | |
430 | * base + 0x04: Data register, 1 bit per gpio | |
431 | * bit n: data bit n | |
432 | */ | |
433 | ||
434 | static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset) | |
435 | { | |
436 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
437 | void __iomem *base = ourchip->base; | |
438 | unsigned long flags; | |
439 | unsigned long con; | |
440 | ||
441 | samsung_gpio_lock(ourchip, flags); | |
442 | ||
443 | con = __raw_readl(base + 0x00); | |
444 | con &= ~(3 << (offset * 2)); | |
445 | ||
446 | __raw_writel(con, base + 0x00); | |
447 | ||
448 | samsung_gpio_unlock(ourchip, flags); | |
449 | return 0; | |
450 | } | |
451 | ||
452 | static int samsung_gpiolib_2bit_output(struct gpio_chip *chip, | |
453 | unsigned offset, int value) | |
454 | { | |
455 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
456 | void __iomem *base = ourchip->base; | |
457 | unsigned long flags; | |
458 | unsigned long dat; | |
459 | unsigned long con; | |
460 | ||
461 | samsung_gpio_lock(ourchip, flags); | |
462 | ||
463 | dat = __raw_readl(base + 0x04); | |
464 | dat &= ~(1 << offset); | |
465 | if (value) | |
466 | dat |= 1 << offset; | |
467 | __raw_writel(dat, base + 0x04); | |
468 | ||
469 | con = __raw_readl(base + 0x00); | |
470 | con &= ~(3 << (offset * 2)); | |
471 | con |= 1 << (offset * 2); | |
472 | ||
473 | __raw_writel(con, base + 0x00); | |
474 | __raw_writel(dat, base + 0x04); | |
475 | ||
476 | samsung_gpio_unlock(ourchip, flags); | |
477 | return 0; | |
478 | } | |
479 | ||
480 | /* | |
481 | * The samsung_gpiolib_4bit routines are to control the gpio banks where | |
482 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | |
483 | * following example: | |
484 | * | |
485 | * base + 0x00: Control register, 4 bits per gpio | |
486 | * gpio n: 4 bits starting at (4*n) | |
487 | * 0000 = input, 0001 = output, others mean special-function | |
488 | * base + 0x04: Data register, 1 bit per gpio | |
489 | * bit n: data bit n | |
490 | * | |
491 | * Note, since the data register is one bit per gpio and is at base + 0x4 | |
492 | * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the | |
493 | * state of the output. | |
494 | */ | |
495 | ||
496 | static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, | |
497 | unsigned int offset) | |
498 | { | |
499 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
500 | void __iomem *base = ourchip->base; | |
501 | unsigned long con; | |
502 | ||
503 | con = __raw_readl(base + GPIOCON_OFF); | |
2b88ff4a EK |
504 | if (ourchip->bitmap_gpio_int & BIT(offset)) |
505 | con |= 0xf << con_4bit_shift(offset); | |
506 | else | |
507 | con &= ~(0xf << con_4bit_shift(offset)); | |
1b39d5f2 KK |
508 | __raw_writel(con, base + GPIOCON_OFF); |
509 | ||
343db4bd | 510 | pr_debug("%s: %p: CON now %08lx\n", __func__, base, con); |
1b39d5f2 KK |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, | |
516 | unsigned int offset, int value) | |
517 | { | |
518 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
519 | void __iomem *base = ourchip->base; | |
520 | unsigned long con; | |
521 | unsigned long dat; | |
522 | ||
523 | con = __raw_readl(base + GPIOCON_OFF); | |
524 | con &= ~(0xf << con_4bit_shift(offset)); | |
525 | con |= 0x1 << con_4bit_shift(offset); | |
526 | ||
527 | dat = __raw_readl(base + GPIODAT_OFF); | |
528 | ||
529 | if (value) | |
530 | dat |= 1 << offset; | |
531 | else | |
532 | dat &= ~(1 << offset); | |
533 | ||
534 | __raw_writel(dat, base + GPIODAT_OFF); | |
535 | __raw_writel(con, base + GPIOCON_OFF); | |
536 | __raw_writel(dat, base + GPIODAT_OFF); | |
537 | ||
343db4bd | 538 | pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); |
1b39d5f2 KK |
539 | |
540 | return 0; | |
541 | } | |
542 | ||
543 | /* | |
544 | * The next set of routines are for the case where the GPIO configuration | |
545 | * registers are 4 bits per GPIO but there is more than one register (the | |
546 | * bank has more than 8 GPIOs. | |
547 | * | |
548 | * This case is the similar to the 4 bit case, but the registers are as | |
549 | * follows: | |
550 | * | |
551 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | |
552 | * gpio n: 4 bits starting at (4*n) | |
553 | * 0000 = input, 0001 = output, others mean special-function | |
554 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | |
555 | * gpio n: 4 bits starting at (4*n) | |
556 | * 0000 = input, 0001 = output, others mean special-function | |
557 | * base + 0x08: Data register, 1 bit per gpio | |
558 | * bit n: data bit n | |
559 | * | |
560 | * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set | |
561 | * routines we store the 'base + 0x4' address so that these routines see | |
562 | * the data register at ourchip->base + 0x04. | |
563 | */ | |
564 | ||
565 | static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, | |
566 | unsigned int offset) | |
567 | { | |
568 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
569 | void __iomem *base = ourchip->base; | |
570 | void __iomem *regcon = base; | |
571 | unsigned long con; | |
572 | ||
573 | if (offset > 7) | |
574 | offset -= 8; | |
575 | else | |
576 | regcon -= 4; | |
577 | ||
578 | con = __raw_readl(regcon); | |
579 | con &= ~(0xf << con_4bit_shift(offset)); | |
580 | __raw_writel(con, regcon); | |
581 | ||
343db4bd | 582 | pr_debug("%s: %p: CON %08lx\n", __func__, base, con); |
1b39d5f2 KK |
583 | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, | |
588 | unsigned int offset, int value) | |
589 | { | |
590 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
591 | void __iomem *base = ourchip->base; | |
592 | void __iomem *regcon = base; | |
593 | unsigned long con; | |
594 | unsigned long dat; | |
595 | unsigned con_offset = offset; | |
596 | ||
597 | if (con_offset > 7) | |
598 | con_offset -= 8; | |
599 | else | |
600 | regcon -= 4; | |
601 | ||
602 | con = __raw_readl(regcon); | |
603 | con &= ~(0xf << con_4bit_shift(con_offset)); | |
604 | con |= 0x1 << con_4bit_shift(con_offset); | |
605 | ||
606 | dat = __raw_readl(base + GPIODAT_OFF); | |
607 | ||
608 | if (value) | |
609 | dat |= 1 << offset; | |
610 | else | |
611 | dat &= ~(1 << offset); | |
612 | ||
613 | __raw_writel(dat, base + GPIODAT_OFF); | |
614 | __raw_writel(con, regcon); | |
615 | __raw_writel(dat, base + GPIODAT_OFF); | |
616 | ||
343db4bd | 617 | pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); |
1b39d5f2 KK |
618 | |
619 | return 0; | |
620 | } | |
621 | ||
c034b184 | 622 | #ifdef CONFIG_PLAT_S3C24XX |
1b39d5f2 KK |
623 | /* The next set of routines are for the case of s3c24xx bank a */ |
624 | ||
625 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | |
626 | { | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | |
631 | unsigned offset, int value) | |
632 | { | |
633 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
634 | void __iomem *base = ourchip->base; | |
635 | unsigned long flags; | |
636 | unsigned long dat; | |
637 | unsigned long con; | |
638 | ||
639 | local_irq_save(flags); | |
640 | ||
641 | con = __raw_readl(base + 0x00); | |
642 | dat = __raw_readl(base + 0x04); | |
643 | ||
644 | dat &= ~(1 << offset); | |
645 | if (value) | |
646 | dat |= 1 << offset; | |
647 | ||
648 | __raw_writel(dat, base + 0x04); | |
649 | ||
650 | con &= ~(1 << offset); | |
651 | ||
652 | __raw_writel(con, base + 0x00); | |
653 | __raw_writel(dat, base + 0x04); | |
654 | ||
655 | local_irq_restore(flags); | |
656 | return 0; | |
657 | } | |
c034b184 | 658 | #endif |
1b39d5f2 | 659 | |
1b39d5f2 KK |
660 | static void samsung_gpiolib_set(struct gpio_chip *chip, |
661 | unsigned offset, int value) | |
662 | { | |
663 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
664 | void __iomem *base = ourchip->base; | |
665 | unsigned long flags; | |
666 | unsigned long dat; | |
667 | ||
668 | samsung_gpio_lock(ourchip, flags); | |
669 | ||
670 | dat = __raw_readl(base + 0x04); | |
671 | dat &= ~(1 << offset); | |
672 | if (value) | |
673 | dat |= 1 << offset; | |
674 | __raw_writel(dat, base + 0x04); | |
675 | ||
676 | samsung_gpio_unlock(ourchip, flags); | |
677 | } | |
678 | ||
679 | static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset) | |
680 | { | |
681 | struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); | |
682 | unsigned long val; | |
683 | ||
684 | val = __raw_readl(ourchip->base + 0x04); | |
685 | val >>= offset; | |
686 | val &= 1; | |
687 | ||
688 | return val; | |
689 | } | |
690 | ||
691 | /* | |
692 | * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios | |
693 | * for use with the configuration calls, and other parts of the s3c gpiolib | |
694 | * support code. | |
695 | * | |
696 | * Not all s3c support code will need this, as some configurations of cpu | |
697 | * may only support one or two different configuration options and have an | |
698 | * easy gpio to samsung_gpio_chip mapping function. If this is the case, then | |
699 | * the machine support file should provide its own samsung_gpiolib_getchip() | |
700 | * and any other necessary functions. | |
701 | */ | |
702 | ||
703 | #ifdef CONFIG_S3C_GPIO_TRACK | |
704 | struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; | |
705 | ||
706 | static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip) | |
707 | { | |
708 | unsigned int gpn; | |
709 | int i; | |
710 | ||
711 | gpn = chip->chip.base; | |
712 | for (i = 0; i < chip->chip.ngpio; i++, gpn++) { | |
713 | BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); | |
714 | s3c_gpios[gpn] = chip; | |
715 | } | |
716 | } | |
717 | #endif /* CONFIG_S3C_GPIO_TRACK */ | |
718 | ||
719 | /* | |
720 | * samsung_gpiolib_add() - add the Samsung gpio_chip. | |
721 | * @chip: The chip to register | |
722 | * | |
723 | * This is a wrapper to gpiochip_add() that takes our specific gpio chip | |
724 | * information and makes the necessary alterations for the platform and | |
725 | * notes the information for use with the configuration systems and any | |
726 | * other parts of the system. | |
727 | */ | |
728 | ||
729 | static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip) | |
730 | { | |
731 | struct gpio_chip *gc = &chip->chip; | |
732 | int ret; | |
733 | ||
734 | BUG_ON(!chip->base); | |
735 | BUG_ON(!gc->label); | |
736 | BUG_ON(!gc->ngpio); | |
737 | ||
738 | spin_lock_init(&chip->lock); | |
739 | ||
740 | if (!gc->direction_input) | |
741 | gc->direction_input = samsung_gpiolib_2bit_input; | |
742 | if (!gc->direction_output) | |
743 | gc->direction_output = samsung_gpiolib_2bit_output; | |
744 | if (!gc->set) | |
745 | gc->set = samsung_gpiolib_set; | |
746 | if (!gc->get) | |
747 | gc->get = samsung_gpiolib_get; | |
748 | ||
749 | #ifdef CONFIG_PM | |
750 | if (chip->pm != NULL) { | |
751 | if (!chip->pm->save || !chip->pm->resume) | |
343db4bd | 752 | pr_err("gpio: %s has missing PM functions\n", |
1b39d5f2 KK |
753 | gc->label); |
754 | } else | |
343db4bd | 755 | pr_err("gpio: %s has no PM function\n", gc->label); |
1b39d5f2 KK |
756 | #endif |
757 | ||
758 | /* gpiochip_add() prints own failure message on error. */ | |
759 | ret = gpiochip_add(gc); | |
760 | if (ret >= 0) | |
761 | s3c_gpiolib_track(chip); | |
762 | } | |
763 | ||
764 | static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, | |
765 | int nr_chips, void __iomem *base) | |
766 | { | |
767 | int i; | |
768 | struct gpio_chip *gc = &chip->chip; | |
769 | ||
770 | for (i = 0 ; i < nr_chips; i++, chip++) { | |
8a8ab2e6 PK |
771 | /* skip banks not present on SoC */ |
772 | if (chip->chip.base >= S3C_GPIO_END) | |
773 | continue; | |
774 | ||
1b39d5f2 KK |
775 | if (!chip->config) |
776 | chip->config = &s3c24xx_gpiocfg_default; | |
777 | if (!chip->pm) | |
778 | chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); | |
779 | if ((base != NULL) && (chip->base == NULL)) | |
780 | chip->base = base + ((i) * 0x10); | |
781 | ||
782 | if (!gc->direction_input) | |
783 | gc->direction_input = samsung_gpiolib_2bit_input; | |
784 | if (!gc->direction_output) | |
785 | gc->direction_output = samsung_gpiolib_2bit_output; | |
786 | ||
787 | samsung_gpiolib_add(chip); | |
788 | } | |
789 | } | |
790 | ||
791 | static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, | |
792 | int nr_chips, void __iomem *base, | |
793 | unsigned int offset) | |
794 | { | |
795 | int i; | |
796 | ||
797 | for (i = 0 ; i < nr_chips; i++, chip++) { | |
798 | chip->chip.direction_input = samsung_gpiolib_2bit_input; | |
799 | chip->chip.direction_output = samsung_gpiolib_2bit_output; | |
800 | ||
801 | if (!chip->config) | |
802 | chip->config = &samsung_gpio_cfgs[7]; | |
803 | if (!chip->pm) | |
804 | chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); | |
805 | if ((base != NULL) && (chip->base == NULL)) | |
806 | chip->base = base + ((i) * offset); | |
807 | ||
808 | samsung_gpiolib_add(chip); | |
809 | } | |
810 | } | |
811 | ||
812 | /* | |
813 | * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. | |
814 | * @chip: The gpio chip that is being configured. | |
815 | * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. | |
816 | * | |
817 | * This helper deal with the GPIO cases where the control register has 4 bits | |
818 | * of control per GPIO, generally in the form of: | |
819 | * 0000 = Input | |
820 | * 0001 = Output | |
821 | * others = Special functions (dependent on bank) | |
822 | * | |
823 | * Note, since the code to deal with the case where there are two control | |
824 | * registers instead of one, we do not have a separate set of function | |
825 | * (samsung_gpiolib_add_4bit2_chips)for each case. | |
826 | */ | |
827 | ||
828 | static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, | |
829 | int nr_chips, void __iomem *base) | |
830 | { | |
831 | int i; | |
832 | ||
833 | for (i = 0 ; i < nr_chips; i++, chip++) { | |
834 | chip->chip.direction_input = samsung_gpiolib_4bit_input; | |
835 | chip->chip.direction_output = samsung_gpiolib_4bit_output; | |
836 | ||
837 | if (!chip->config) | |
838 | chip->config = &samsung_gpio_cfgs[2]; | |
839 | if (!chip->pm) | |
840 | chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); | |
841 | if ((base != NULL) && (chip->base == NULL)) | |
842 | chip->base = base + ((i) * 0x20); | |
843 | ||
2b88ff4a EK |
844 | chip->bitmap_gpio_int = 0; |
845 | ||
1b39d5f2 KK |
846 | samsung_gpiolib_add(chip); |
847 | } | |
848 | } | |
849 | ||
850 | static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip, | |
851 | int nr_chips) | |
852 | { | |
853 | for (; nr_chips > 0; nr_chips--, chip++) { | |
854 | chip->chip.direction_input = samsung_gpiolib_4bit2_input; | |
855 | chip->chip.direction_output = samsung_gpiolib_4bit2_output; | |
856 | ||
857 | if (!chip->config) | |
858 | chip->config = &samsung_gpio_cfgs[2]; | |
859 | if (!chip->pm) | |
860 | chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); | |
861 | ||
862 | samsung_gpiolib_add(chip); | |
863 | } | |
864 | } | |
865 | ||
1b39d5f2 KK |
866 | int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) |
867 | { | |
868 | struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip); | |
869 | ||
870 | return samsung_chip->irq_base + offset; | |
871 | } | |
872 | ||
873 | #ifdef CONFIG_PLAT_S3C24XX | |
874 | static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset) | |
875 | { | |
d97fedef | 876 | if (offset < 4) { |
1c8408e3 HS |
877 | if (soc_is_s3c2412()) |
878 | return IRQ_EINT0_2412 + offset; | |
879 | else | |
880 | return IRQ_EINT0 + offset; | |
d97fedef | 881 | } |
1b39d5f2 KK |
882 | |
883 | if (offset < 8) | |
884 | return IRQ_EINT4 + offset - 4; | |
885 | ||
886 | return -EINVAL; | |
887 | } | |
888 | #endif | |
889 | ||
54362e11 | 890 | #ifdef CONFIG_ARCH_S3C64XX |
1b39d5f2 KK |
891 | static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin) |
892 | { | |
893 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; | |
894 | } | |
895 | ||
896 | static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin) | |
897 | { | |
898 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; | |
899 | } | |
900 | #endif | |
901 | ||
902 | struct samsung_gpio_chip s3c24xx_gpios[] = { | |
903 | #ifdef CONFIG_PLAT_S3C24XX | |
904 | { | |
905 | .config = &s3c24xx_gpiocfg_banka, | |
906 | .chip = { | |
907 | .base = S3C2410_GPA(0), | |
908 | .owner = THIS_MODULE, | |
909 | .label = "GPIOA", | |
035b2f7c | 910 | .ngpio = 27, |
1b39d5f2 KK |
911 | .direction_input = s3c24xx_gpiolib_banka_input, |
912 | .direction_output = s3c24xx_gpiolib_banka_output, | |
913 | }, | |
914 | }, { | |
915 | .chip = { | |
916 | .base = S3C2410_GPB(0), | |
917 | .owner = THIS_MODULE, | |
918 | .label = "GPIOB", | |
035b2f7c | 919 | .ngpio = 11, |
1b39d5f2 KK |
920 | }, |
921 | }, { | |
922 | .chip = { | |
923 | .base = S3C2410_GPC(0), | |
924 | .owner = THIS_MODULE, | |
925 | .label = "GPIOC", | |
926 | .ngpio = 16, | |
927 | }, | |
928 | }, { | |
929 | .chip = { | |
930 | .base = S3C2410_GPD(0), | |
931 | .owner = THIS_MODULE, | |
932 | .label = "GPIOD", | |
933 | .ngpio = 16, | |
934 | }, | |
935 | }, { | |
936 | .chip = { | |
937 | .base = S3C2410_GPE(0), | |
938 | .label = "GPIOE", | |
939 | .owner = THIS_MODULE, | |
940 | .ngpio = 16, | |
941 | }, | |
942 | }, { | |
943 | .chip = { | |
944 | .base = S3C2410_GPF(0), | |
945 | .owner = THIS_MODULE, | |
946 | .label = "GPIOF", | |
947 | .ngpio = 8, | |
948 | .to_irq = s3c24xx_gpiolib_fbank_to_irq, | |
949 | }, | |
950 | }, { | |
951 | .irq_base = IRQ_EINT8, | |
952 | .chip = { | |
953 | .base = S3C2410_GPG(0), | |
954 | .owner = THIS_MODULE, | |
955 | .label = "GPIOG", | |
956 | .ngpio = 16, | |
957 | .to_irq = samsung_gpiolib_to_irq, | |
958 | }, | |
959 | }, { | |
960 | .chip = { | |
961 | .base = S3C2410_GPH(0), | |
962 | .owner = THIS_MODULE, | |
963 | .label = "GPIOH", | |
035b2f7c | 964 | .ngpio = 15, |
1b39d5f2 KK |
965 | }, |
966 | }, | |
967 | /* GPIOS for the S3C2443 and later devices. */ | |
968 | { | |
969 | .base = S3C2440_GPJCON, | |
970 | .chip = { | |
971 | .base = S3C2410_GPJ(0), | |
972 | .owner = THIS_MODULE, | |
973 | .label = "GPIOJ", | |
974 | .ngpio = 16, | |
975 | }, | |
976 | }, { | |
977 | .base = S3C2443_GPKCON, | |
978 | .chip = { | |
979 | .base = S3C2410_GPK(0), | |
980 | .owner = THIS_MODULE, | |
981 | .label = "GPIOK", | |
982 | .ngpio = 16, | |
983 | }, | |
984 | }, { | |
985 | .base = S3C2443_GPLCON, | |
986 | .chip = { | |
987 | .base = S3C2410_GPL(0), | |
988 | .owner = THIS_MODULE, | |
989 | .label = "GPIOL", | |
990 | .ngpio = 15, | |
991 | }, | |
992 | }, { | |
993 | .base = S3C2443_GPMCON, | |
994 | .chip = { | |
995 | .base = S3C2410_GPM(0), | |
996 | .owner = THIS_MODULE, | |
997 | .label = "GPIOM", | |
998 | .ngpio = 2, | |
999 | }, | |
1000 | }, | |
1001 | #endif | |
1002 | }; | |
1003 | ||
1004 | /* | |
1005 | * GPIO bank summary: | |
1006 | * | |
1007 | * Bank GPIOs Style SlpCon ExtInt Group | |
1008 | * A 8 4Bit Yes 1 | |
1009 | * B 7 4Bit Yes 1 | |
1010 | * C 8 4Bit Yes 2 | |
1011 | * D 5 4Bit Yes 3 | |
1012 | * E 5 4Bit Yes None | |
1013 | * F 16 2Bit Yes 4 [1] | |
1014 | * G 7 4Bit Yes 5 | |
1015 | * H 10 4Bit[2] Yes 6 | |
1016 | * I 16 2Bit Yes None | |
1017 | * J 12 2Bit Yes None | |
1018 | * K 16 4Bit[2] No None | |
1019 | * L 15 4Bit[2] No None | |
1020 | * M 6 4Bit No IRQ_EINT | |
1021 | * N 16 2Bit No IRQ_EINT | |
1022 | * O 16 2Bit Yes 7 | |
1023 | * P 15 2Bit Yes 8 | |
1024 | * Q 9 2Bit Yes 9 | |
1025 | * | |
1026 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | |
1027 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | |
1028 | */ | |
1029 | ||
1030 | static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = { | |
54362e11 | 1031 | #ifdef CONFIG_ARCH_S3C64XX |
1b39d5f2 KK |
1032 | { |
1033 | .chip = { | |
1034 | .base = S3C64XX_GPA(0), | |
1035 | .ngpio = S3C64XX_GPIO_A_NR, | |
1036 | .label = "GPA", | |
1037 | }, | |
1038 | }, { | |
1039 | .chip = { | |
1040 | .base = S3C64XX_GPB(0), | |
1041 | .ngpio = S3C64XX_GPIO_B_NR, | |
1042 | .label = "GPB", | |
1043 | }, | |
1044 | }, { | |
1045 | .chip = { | |
1046 | .base = S3C64XX_GPC(0), | |
1047 | .ngpio = S3C64XX_GPIO_C_NR, | |
1048 | .label = "GPC", | |
1049 | }, | |
1050 | }, { | |
1051 | .chip = { | |
1052 | .base = S3C64XX_GPD(0), | |
1053 | .ngpio = S3C64XX_GPIO_D_NR, | |
1054 | .label = "GPD", | |
1055 | }, | |
1056 | }, { | |
1057 | .config = &samsung_gpio_cfgs[0], | |
1058 | .chip = { | |
1059 | .base = S3C64XX_GPE(0), | |
1060 | .ngpio = S3C64XX_GPIO_E_NR, | |
1061 | .label = "GPE", | |
1062 | }, | |
1063 | }, { | |
1064 | .base = S3C64XX_GPG_BASE, | |
1065 | .chip = { | |
1066 | .base = S3C64XX_GPG(0), | |
1067 | .ngpio = S3C64XX_GPIO_G_NR, | |
1068 | .label = "GPG", | |
1069 | }, | |
1070 | }, { | |
1071 | .base = S3C64XX_GPM_BASE, | |
1072 | .config = &samsung_gpio_cfgs[1], | |
1073 | .chip = { | |
1074 | .base = S3C64XX_GPM(0), | |
1075 | .ngpio = S3C64XX_GPIO_M_NR, | |
1076 | .label = "GPM", | |
1077 | .to_irq = s3c64xx_gpiolib_mbank_to_irq, | |
1078 | }, | |
1079 | }, | |
1080 | #endif | |
1081 | }; | |
1082 | ||
1083 | static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = { | |
54362e11 | 1084 | #ifdef CONFIG_ARCH_S3C64XX |
1b39d5f2 KK |
1085 | { |
1086 | .base = S3C64XX_GPH_BASE + 0x4, | |
1087 | .chip = { | |
1088 | .base = S3C64XX_GPH(0), | |
1089 | .ngpio = S3C64XX_GPIO_H_NR, | |
1090 | .label = "GPH", | |
1091 | }, | |
1092 | }, { | |
1093 | .base = S3C64XX_GPK_BASE + 0x4, | |
1094 | .config = &samsung_gpio_cfgs[0], | |
1095 | .chip = { | |
1096 | .base = S3C64XX_GPK(0), | |
1097 | .ngpio = S3C64XX_GPIO_K_NR, | |
1098 | .label = "GPK", | |
1099 | }, | |
1100 | }, { | |
1101 | .base = S3C64XX_GPL_BASE + 0x4, | |
1102 | .config = &samsung_gpio_cfgs[1], | |
1103 | .chip = { | |
1104 | .base = S3C64XX_GPL(0), | |
1105 | .ngpio = S3C64XX_GPIO_L_NR, | |
1106 | .label = "GPL", | |
1107 | .to_irq = s3c64xx_gpiolib_lbank_to_irq, | |
1108 | }, | |
1109 | }, | |
1110 | #endif | |
1111 | }; | |
1112 | ||
1113 | static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = { | |
54362e11 | 1114 | #ifdef CONFIG_ARCH_S3C64XX |
1b39d5f2 KK |
1115 | { |
1116 | .base = S3C64XX_GPF_BASE, | |
1117 | .config = &samsung_gpio_cfgs[6], | |
1118 | .chip = { | |
1119 | .base = S3C64XX_GPF(0), | |
1120 | .ngpio = S3C64XX_GPIO_F_NR, | |
1121 | .label = "GPF", | |
1122 | }, | |
1123 | }, { | |
1124 | .config = &samsung_gpio_cfgs[7], | |
1125 | .chip = { | |
1126 | .base = S3C64XX_GPI(0), | |
1127 | .ngpio = S3C64XX_GPIO_I_NR, | |
1128 | .label = "GPI", | |
1129 | }, | |
1130 | }, { | |
1131 | .config = &samsung_gpio_cfgs[7], | |
1132 | .chip = { | |
1133 | .base = S3C64XX_GPJ(0), | |
1134 | .ngpio = S3C64XX_GPIO_J_NR, | |
1135 | .label = "GPJ", | |
1136 | }, | |
1137 | }, { | |
1138 | .config = &samsung_gpio_cfgs[6], | |
1139 | .chip = { | |
1140 | .base = S3C64XX_GPO(0), | |
1141 | .ngpio = S3C64XX_GPIO_O_NR, | |
1142 | .label = "GPO", | |
1143 | }, | |
1144 | }, { | |
1145 | .config = &samsung_gpio_cfgs[6], | |
1146 | .chip = { | |
1147 | .base = S3C64XX_GPP(0), | |
1148 | .ngpio = S3C64XX_GPIO_P_NR, | |
1149 | .label = "GPP", | |
1150 | }, | |
1151 | }, { | |
1152 | .config = &samsung_gpio_cfgs[6], | |
1153 | .chip = { | |
1154 | .base = S3C64XX_GPQ(0), | |
1155 | .ngpio = S3C64XX_GPIO_Q_NR, | |
1156 | .label = "GPQ", | |
1157 | }, | |
1158 | }, { | |
1159 | .base = S3C64XX_GPN_BASE, | |
1160 | .irq_base = IRQ_EINT(0), | |
1161 | .config = &samsung_gpio_cfgs[5], | |
1162 | .chip = { | |
1163 | .base = S3C64XX_GPN(0), | |
1164 | .ngpio = S3C64XX_GPIO_N_NR, | |
1165 | .label = "GPN", | |
1166 | .to_irq = samsung_gpiolib_to_irq, | |
1167 | }, | |
1168 | }, | |
1169 | #endif | |
1170 | }; | |
1171 | ||
1b39d5f2 KK |
1172 | /* TODO: cleanup soc_is_* */ |
1173 | static __init int samsung_gpiolib_init(void) | |
1174 | { | |
ba51bdd3 | 1175 | /* |
608f9737 TF |
1176 | * Currently there are two drivers that can provide GPIO support for |
1177 | * Samsung SoCs. For device tree enabled platforms, the new | |
1178 | * pinctrl-samsung driver is used, providing both GPIO and pin control | |
1179 | * interfaces. For legacy (non-DT) platforms this driver is used. | |
1180 | */ | |
1181 | if (of_have_populated_dt()) | |
1182 | return -ENODEV; | |
ba51bdd3 | 1183 | |
1b39d5f2 KK |
1184 | samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); |
1185 | ||
1186 | if (soc_is_s3c24xx()) { | |
1187 | s3c24xx_gpiolib_add_chips(s3c24xx_gpios, | |
1188 | ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO); | |
1189 | } else if (soc_is_s3c64xx()) { | |
1190 | samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit, | |
1191 | ARRAY_SIZE(s3c64xx_gpios_2bit), | |
1192 | S3C64XX_VA_GPIO + 0xE0, 0x20); | |
1193 | samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit, | |
1194 | ARRAY_SIZE(s3c64xx_gpios_4bit), | |
1195 | S3C64XX_VA_GPIO); | |
1196 | samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, | |
1197 | ARRAY_SIZE(s3c64xx_gpios_4bit2)); | |
fbe92fcc MB |
1198 | } else { |
1199 | WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); | |
1200 | return -ENODEV; | |
1b39d5f2 KK |
1201 | } |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | core_initcall(samsung_gpiolib_init); | |
1206 | ||
1207 | int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) | |
1208 | { | |
1209 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1210 | unsigned long flags; | |
1211 | int offset; | |
1212 | int ret; | |
1213 | ||
1214 | if (!chip) | |
1215 | return -EINVAL; | |
1216 | ||
1217 | offset = pin - chip->chip.base; | |
1218 | ||
1219 | samsung_gpio_lock(chip, flags); | |
1220 | ret = samsung_gpio_do_setcfg(chip, offset, config); | |
1221 | samsung_gpio_unlock(chip, flags); | |
1222 | ||
1223 | return ret; | |
1224 | } | |
1225 | EXPORT_SYMBOL(s3c_gpio_cfgpin); | |
1226 | ||
1227 | int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, | |
1228 | unsigned int cfg) | |
1229 | { | |
1230 | int ret; | |
1231 | ||
1232 | for (; nr > 0; nr--, start++) { | |
1233 | ret = s3c_gpio_cfgpin(start, cfg); | |
1234 | if (ret != 0) | |
1235 | return ret; | |
1236 | } | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range); | |
1241 | ||
1242 | int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, | |
1243 | unsigned int cfg, samsung_gpio_pull_t pull) | |
1244 | { | |
1245 | int ret; | |
1246 | ||
1247 | for (; nr > 0; nr--, start++) { | |
1248 | s3c_gpio_setpull(start, pull); | |
1249 | ret = s3c_gpio_cfgpin(start, cfg); | |
1250 | if (ret != 0) | |
1251 | return ret; | |
1252 | } | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range); | |
1257 | ||
1258 | unsigned s3c_gpio_getcfg(unsigned int pin) | |
1259 | { | |
1260 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1261 | unsigned long flags; | |
1262 | unsigned ret = 0; | |
1263 | int offset; | |
1264 | ||
1265 | if (chip) { | |
1266 | offset = pin - chip->chip.base; | |
1267 | ||
1268 | samsung_gpio_lock(chip, flags); | |
1269 | ret = samsung_gpio_do_getcfg(chip, offset); | |
1270 | samsung_gpio_unlock(chip, flags); | |
1271 | } | |
1272 | ||
1273 | return ret; | |
1274 | } | |
1275 | EXPORT_SYMBOL(s3c_gpio_getcfg); | |
1276 | ||
1277 | int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull) | |
1278 | { | |
1279 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1280 | unsigned long flags; | |
1281 | int offset, ret; | |
1282 | ||
1283 | if (!chip) | |
1284 | return -EINVAL; | |
1285 | ||
1286 | offset = pin - chip->chip.base; | |
1287 | ||
1288 | samsung_gpio_lock(chip, flags); | |
1289 | ret = samsung_gpio_do_setpull(chip, offset, pull); | |
1290 | samsung_gpio_unlock(chip, flags); | |
1291 | ||
1292 | return ret; | |
1293 | } | |
1294 | EXPORT_SYMBOL(s3c_gpio_setpull); | |
1295 | ||
1296 | samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin) | |
1297 | { | |
1298 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1299 | unsigned long flags; | |
1300 | int offset; | |
1301 | u32 pup = 0; | |
1302 | ||
1303 | if (chip) { | |
1304 | offset = pin - chip->chip.base; | |
1305 | ||
1306 | samsung_gpio_lock(chip, flags); | |
1307 | pup = samsung_gpio_do_getpull(chip, offset); | |
1308 | samsung_gpio_unlock(chip, flags); | |
1309 | } | |
1310 | ||
1311 | return (__force samsung_gpio_pull_t)pup; | |
1312 | } | |
1313 | EXPORT_SYMBOL(s3c_gpio_getpull); | |
1314 | ||
1b39d5f2 KK |
1315 | #ifdef CONFIG_S5P_GPIO_DRVSTR |
1316 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) | |
1317 | { | |
1318 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1319 | unsigned int off; | |
1320 | void __iomem *reg; | |
1321 | int shift; | |
1322 | u32 drvstr; | |
1323 | ||
1324 | if (!chip) | |
1325 | return -EINVAL; | |
1326 | ||
1327 | off = pin - chip->chip.base; | |
1328 | shift = off * 2; | |
1329 | reg = chip->base + 0x0C; | |
1330 | ||
1331 | drvstr = __raw_readl(reg); | |
1332 | drvstr = drvstr >> shift; | |
1333 | drvstr &= 0x3; | |
1334 | ||
1335 | return (__force s5p_gpio_drvstr_t)drvstr; | |
1336 | } | |
1337 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | |
1338 | ||
1339 | int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) | |
1340 | { | |
1341 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); | |
1342 | unsigned int off; | |
1343 | void __iomem *reg; | |
1344 | int shift; | |
1345 | u32 tmp; | |
1346 | ||
1347 | if (!chip) | |
1348 | return -EINVAL; | |
1349 | ||
1350 | off = pin - chip->chip.base; | |
1351 | shift = off * 2; | |
1352 | reg = chip->base + 0x0C; | |
1353 | ||
1354 | tmp = __raw_readl(reg); | |
1355 | tmp &= ~(0x3 << shift); | |
1356 | tmp |= drvstr << shift; | |
1357 | ||
1358 | __raw_writel(tmp, reg); | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | |
1363 | #endif /* CONFIG_S5P_GPIO_DRVSTR */ | |
1364 | ||
1365 | #ifdef CONFIG_PLAT_S3C24XX | |
1366 | unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) | |
1367 | { | |
1368 | unsigned long flags; | |
1369 | unsigned long misccr; | |
1370 | ||
1371 | local_irq_save(flags); | |
1372 | misccr = __raw_readl(S3C24XX_MISCCR); | |
1373 | misccr &= ~clear; | |
1374 | misccr ^= change; | |
1375 | __raw_writel(misccr, S3C24XX_MISCCR); | |
1376 | local_irq_restore(flags); | |
1377 | ||
1378 | return misccr; | |
1379 | } | |
1380 | EXPORT_SYMBOL(s3c2410_modify_misccr); | |
1381 | #endif |