projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'kirkwood/cleanup' of git://git.infradead.org/users/jcooper/linux into...
[deliverable/linux.git] / drivers / gpio / gpio-samsung.c
CommitLineData
1b39d5f2
KK		 1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * SAMSUNG - GPIOlib support
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
edbaa603 25#include <linux/device.h>
1b39d5f2 26#include <linux/ioport.h>
659d73ad
TA		 27#include <linux/of.h>
28#include <linux/slab.h>
29#include <linux/of_address.h>
1b39d5f2
KK		 30
31#include <asm/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/map.h>
35#include <mach/regs-clock.h>
36#include <mach/regs-gpio.h>
37
38#include <plat/cpu.h>
39#include <plat/gpio-core.h>
40#include <plat/gpio-cfg.h>
41#include <plat/gpio-cfg-helpers.h>
42#include <plat/gpio-fns.h>
43#include <plat/pm.h>
44
45#ifndef DEBUG_GPIO
46#define gpio_dbg(x...) do { } while (0)
47#else
48#define gpio_dbg(x...) printk(KERN_DEBUG x)
49#endif
50
51int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
52 unsigned int off, samsung_gpio_pull_t pull)
53{
54 void __iomem *reg = chip->base + 0x08;
55 int shift = off * 2;
56 u32 pup;
57
58 pup = __raw_readl(reg);
59 pup &= ~(3 << shift);
60 pup |= pull << shift;
61 __raw_writel(pup, reg);
62
63 return 0;
64}
65
66samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
67 unsigned int off)
68{
69 void __iomem *reg = chip->base + 0x08;
70 int shift = off * 2;
71 u32 pup = __raw_readl(reg);
72
73 pup >>= shift;
74 pup &= 0x3;
75
76 return (__force samsung_gpio_pull_t)pup;
77}
78
79int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
80 unsigned int off, samsung_gpio_pull_t pull)
81{
82 switch (pull) {
83 case S3C_GPIO_PULL_NONE:
84 pull = 0x01;
85 break;
86 case S3C_GPIO_PULL_UP:
87 pull = 0x00;
88 break;
89 case S3C_GPIO_PULL_DOWN:
90 pull = 0x02;
91 break;
92 }
93 return samsung_gpio_setpull_updown(chip, off, pull);
94}
95
96samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
97 unsigned int off)
98{
99 samsung_gpio_pull_t pull;
100
101 pull = samsung_gpio_getpull_updown(chip, off);
102
103 switch (pull) {
104 case 0x00:
105 pull = S3C_GPIO_PULL_UP;
106 break;
107 case 0x01:
108 case 0x03:
109 pull = S3C_GPIO_PULL_NONE;
110 break;
111 case 0x02:
112 pull = S3C_GPIO_PULL_DOWN;
113 break;
114 }
115
116 return pull;
117}
118
119static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
120 unsigned int off, samsung_gpio_pull_t pull,
121 samsung_gpio_pull_t updown)
122{
123 void __iomem *reg = chip->base + 0x08;
124 u32 pup = __raw_readl(reg);
125
126 if (pull == updown)
127 pup &= ~(1 << off);
128 else if (pull == S3C_GPIO_PULL_NONE)
129 pup |= (1 << off);
130 else
131 return -EINVAL;
132
133 __raw_writel(pup, reg);
134 return 0;
135}
136
137static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
138 unsigned int off,
139 samsung_gpio_pull_t updown)
140{
141 void __iomem *reg = chip->base + 0x08;
142 u32 pup = __raw_readl(reg);
143
144 pup &= (1 << off);
145 return pup ? S3C_GPIO_PULL_NONE : updown;
146}
147
148samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
149 unsigned int off)
150{
151 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
152}
153
154int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
155 unsigned int off, samsung_gpio_pull_t pull)
156{
157 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
158}
159
160samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
161 unsigned int off)
162{
163 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
164}
165
166int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
168{
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
170}
171
a9696d84 172static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 173 unsigned int off, samsung_gpio_pull_t pull)
174{
175 if (pull == S3C_GPIO_PULL_UP)
176 pull = 3;
177
178 return samsung_gpio_setpull_updown(chip, off, pull);
179}
180
a9696d84 181static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 182 unsigned int off)
183{
184 samsung_gpio_pull_t pull;
185
186 pull = samsung_gpio_getpull_updown(chip, off);
187
188 if (pull == 3)
189 pull = S3C_GPIO_PULL_UP;
190
191 return pull;
192}
193
194/*
195 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
196 * @chip: The gpio chip that is being configured.
197 * @off: The offset for the GPIO being configured.
198 * @cfg: The configuration value to set.
199 *
200 * This helper deal with the GPIO cases where the control register
201 * has two bits of configuration per gpio, which have the following
202 * functions:
203 * 00 = input
204 * 01 = output
205 * 1x = special function
206 */
207
208static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
209 unsigned int off, unsigned int cfg)
210{
211 void __iomem *reg = chip->base;
212 unsigned int shift = off * 2;
213 u32 con;
214
215 if (samsung_gpio_is_cfg_special(cfg)) {
216 cfg &= 0xf;
217 if (cfg > 3)
218 return -EINVAL;
219
220 cfg <<= shift;
221 }
222
223 con = __raw_readl(reg);
224 con &= ~(0x3 << shift);
225 con |= cfg;
226 __raw_writel(con, reg);
227
228 return 0;
229}
230
231/*
232 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
233 * @chip: The gpio chip that is being configured.
234 * @off: The offset for the GPIO being configured.
235 *
f1347599 236 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
1b39d5f2
KK		 237 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
238 * S3C_GPIO_SPECIAL() macro.
239 */
240
241static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
242 unsigned int off)
243{
244 u32 con;
245
246 con = __raw_readl(chip->base);
247 con >>= off * 2;
248 con &= 3;
249
250 /* this conversion works for IN and OUT as well as special mode */
251 return S3C_GPIO_SPECIAL(con);
252}
253
254/*
255 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
256 * @chip: The gpio chip that is being configured.
257 * @off: The offset for the GPIO being configured.
258 * @cfg: The configuration value to set.
259 *
260 * This helper deal with the GPIO cases where the control register has 4 bits
261 * of control per GPIO, generally in the form of:
262 * 0000 = Input
263 * 0001 = Output
264 * others = Special functions (dependent on bank)
265 *
266 * Note, since the code to deal with the case where there are two control
267 * registers instead of one, we do not have a separate set of functions for
268 * each case.
269 */
270
271static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
272 unsigned int off, unsigned int cfg)
273{
274 void __iomem *reg = chip->base;
275 unsigned int shift = (off & 7) * 4;
276 u32 con;
277
278 if (off < 8 && chip->chip.ngpio > 8)
279 reg -= 4;
280
281 if (samsung_gpio_is_cfg_special(cfg)) {
282 cfg &= 0xf;
283 cfg <<= shift;
284 }
285
286 con = __raw_readl(reg);
287 con &= ~(0xf << shift);
288 con |= cfg;
289 __raw_writel(con, reg);
290
291 return 0;
292}
293
294/*
295 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
296 * @chip: The gpio chip that is being configured.
297 * @off: The offset for the GPIO being configured.
298 *
299 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
300 * register setting into a value the software can use, such as could be passed
301 * to samsung_gpio_setcfg_4bit().
302 *
303 * @sa samsung_gpio_getcfg_2bit
304 */
305
306static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
307 unsigned int off)
308{
309 void __iomem *reg = chip->base;
310 unsigned int shift = (off & 7) * 4;
311 u32 con;
312
313 if (off < 8 && chip->chip.ngpio > 8)
314 reg -= 4;
315
316 con = __raw_readl(reg);
317 con >>= shift;
318 con &= 0xf;
319
320 /* this conversion works for IN and OUT as well as special mode */
321 return S3C_GPIO_SPECIAL(con);
322}
323
c034b184 324#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 325/*
326 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
327 * @chip: The gpio chip that is being configured.
328 * @off: The offset for the GPIO being configured.
329 * @cfg: The configuration value to set.
330 *
331 * This helper deal with the GPIO cases where the control register
332 * has one bit of configuration for the gpio, where setting the bit
333 * means the pin is in special function mode and unset means output.
334 */
335
336static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
337 unsigned int off, unsigned int cfg)
338{
339 void __iomem *reg = chip->base;
340 unsigned int shift = off;
341 u32 con;
342
343 if (samsung_gpio_is_cfg_special(cfg)) {
344 cfg &= 0xf;
345
346 /* Map output to 0, and SFN2 to 1 */
347 cfg -= 1;
348 if (cfg > 1)
349 return -EINVAL;
350
351 cfg <<= shift;
352 }
353
354 con = __raw_readl(reg);
355 con &= ~(0x1 << shift);
356 con |= cfg;
357 __raw_writel(con, reg);
358
359 return 0;
360}
361
362/*
363 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
364 * @chip: The gpio chip that is being configured.
365 * @off: The offset for the GPIO being configured.
366 *
367 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
368 * GPIO configuration value.
369 *
370 * @sa samsung_gpio_getcfg_2bit
371 * @sa samsung_gpio_getcfg_4bit
372 */
373
374static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
375 unsigned int off)
376{
377 u32 con;
378
379 con = __raw_readl(chip->base);
380 con >>= off;
381 con &= 1;
382 con++;
383
384 return S3C_GPIO_SFN(con);
385}
c034b184 386#endif
1b39d5f2 387
c034b184 388#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 389static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
390 unsigned int off, unsigned int cfg)
391{
392 void __iomem *reg = chip->base;
393 unsigned int shift;
394 u32 con;
395
396 switch (off) {
397 case 0:
398 case 1:
399 case 2:
400 case 3:
401 case 4:
402 case 5:
403 shift = (off & 7) * 4;
404 reg -= 4;
405 break;
406 case 6:
407 shift = ((off + 1) & 7) * 4;
408 reg -= 4;
409 default:
410 shift = ((off + 1) & 7) * 4;
411 break;
412 }
413
414 if (samsung_gpio_is_cfg_special(cfg)) {
415 cfg &= 0xf;
416 cfg <<= shift;
417 }
418
419 con = __raw_readl(reg);
420 con &= ~(0xf << shift);
421 con |= cfg;
422 __raw_writel(con, reg);
423
424 return 0;
425}
c034b184 426#endif
1b39d5f2
KK		 427
428static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
429 int nr_chips)
430{
431 for (; nr_chips > 0; nr_chips--, chipcfg++) {
432 if (!chipcfg->set_config)
433 chipcfg->set_config = samsung_gpio_setcfg_4bit;
434 if (!chipcfg->get_config)
435 chipcfg->get_config = samsung_gpio_getcfg_4bit;
436 if (!chipcfg->set_pull)
437 chipcfg->set_pull = samsung_gpio_setpull_updown;
438 if (!chipcfg->get_pull)
439 chipcfg->get_pull = samsung_gpio_getpull_updown;
440 }
441}
442
443struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
444 .set_config = samsung_gpio_setcfg_2bit,
445 .get_config = samsung_gpio_getcfg_2bit,
446};
447
c034b184 448#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 449static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
450 .set_config = s3c24xx_gpio_setcfg_abank,
451 .get_config = s3c24xx_gpio_getcfg_abank,
452};
c034b184 453#endif
1b39d5f2 454
2760f7ad 455#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
a9696d84
SP		 456static struct samsung_gpio_cfg exynos_gpio_cfg = {
457 .set_pull = exynos_gpio_setpull,
458 .get_pull = exynos_gpio_getpull,
f79e40eb
MS		 459 .set_config = samsung_gpio_setcfg_4bit,
460 .get_config = samsung_gpio_getcfg_4bit,
1b39d5f2 461};
2760f7ad 462#endif
1b39d5f2 463
c034b184 464#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 465static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
466 .cfg_eint = 0x3,
467 .set_config = s5p64x0_gpio_setcfg_rbank,
468 .get_config = samsung_gpio_getcfg_4bit,
469 .set_pull = samsung_gpio_setpull_updown,
470 .get_pull = samsung_gpio_getpull_updown,
471};
c034b184 472#endif
1b39d5f2
KK		 473
474static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
2985479f 475 [0] = {
1b39d5f2 476 .cfg_eint = 0x0,
2985479f
MB		 477 },
478 [1] = {
1b39d5f2 479 .cfg_eint = 0x3,
2985479f
MB		 480 },
481 [2] = {
1b39d5f2 482 .cfg_eint = 0x7,
2985479f
MB		 483 },
484 [3] = {
1b39d5f2 485 .cfg_eint = 0xF,
2985479f
MB		 486 },
487 [4] = {
1b39d5f2
KK		 488 .cfg_eint = 0x0,
489 .set_config = samsung_gpio_setcfg_2bit,
490 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 491 },
492 [5] = {
1b39d5f2
KK		 493 .cfg_eint = 0x2,
494 .set_config = samsung_gpio_setcfg_2bit,
495 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 496 },
497 [6] = {
1b39d5f2
KK		 498 .cfg_eint = 0x3,
499 .set_config = samsung_gpio_setcfg_2bit,
500 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 501 },
502 [7] = {
1b39d5f2
KK		 503 .set_config = samsung_gpio_setcfg_2bit,
504 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 505 },
506 [8] = {
a9696d84
SP		 507 .set_pull = exynos_gpio_setpull,
508 .get_pull = exynos_gpio_getpull,
2985479f
MB		 509 },
510 [9] = {
b82cee24 511 .cfg_eint = 0x3,
a9696d84
SP		 512 .set_pull = exynos_gpio_setpull,
513 .get_pull = exynos_gpio_getpull,
b82cee24 514 }
1b39d5f2
KK		 515};
516
517/*
518 * Default routines for controlling GPIO, based on the original S3C24XX
519 * GPIO functions which deal with the case where each gpio bank of the
520 * chip is as following:
521 *
522 * base + 0x00: Control register, 2 bits per gpio
523 * gpio n: 2 bits starting at (2*n)
524 * 00 = input, 01 = output, others mean special-function
525 * base + 0x04: Data register, 1 bit per gpio
526 * bit n: data bit n
527*/
528
529static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
530{
531 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
532 void __iomem *base = ourchip->base;
533 unsigned long flags;
534 unsigned long con;
535
536 samsung_gpio_lock(ourchip, flags);
537
538 con = __raw_readl(base + 0x00);
539 con &= ~(3 << (offset * 2));
540
541 __raw_writel(con, base + 0x00);
542
543 samsung_gpio_unlock(ourchip, flags);
544 return 0;
545}
546
547static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
548 unsigned offset, int value)
549{
550 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
551 void __iomem *base = ourchip->base;
552 unsigned long flags;
553 unsigned long dat;
554 unsigned long con;
555
556 samsung_gpio_lock(ourchip, flags);
557
558 dat = __raw_readl(base + 0x04);
559 dat &= ~(1 << offset);
560 if (value)
561 dat |= 1 << offset;
562 __raw_writel(dat, base + 0x04);
563
564 con = __raw_readl(base + 0x00);
565 con &= ~(3 << (offset * 2));
566 con |= 1 << (offset * 2);
567
568 __raw_writel(con, base + 0x00);
569 __raw_writel(dat, base + 0x04);
570
571 samsung_gpio_unlock(ourchip, flags);
572 return 0;
573}
574
575/*
576 * The samsung_gpiolib_4bit routines are to control the gpio banks where
577 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
578 * following example:
579 *
580 * base + 0x00: Control register, 4 bits per gpio
581 * gpio n: 4 bits starting at (4*n)
582 * 0000 = input, 0001 = output, others mean special-function
583 * base + 0x04: Data register, 1 bit per gpio
584 * bit n: data bit n
585 *
586 * Note, since the data register is one bit per gpio and is at base + 0x4
587 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
588 * state of the output.
589 */
590
591static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
592 unsigned int offset)
593{
594 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
595 void __iomem *base = ourchip->base;
596 unsigned long con;
597
598 con = __raw_readl(base + GPIOCON_OFF);
599 con &= ~(0xf << con_4bit_shift(offset));
600 __raw_writel(con, base + GPIOCON_OFF);
601
602 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
603
604 return 0;
605}
606
607static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
608 unsigned int offset, int value)
609{
610 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
611 void __iomem *base = ourchip->base;
612 unsigned long con;
613 unsigned long dat;
614
615 con = __raw_readl(base + GPIOCON_OFF);
616 con &= ~(0xf << con_4bit_shift(offset));
617 con |= 0x1 << con_4bit_shift(offset);
618
619 dat = __raw_readl(base + GPIODAT_OFF);
620
621 if (value)
622 dat |= 1 << offset;
623 else
624 dat &= ~(1 << offset);
625
626 __raw_writel(dat, base + GPIODAT_OFF);
627 __raw_writel(con, base + GPIOCON_OFF);
628 __raw_writel(dat, base + GPIODAT_OFF);
629
630 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
631
632 return 0;
633}
634
635/*
636 * The next set of routines are for the case where the GPIO configuration
637 * registers are 4 bits per GPIO but there is more than one register (the
638 * bank has more than 8 GPIOs.
639 *
640 * This case is the similar to the 4 bit case, but the registers are as
641 * follows:
642 *
643 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
644 * gpio n: 4 bits starting at (4*n)
645 * 0000 = input, 0001 = output, others mean special-function
646 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
647 * gpio n: 4 bits starting at (4*n)
648 * 0000 = input, 0001 = output, others mean special-function
649 * base + 0x08: Data register, 1 bit per gpio
650 * bit n: data bit n
651 *
652 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
653 * routines we store the 'base + 0x4' address so that these routines see
654 * the data register at ourchip->base + 0x04.
655 */
656
657static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
658 unsigned int offset)
659{
660 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
661 void __iomem *base = ourchip->base;
662 void __iomem *regcon = base;
663 unsigned long con;
664
665 if (offset > 7)
666 offset -= 8;
667 else
668 regcon -= 4;
669
670 con = __raw_readl(regcon);
671 con &= ~(0xf << con_4bit_shift(offset));
672 __raw_writel(con, regcon);
673
674 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
675
676 return 0;
677}
678
679static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
680 unsigned int offset, int value)
681{
682 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
683 void __iomem *base = ourchip->base;
684 void __iomem *regcon = base;
685 unsigned long con;
686 unsigned long dat;
687 unsigned con_offset = offset;
688
689 if (con_offset > 7)
690 con_offset -= 8;
691 else
692 regcon -= 4;
693
694 con = __raw_readl(regcon);
695 con &= ~(0xf << con_4bit_shift(con_offset));
696 con |= 0x1 << con_4bit_shift(con_offset);
697
698 dat = __raw_readl(base + GPIODAT_OFF);
699
700 if (value)
701 dat |= 1 << offset;
702 else
703 dat &= ~(1 << offset);
704
705 __raw_writel(dat, base + GPIODAT_OFF);
706 __raw_writel(con, regcon);
707 __raw_writel(dat, base + GPIODAT_OFF);
708
709 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
710
711 return 0;
712}
713
c034b184 714#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 715/* The next set of routines are for the case of s3c24xx bank a */
716
717static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
718{
719 return -EINVAL;
720}
721
722static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
723 unsigned offset, int value)
724{
725 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
726 void __iomem *base = ourchip->base;
727 unsigned long flags;
728 unsigned long dat;
729 unsigned long con;
730
731 local_irq_save(flags);
732
733 con = __raw_readl(base + 0x00);
734 dat = __raw_readl(base + 0x04);
735
736 dat &= ~(1 << offset);
737 if (value)
738 dat |= 1 << offset;
739
740 __raw_writel(dat, base + 0x04);
741
742 con &= ~(1 << offset);
743
744 __raw_writel(con, base + 0x00);
745 __raw_writel(dat, base + 0x04);
746
747 local_irq_restore(flags);
748 return 0;
749}
c034b184 750#endif
1b39d5f2
KK		 751
752/* The next set of routines are for the case of s5p64x0 bank r */
753
754static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
755 unsigned int offset)
756{
757 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
758 void __iomem *base = ourchip->base;
759 void __iomem *regcon = base;
760 unsigned long con;
761 unsigned long flags;
762
763 switch (offset) {
764 case 6:
765 offset += 1;
766 case 0:
767 case 1:
768 case 2:
769 case 3:
770 case 4:
771 case 5:
772 regcon -= 4;
773 break;
774 default:
775 offset -= 7;
776 break;
777 }
778
779 samsung_gpio_lock(ourchip, flags);
780
781 con = __raw_readl(regcon);
782 con &= ~(0xf << con_4bit_shift(offset));
783 __raw_writel(con, regcon);
784
785 samsung_gpio_unlock(ourchip, flags);
786
787 return 0;
788}
789
790static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
791 unsigned int offset, int value)
792{
793 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
794 void __iomem *base = ourchip->base;
795 void __iomem *regcon = base;
796 unsigned long con;
797 unsigned long dat;
798 unsigned long flags;
799 unsigned con_offset = offset;
800
801 switch (con_offset) {
802 case 6:
803 con_offset += 1;
804 case 0:
805 case 1:
806 case 2:
807 case 3:
808 case 4:
809 case 5:
810 regcon -= 4;
811 break;
812 default:
813 con_offset -= 7;
814 break;
815 }
816
817 samsung_gpio_lock(ourchip, flags);
818
819 con = __raw_readl(regcon);
820 con &= ~(0xf << con_4bit_shift(con_offset));
821 con |= 0x1 << con_4bit_shift(con_offset);
822
823 dat = __raw_readl(base + GPIODAT_OFF);
824 if (value)
825 dat |= 1 << offset;
826 else
827 dat &= ~(1 << offset);
828
829 __raw_writel(con, regcon);
830 __raw_writel(dat, base + GPIODAT_OFF);
831
832 samsung_gpio_unlock(ourchip, flags);
833
834 return 0;
835}
836
837static void samsung_gpiolib_set(struct gpio_chip *chip,
838 unsigned offset, int value)
839{
840 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
841 void __iomem *base = ourchip->base;
842 unsigned long flags;
843 unsigned long dat;
844
845 samsung_gpio_lock(ourchip, flags);
846
847 dat = __raw_readl(base + 0x04);
848 dat &= ~(1 << offset);
849 if (value)
850 dat |= 1 << offset;
851 __raw_writel(dat, base + 0x04);
852
853 samsung_gpio_unlock(ourchip, flags);
854}
855
856static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
857{
858 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
859 unsigned long val;
860
861 val = __raw_readl(ourchip->base + 0x04);
862 val >>= offset;
863 val &= 1;
864
865 return val;
866}
867
868/*
869 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
870 * for use with the configuration calls, and other parts of the s3c gpiolib
871 * support code.
872 *
873 * Not all s3c support code will need this, as some configurations of cpu
874 * may only support one or two different configuration options and have an
875 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
876 * the machine support file should provide its own samsung_gpiolib_getchip()
877 * and any other necessary functions.
878 */
879
880#ifdef CONFIG_S3C_GPIO_TRACK
881struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
882
883static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
884{
885 unsigned int gpn;
886 int i;
887
888 gpn = chip->chip.base;
889 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
890 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
891 s3c_gpios[gpn] = chip;
892 }
893}
894#endif /* CONFIG_S3C_GPIO_TRACK */
895
896/*
897 * samsung_gpiolib_add() - add the Samsung gpio_chip.
898 * @chip: The chip to register
899 *
900 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
901 * information and makes the necessary alterations for the platform and
902 * notes the information for use with the configuration systems and any
903 * other parts of the system.
904 */
905
906static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
907{
908 struct gpio_chip *gc = &chip->chip;
909 int ret;
910
911 BUG_ON(!chip->base);
912 BUG_ON(!gc->label);
913 BUG_ON(!gc->ngpio);
914
915 spin_lock_init(&chip->lock);
916
917 if (!gc->direction_input)
918 gc->direction_input = samsung_gpiolib_2bit_input;
919 if (!gc->direction_output)
920 gc->direction_output = samsung_gpiolib_2bit_output;
921 if (!gc->set)
922 gc->set = samsung_gpiolib_set;
923 if (!gc->get)
924 gc->get = samsung_gpiolib_get;
925
926#ifdef CONFIG_PM
927 if (chip->pm != NULL) {
928 if (!chip->pm->save || !chip->pm->resume)
929 printk(KERN_ERR "gpio: %s has missing PM functions\n",
930 gc->label);
931 } else
932 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
933#endif
934
935 /* gpiochip_add() prints own failure message on error. */
936 ret = gpiochip_add(gc);
937 if (ret >= 0)
938 s3c_gpiolib_track(chip);
939}
940
172c6a13
HS		 941#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
942static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
943 const struct of_phandle_args *gpiospec, u32 *flags)
944{
945 unsigned int pin;
946
947 if (WARN_ON(gc->of_gpio_n_cells < 3))
948 return -EINVAL;
949
950 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
951 return -EINVAL;
952
953 if (gpiospec->args[0] > gc->ngpio)
954 return -EINVAL;
955
956 pin = gc->base + gpiospec->args[0];
957
958 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
959 pr_warn("gpio_xlate: failed to set pin function\n");
960 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
961 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
962
963 if (flags)
964 *flags = gpiospec->args[2] >> 16;
965
966 return gpiospec->args[0];
967}
968
969static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
970 { .compatible = "samsung,s3c24xx-gpio", },
971 {}
972};
973
974static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
975 u64 base, u64 offset)
976{
977 struct gpio_chip *gc = &chip->chip;
978 u64 address;
979
980 if (!of_have_populated_dt())
981 return;
982
983 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
984 gc->of_node = of_find_matching_node_by_address(NULL,
985 s3c24xx_gpio_dt_match, address);
986 if (!gc->of_node) {
987 pr_info("gpio: device tree node not found for gpio controller"
988 " with base address %08llx\n", address);
989 return;
990 }
991 gc->of_gpio_n_cells = 3;
992 gc->of_xlate = s3c24xx_gpio_xlate;
993}
994#else
995static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
996 u64 base, u64 offset)
997{
998 return;
999}
1000#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
1001
1b39d5f2
KK		 1002static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1003 int nr_chips, void __iomem *base)
1004{
1005 int i;
1006 struct gpio_chip *gc = &chip->chip;
1007
1008 for (i = 0 ; i < nr_chips; i++, chip++) {
8a8ab2e6
PK		 1009 /* skip banks not present on SoC */
1010 if (chip->chip.base >= S3C_GPIO_END)
1011 continue;
1012
1b39d5f2
KK		 1013 if (!chip->config)
1014 chip->config = &s3c24xx_gpiocfg_default;
1015 if (!chip->pm)
1016 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1017 if ((base != NULL) && (chip->base == NULL))
1018 chip->base = base + ((i) * 0x10);
1019
1020 if (!gc->direction_input)
1021 gc->direction_input = samsung_gpiolib_2bit_input;
1022 if (!gc->direction_output)
1023 gc->direction_output = samsung_gpiolib_2bit_output;
1024
1025 samsung_gpiolib_add(chip);
172c6a13
HS		 1026
1027 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1b39d5f2
KK		 1028 }
1029}
1030
1031static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1032 int nr_chips, void __iomem *base,
1033 unsigned int offset)
1034{
1035 int i;
1036
1037 for (i = 0 ; i < nr_chips; i++, chip++) {
1038 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1039 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1040
1041 if (!chip->config)
1042 chip->config = &samsung_gpio_cfgs[7];
1043 if (!chip->pm)
1044 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1045 if ((base != NULL) && (chip->base == NULL))
1046 chip->base = base + ((i) * offset);
1047
1048 samsung_gpiolib_add(chip);
1049 }
1050}
1051
1052/*
1053 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1054 * @chip: The gpio chip that is being configured.
1055 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1056 *
1057 * This helper deal with the GPIO cases where the control register has 4 bits
1058 * of control per GPIO, generally in the form of:
1059 * 0000 = Input
1060 * 0001 = Output
1061 * others = Special functions (dependent on bank)
1062 *
1063 * Note, since the code to deal with the case where there are two control
1064 * registers instead of one, we do not have a separate set of function
1065 * (samsung_gpiolib_add_4bit2_chips)for each case.
1066 */
1067
1068static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1069 int nr_chips, void __iomem *base)
1070{
1071 int i;
1072
1073 for (i = 0 ; i < nr_chips; i++, chip++) {
1074 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1075 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1076
1077 if (!chip->config)
1078 chip->config = &samsung_gpio_cfgs[2];
1079 if (!chip->pm)
1080 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1081 if ((base != NULL) && (chip->base == NULL))
1082 chip->base = base + ((i) * 0x20);
1083
1084 samsung_gpiolib_add(chip);
1085 }
1086}
1087
1088static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1089 int nr_chips)
1090{
1091 for (; nr_chips > 0; nr_chips--, chip++) {
1092 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1093 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1094
1095 if (!chip->config)
1096 chip->config = &samsung_gpio_cfgs[2];
1097 if (!chip->pm)
1098 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1099
1100 samsung_gpiolib_add(chip);
1101 }
1102}
1103
1104static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1105 int nr_chips)
1106{
1107 for (; nr_chips > 0; nr_chips--, chip++) {
1108 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1109 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1110
1111 if (!chip->pm)
1112 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1113
1114 samsung_gpiolib_add(chip);
1115 }
1116}
1117
1118int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1119{
1120 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1121
1122 return samsung_chip->irq_base + offset;
1123}
1124
1125#ifdef CONFIG_PLAT_S3C24XX
1126static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1127{
1128 if (offset < 4)
1129 return IRQ_EINT0 + offset;
1130
1131 if (offset < 8)
1132 return IRQ_EINT4 + offset - 4;
1133
1134 return -EINVAL;
1135}
1136#endif
1137
1138#ifdef CONFIG_PLAT_S3C64XX
1139static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1140{
1141 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1142}
1143
1144static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1145{
1146 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1147}
1148#endif
1149
1150struct samsung_gpio_chip s3c24xx_gpios[] = {
1151#ifdef CONFIG_PLAT_S3C24XX
1152 {
1153 .config = &s3c24xx_gpiocfg_banka,
1154 .chip = {
1155 .base = S3C2410_GPA(0),
1156 .owner = THIS_MODULE,
1157 .label = "GPIOA",
1158 .ngpio = 24,
1159 .direction_input = s3c24xx_gpiolib_banka_input,
1160 .direction_output = s3c24xx_gpiolib_banka_output,
1161 },
1162 }, {
1163 .chip = {
1164 .base = S3C2410_GPB(0),
1165 .owner = THIS_MODULE,
1166 .label = "GPIOB",
1167 .ngpio = 16,
1168 },
1169 }, {
1170 .chip = {
1171 .base = S3C2410_GPC(0),
1172 .owner = THIS_MODULE,
1173 .label = "GPIOC",
1174 .ngpio = 16,
1175 },
1176 }, {
1177 .chip = {
1178 .base = S3C2410_GPD(0),
1179 .owner = THIS_MODULE,
1180 .label = "GPIOD",
1181 .ngpio = 16,
1182 },
1183 }, {
1184 .chip = {
1185 .base = S3C2410_GPE(0),
1186 .label = "GPIOE",
1187 .owner = THIS_MODULE,
1188 .ngpio = 16,
1189 },
1190 }, {
1191 .chip = {
1192 .base = S3C2410_GPF(0),
1193 .owner = THIS_MODULE,
1194 .label = "GPIOF",
1195 .ngpio = 8,
1196 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1197 },
1198 }, {
1199 .irq_base = IRQ_EINT8,
1200 .chip = {
1201 .base = S3C2410_GPG(0),
1202 .owner = THIS_MODULE,
1203 .label = "GPIOG",
1204 .ngpio = 16,
1205 .to_irq = samsung_gpiolib_to_irq,
1206 },
1207 }, {
1208 .chip = {
1209 .base = S3C2410_GPH(0),
1210 .owner = THIS_MODULE,
1211 .label = "GPIOH",
1212 .ngpio = 11,
1213 },
1214 },
1215 /* GPIOS for the S3C2443 and later devices. */
1216 {
1217 .base = S3C2440_GPJCON,
1218 .chip = {
1219 .base = S3C2410_GPJ(0),
1220 .owner = THIS_MODULE,
1221 .label = "GPIOJ",
1222 .ngpio = 16,
1223 },
1224 }, {
1225 .base = S3C2443_GPKCON,
1226 .chip = {
1227 .base = S3C2410_GPK(0),
1228 .owner = THIS_MODULE,
1229 .label = "GPIOK",
1230 .ngpio = 16,
1231 },
1232 }, {
1233 .base = S3C2443_GPLCON,
1234 .chip = {
1235 .base = S3C2410_GPL(0),
1236 .owner = THIS_MODULE,
1237 .label = "GPIOL",
1238 .ngpio = 15,
1239 },
1240 }, {
1241 .base = S3C2443_GPMCON,
1242 .chip = {
1243 .base = S3C2410_GPM(0),
1244 .owner = THIS_MODULE,
1245 .label = "GPIOM",
1246 .ngpio = 2,
1247 },
1248 },
1249#endif
1250};
1251
1252/*
1253 * GPIO bank summary:
1254 *
1255 * Bank GPIOs Style SlpCon ExtInt Group
1256 * A 8 4Bit Yes 1
1257 * B 7 4Bit Yes 1
1258 * C 8 4Bit Yes 2
1259 * D 5 4Bit Yes 3
1260 * E 5 4Bit Yes None
1261 * F 16 2Bit Yes 4 [1]
1262 * G 7 4Bit Yes 5
1263 * H 10 4Bit[2] Yes 6
1264 * I 16 2Bit Yes None
1265 * J 12 2Bit Yes None
1266 * K 16 4Bit[2] No None
1267 * L 15 4Bit[2] No None
1268 * M 6 4Bit No IRQ_EINT
1269 * N 16 2Bit No IRQ_EINT
1270 * O 16 2Bit Yes 7
1271 * P 15 2Bit Yes 8
1272 * Q 9 2Bit Yes 9
1273 *
1274 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1275 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1276 */
1277
1278static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1279#ifdef CONFIG_PLAT_S3C64XX
1280 {
1281 .chip = {
1282 .base = S3C64XX_GPA(0),
1283 .ngpio = S3C64XX_GPIO_A_NR,
1284 .label = "GPA",
1285 },
1286 }, {
1287 .chip = {
1288 .base = S3C64XX_GPB(0),
1289 .ngpio = S3C64XX_GPIO_B_NR,
1290 .label = "GPB",
1291 },
1292 }, {
1293 .chip = {
1294 .base = S3C64XX_GPC(0),
1295 .ngpio = S3C64XX_GPIO_C_NR,
1296 .label = "GPC",
1297 },
1298 }, {
1299 .chip = {
1300 .base = S3C64XX_GPD(0),
1301 .ngpio = S3C64XX_GPIO_D_NR,
1302 .label = "GPD",
1303 },
1304 }, {
1305 .config = &samsung_gpio_cfgs[0],
1306 .chip = {
1307 .base = S3C64XX_GPE(0),
1308 .ngpio = S3C64XX_GPIO_E_NR,
1309 .label = "GPE",
1310 },
1311 }, {
1312 .base = S3C64XX_GPG_BASE,
1313 .chip = {
1314 .base = S3C64XX_GPG(0),
1315 .ngpio = S3C64XX_GPIO_G_NR,
1316 .label = "GPG",
1317 },
1318 }, {
1319 .base = S3C64XX_GPM_BASE,
1320 .config = &samsung_gpio_cfgs[1],
1321 .chip = {
1322 .base = S3C64XX_GPM(0),
1323 .ngpio = S3C64XX_GPIO_M_NR,
1324 .label = "GPM",
1325 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1326 },
1327 },
1328#endif
1329};
1330
1331static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1332#ifdef CONFIG_PLAT_S3C64XX
1333 {
1334 .base = S3C64XX_GPH_BASE + 0x4,
1335 .chip = {
1336 .base = S3C64XX_GPH(0),
1337 .ngpio = S3C64XX_GPIO_H_NR,
1338 .label = "GPH",
1339 },
1340 }, {
1341 .base = S3C64XX_GPK_BASE + 0x4,
1342 .config = &samsung_gpio_cfgs[0],
1343 .chip = {
1344 .base = S3C64XX_GPK(0),
1345 .ngpio = S3C64XX_GPIO_K_NR,
1346 .label = "GPK",
1347 },
1348 }, {
1349 .base = S3C64XX_GPL_BASE + 0x4,
1350 .config = &samsung_gpio_cfgs[1],
1351 .chip = {
1352 .base = S3C64XX_GPL(0),
1353 .ngpio = S3C64XX_GPIO_L_NR,
1354 .label = "GPL",
1355 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1356 },
1357 },
1358#endif
1359};
1360
1361static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1362#ifdef CONFIG_PLAT_S3C64XX
1363 {
1364 .base = S3C64XX_GPF_BASE,
1365 .config = &samsung_gpio_cfgs[6],
1366 .chip = {
1367 .base = S3C64XX_GPF(0),
1368 .ngpio = S3C64XX_GPIO_F_NR,
1369 .label = "GPF",
1370 },
1371 }, {
1372 .config = &samsung_gpio_cfgs[7],
1373 .chip = {
1374 .base = S3C64XX_GPI(0),
1375 .ngpio = S3C64XX_GPIO_I_NR,
1376 .label = "GPI",
1377 },
1378 }, {
1379 .config = &samsung_gpio_cfgs[7],
1380 .chip = {
1381 .base = S3C64XX_GPJ(0),
1382 .ngpio = S3C64XX_GPIO_J_NR,
1383 .label = "GPJ",
1384 },
1385 }, {
1386 .config = &samsung_gpio_cfgs[6],
1387 .chip = {
1388 .base = S3C64XX_GPO(0),
1389 .ngpio = S3C64XX_GPIO_O_NR,
1390 .label = "GPO",
1391 },
1392 }, {
1393 .config = &samsung_gpio_cfgs[6],
1394 .chip = {
1395 .base = S3C64XX_GPP(0),
1396 .ngpio = S3C64XX_GPIO_P_NR,
1397 .label = "GPP",
1398 },
1399 }, {
1400 .config = &samsung_gpio_cfgs[6],
1401 .chip = {
1402 .base = S3C64XX_GPQ(0),
1403 .ngpio = S3C64XX_GPIO_Q_NR,
1404 .label = "GPQ",
1405 },
1406 }, {
1407 .base = S3C64XX_GPN_BASE,
1408 .irq_base = IRQ_EINT(0),
1409 .config = &samsung_gpio_cfgs[5],
1410 .chip = {
1411 .base = S3C64XX_GPN(0),
1412 .ngpio = S3C64XX_GPIO_N_NR,
1413 .label = "GPN",
1414 .to_irq = samsung_gpiolib_to_irq,
1415 },
1416 },
1417#endif
1418};
1419
1420/*
1421 * S5P6440 GPIO bank summary:
1422 *
1423 * Bank GPIOs Style SlpCon ExtInt Group
1424 * A 6 4Bit Yes 1
1425 * B 7 4Bit Yes 1
1426 * C 8 4Bit Yes 2
1427 * F 2 2Bit Yes 4 [1]
1428 * G 7 4Bit Yes 5
1429 * H 10 4Bit[2] Yes 6
1430 * I 16 2Bit Yes None
1431 * J 12 2Bit Yes None
1432 * N 16 2Bit No IRQ_EINT
1433 * P 8 2Bit Yes 8
1434 * R 15 4Bit[2] Yes 8
1435 */
1436
1437static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1438#ifdef CONFIG_CPU_S5P6440
1439 {
1440 .chip = {
1441 .base = S5P6440_GPA(0),
1442 .ngpio = S5P6440_GPIO_A_NR,
1443 .label = "GPA",
1444 },
1445 }, {
1446 .chip = {
1447 .base = S5P6440_GPB(0),
1448 .ngpio = S5P6440_GPIO_B_NR,
1449 .label = "GPB",
1450 },
1451 }, {
1452 .chip = {
1453 .base = S5P6440_GPC(0),
1454 .ngpio = S5P6440_GPIO_C_NR,
1455 .label = "GPC",
1456 },
1457 }, {
1458 .base = S5P64X0_GPG_BASE,
1459 .chip = {
1460 .base = S5P6440_GPG(0),
1461 .ngpio = S5P6440_GPIO_G_NR,
1462 .label = "GPG",
1463 },
1464 },
1465#endif
1466};
1467
1468static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1469#ifdef CONFIG_CPU_S5P6440
1470 {
1471 .base = S5P64X0_GPH_BASE + 0x4,
1472 .chip = {
1473 .base = S5P6440_GPH(0),
1474 .ngpio = S5P6440_GPIO_H_NR,
1475 .label = "GPH",
1476 },
1477 },
1478#endif
1479};
1480
1481static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1482#ifdef CONFIG_CPU_S5P6440
1483 {
1484 .base = S5P64X0_GPR_BASE + 0x4,
1485 .config = &s5p64x0_gpio_cfg_rbank,
1486 .chip = {
1487 .base = S5P6440_GPR(0),
1488 .ngpio = S5P6440_GPIO_R_NR,
1489 .label = "GPR",
1490 },
1491 },
1492#endif
1493};
1494
1495static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1496#ifdef CONFIG_CPU_S5P6440
1497 {
1498 .base = S5P64X0_GPF_BASE,
1499 .config = &samsung_gpio_cfgs[6],
1500 .chip = {
1501 .base = S5P6440_GPF(0),
1502 .ngpio = S5P6440_GPIO_F_NR,
1503 .label = "GPF",
1504 },
1505 }, {
1506 .base = S5P64X0_GPI_BASE,
1507 .config = &samsung_gpio_cfgs[4],
1508 .chip = {
1509 .base = S5P6440_GPI(0),
1510 .ngpio = S5P6440_GPIO_I_NR,
1511 .label = "GPI",
1512 },
1513 }, {
1514 .base = S5P64X0_GPJ_BASE,
1515 .config = &samsung_gpio_cfgs[4],
1516 .chip = {
1517 .base = S5P6440_GPJ(0),
1518 .ngpio = S5P6440_GPIO_J_NR,
1519 .label = "GPJ",
1520 },
1521 }, {
1522 .base = S5P64X0_GPN_BASE,
1523 .config = &samsung_gpio_cfgs[5],
1524 .chip = {
1525 .base = S5P6440_GPN(0),
1526 .ngpio = S5P6440_GPIO_N_NR,
1527 .label = "GPN",
1528 },
1529 }, {
1530 .base = S5P64X0_GPP_BASE,
1531 .config = &samsung_gpio_cfgs[6],
1532 .chip = {
1533 .base = S5P6440_GPP(0),
1534 .ngpio = S5P6440_GPIO_P_NR,
1535 .label = "GPP",
1536 },
1537 },
1538#endif
1539};
1540
1541/*
1542 * S5P6450 GPIO bank summary:
1543 *
1544 * Bank GPIOs Style SlpCon ExtInt Group
1545 * A 6 4Bit Yes 1
1546 * B 7 4Bit Yes 1
1547 * C 8 4Bit Yes 2
1548 * D 8 4Bit Yes None
1549 * F 2 2Bit Yes None
1550 * G 14 4Bit[2] Yes 5
1551 * H 10 4Bit[2] Yes 6
1552 * I 16 2Bit Yes None
1553 * J 12 2Bit Yes None
1554 * K 5 4Bit Yes None
1555 * N 16 2Bit No IRQ_EINT
1556 * P 11 2Bit Yes 8
1557 * Q 14 2Bit Yes None
1558 * R 15 4Bit[2] Yes None
1559 * S 8 2Bit Yes None
1560 *
1561 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1562 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1563 */
1564
1565static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1566#ifdef CONFIG_CPU_S5P6450
1567 {
1568 .chip = {
1569 .base = S5P6450_GPA(0),
1570 .ngpio = S5P6450_GPIO_A_NR,
1571 .label = "GPA",
1572 },
1573 }, {
1574 .chip = {
1575 .base = S5P6450_GPB(0),
1576 .ngpio = S5P6450_GPIO_B_NR,
1577 .label = "GPB",
1578 },
1579 }, {
1580 .chip = {
1581 .base = S5P6450_GPC(0),
1582 .ngpio = S5P6450_GPIO_C_NR,
1583 .label = "GPC",
1584 },
1585 }, {
1586 .chip = {
1587 .base = S5P6450_GPD(0),
1588 .ngpio = S5P6450_GPIO_D_NR,
1589 .label = "GPD",
1590 },
1591 }, {
1592 .base = S5P6450_GPK_BASE,
1593 .chip = {
1594 .base = S5P6450_GPK(0),
1595 .ngpio = S5P6450_GPIO_K_NR,
1596 .label = "GPK",
1597 },
1598 },
1599#endif
1600};
1601
1602static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1603#ifdef CONFIG_CPU_S5P6450
1604 {
1605 .base = S5P64X0_GPG_BASE + 0x4,
1606 .chip = {
1607 .base = S5P6450_GPG(0),
1608 .ngpio = S5P6450_GPIO_G_NR,
1609 .label = "GPG",
1610 },
1611 }, {
1612 .base = S5P64X0_GPH_BASE + 0x4,
1613 .chip = {
1614 .base = S5P6450_GPH(0),
1615 .ngpio = S5P6450_GPIO_H_NR,
1616 .label = "GPH",
1617 },
1618 },
1619#endif
1620};
1621
1622static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1623#ifdef CONFIG_CPU_S5P6450
1624 {
1625 .base = S5P64X0_GPR_BASE + 0x4,
1626 .config = &s5p64x0_gpio_cfg_rbank,
1627 .chip = {
1628 .base = S5P6450_GPR(0),
1629 .ngpio = S5P6450_GPIO_R_NR,
1630 .label = "GPR",
1631 },
1632 },
1633#endif
1634};
1635
1636static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1637#ifdef CONFIG_CPU_S5P6450
1638 {
1639 .base = S5P64X0_GPF_BASE,
1640 .config = &samsung_gpio_cfgs[6],
1641 .chip = {
1642 .base = S5P6450_GPF(0),
1643 .ngpio = S5P6450_GPIO_F_NR,
1644 .label = "GPF",
1645 },
1646 }, {
1647 .base = S5P64X0_GPI_BASE,
1648 .config = &samsung_gpio_cfgs[4],
1649 .chip = {
1650 .base = S5P6450_GPI(0),
1651 .ngpio = S5P6450_GPIO_I_NR,
1652 .label = "GPI",
1653 },
1654 }, {
1655 .base = S5P64X0_GPJ_BASE,
1656 .config = &samsung_gpio_cfgs[4],
1657 .chip = {
1658 .base = S5P6450_GPJ(0),
1659 .ngpio = S5P6450_GPIO_J_NR,
1660 .label = "GPJ",
1661 },
1662 }, {
1663 .base = S5P64X0_GPN_BASE,
1664 .config = &samsung_gpio_cfgs[5],
1665 .chip = {
1666 .base = S5P6450_GPN(0),
1667 .ngpio = S5P6450_GPIO_N_NR,
1668 .label = "GPN",
1669 },
1670 }, {
1671 .base = S5P64X0_GPP_BASE,
1672 .config = &samsung_gpio_cfgs[6],
1673 .chip = {
1674 .base = S5P6450_GPP(0),
1675 .ngpio = S5P6450_GPIO_P_NR,
1676 .label = "GPP",
1677 },
1678 }, {
1679 .base = S5P6450_GPQ_BASE,
1680 .config = &samsung_gpio_cfgs[5],
1681 .chip = {
1682 .base = S5P6450_GPQ(0),
1683 .ngpio = S5P6450_GPIO_Q_NR,
1684 .label = "GPQ",
1685 },
1686 }, {
1687 .base = S5P6450_GPS_BASE,
1688 .config = &samsung_gpio_cfgs[6],
1689 .chip = {
1690 .base = S5P6450_GPS(0),
1691 .ngpio = S5P6450_GPIO_S_NR,
1692 .label = "GPS",
1693 },
1694 },
1695#endif
1696};
1697
1698/*
1699 * S5PC100 GPIO bank summary:
1700 *
1701 * Bank GPIOs Style INT Type
1702 * A0 8 4Bit GPIO_INT0
1703 * A1 5 4Bit GPIO_INT1
1704 * B 8 4Bit GPIO_INT2
1705 * C 5 4Bit GPIO_INT3
1706 * D 7 4Bit GPIO_INT4
1707 * E0 8 4Bit GPIO_INT5
1708 * E1 6 4Bit GPIO_INT6
1709 * F0 8 4Bit GPIO_INT7
1710 * F1 8 4Bit GPIO_INT8
1711 * F2 8 4Bit GPIO_INT9
1712 * F3 4 4Bit GPIO_INT10
1713 * G0 8 4Bit GPIO_INT11
1714 * G1 3 4Bit GPIO_INT12
1715 * G2 7 4Bit GPIO_INT13
1716 * G3 7 4Bit GPIO_INT14
1717 * H0 8 4Bit WKUP_INT
1718 * H1 8 4Bit WKUP_INT
1719 * H2 8 4Bit WKUP_INT
1720 * H3 8 4Bit WKUP_INT
1721 * I 8 4Bit GPIO_INT15
1722 * J0 8 4Bit GPIO_INT16
1723 * J1 5 4Bit GPIO_INT17
1724 * J2 8 4Bit GPIO_INT18
1725 * J3 8 4Bit GPIO_INT19
1726 * J4 4 4Bit GPIO_INT20
1727 * K0 8 4Bit None
1728 * K1 6 4Bit None
1729 * K2 8 4Bit None
1730 * K3 8 4Bit None
1731 * L0 8 4Bit None
1732 * L1 8 4Bit None
1733 * L2 8 4Bit None
1734 * L3 8 4Bit None
1735 */
1736
1737static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1738#ifdef CONFIG_CPU_S5PC100
1739 {
1740 .chip = {
1741 .base = S5PC100_GPA0(0),
1742 .ngpio = S5PC100_GPIO_A0_NR,
1743 .label = "GPA0",
1744 },
1745 }, {
1746 .chip = {
1747 .base = S5PC100_GPA1(0),
1748 .ngpio = S5PC100_GPIO_A1_NR,
1749 .label = "GPA1",
1750 },
1751 }, {
1752 .chip = {
1753 .base = S5PC100_GPB(0),
1754 .ngpio = S5PC100_GPIO_B_NR,
1755 .label = "GPB",
1756 },
1757 }, {
1758 .chip = {
1759 .base = S5PC100_GPC(0),
1760 .ngpio = S5PC100_GPIO_C_NR,
1761 .label = "GPC",
1762 },
1763 }, {
1764 .chip = {
1765 .base = S5PC100_GPD(0),
1766 .ngpio = S5PC100_GPIO_D_NR,
1767 .label = "GPD",
1768 },
1769 }, {
1770 .chip = {
1771 .base = S5PC100_GPE0(0),
1772 .ngpio = S5PC100_GPIO_E0_NR,
1773 .label = "GPE0",
1774 },
1775 }, {
1776 .chip = {
1777 .base = S5PC100_GPE1(0),
1778 .ngpio = S5PC100_GPIO_E1_NR,
1779 .label = "GPE1",
1780 },
1781 }, {
1782 .chip = {
1783 .base = S5PC100_GPF0(0),
1784 .ngpio = S5PC100_GPIO_F0_NR,
1785 .label = "GPF0",
1786 },
1787 }, {
1788 .chip = {
1789 .base = S5PC100_GPF1(0),
1790 .ngpio = S5PC100_GPIO_F1_NR,
1791 .label = "GPF1",
1792 },
1793 }, {
1794 .chip = {
1795 .base = S5PC100_GPF2(0),
1796 .ngpio = S5PC100_GPIO_F2_NR,
1797 .label = "GPF2",
1798 },
1799 }, {
1800 .chip = {
1801 .base = S5PC100_GPF3(0),
1802 .ngpio = S5PC100_GPIO_F3_NR,
1803 .label = "GPF3",
1804 },
1805 }, {
1806 .chip = {
1807 .base = S5PC100_GPG0(0),
1808 .ngpio = S5PC100_GPIO_G0_NR,
1809 .label = "GPG0",
1810 },
1811 }, {
1812 .chip = {
1813 .base = S5PC100_GPG1(0),
1814 .ngpio = S5PC100_GPIO_G1_NR,
1815 .label = "GPG1",
1816 },
1817 }, {
1818 .chip = {
1819 .base = S5PC100_GPG2(0),
1820 .ngpio = S5PC100_GPIO_G2_NR,
1821 .label = "GPG2",
1822 },
1823 }, {
1824 .chip = {
1825 .base = S5PC100_GPG3(0),
1826 .ngpio = S5PC100_GPIO_G3_NR,
1827 .label = "GPG3",
1828 },
1829 }, {
1830 .chip = {
1831 .base = S5PC100_GPI(0),
1832 .ngpio = S5PC100_GPIO_I_NR,
1833 .label = "GPI",
1834 },
1835 }, {
1836 .chip = {
1837 .base = S5PC100_GPJ0(0),
1838 .ngpio = S5PC100_GPIO_J0_NR,
1839 .label = "GPJ0",
1840 },
1841 }, {
1842 .chip = {
1843 .base = S5PC100_GPJ1(0),
1844 .ngpio = S5PC100_GPIO_J1_NR,
1845 .label = "GPJ1",
1846 },
1847 }, {
1848 .chip = {
1849 .base = S5PC100_GPJ2(0),
1850 .ngpio = S5PC100_GPIO_J2_NR,
1851 .label = "GPJ2",
1852 },
1853 }, {
1854 .chip = {
1855 .base = S5PC100_GPJ3(0),
1856 .ngpio = S5PC100_GPIO_J3_NR,
1857 .label = "GPJ3",
1858 },
1859 }, {
1860 .chip = {
1861 .base = S5PC100_GPJ4(0),
1862 .ngpio = S5PC100_GPIO_J4_NR,
1863 .label = "GPJ4",
1864 },
1865 }, {
1866 .chip = {
1867 .base = S5PC100_GPK0(0),
1868 .ngpio = S5PC100_GPIO_K0_NR,
1869 .label = "GPK0",
1870 },
1871 }, {
1872 .chip = {
1873 .base = S5PC100_GPK1(0),
1874 .ngpio = S5PC100_GPIO_K1_NR,
1875 .label = "GPK1",
1876 },
1877 }, {
1878 .chip = {
1879 .base = S5PC100_GPK2(0),
1880 .ngpio = S5PC100_GPIO_K2_NR,
1881 .label = "GPK2",
1882 },
1883 }, {
1884 .chip = {
1885 .base = S5PC100_GPK3(0),
1886 .ngpio = S5PC100_GPIO_K3_NR,
1887 .label = "GPK3",
1888 },
1889 }, {
1890 .chip = {
1891 .base = S5PC100_GPL0(0),
1892 .ngpio = S5PC100_GPIO_L0_NR,
1893 .label = "GPL0",
1894 },
1895 }, {
1896 .chip = {
1897 .base = S5PC100_GPL1(0),
1898 .ngpio = S5PC100_GPIO_L1_NR,
1899 .label = "GPL1",
1900 },
1901 }, {
1902 .chip = {
1903 .base = S5PC100_GPL2(0),
1904 .ngpio = S5PC100_GPIO_L2_NR,
1905 .label = "GPL2",
1906 },
1907 }, {
1908 .chip = {
1909 .base = S5PC100_GPL3(0),
1910 .ngpio = S5PC100_GPIO_L3_NR,
1911 .label = "GPL3",
1912 },
1913 }, {
1914 .chip = {
1915 .base = S5PC100_GPL4(0),
1916 .ngpio = S5PC100_GPIO_L4_NR,
1917 .label = "GPL4",
1918 },
1919 }, {
1920 .base = (S5P_VA_GPIO + 0xC00),
1921 .irq_base = IRQ_EINT(0),
1922 .chip = {
1923 .base = S5PC100_GPH0(0),
1924 .ngpio = S5PC100_GPIO_H0_NR,
1925 .label = "GPH0",
1926 .to_irq = samsung_gpiolib_to_irq,
1927 },
1928 }, {
1929 .base = (S5P_VA_GPIO + 0xC20),
1930 .irq_base = IRQ_EINT(8),
1931 .chip = {
1932 .base = S5PC100_GPH1(0),
1933 .ngpio = S5PC100_GPIO_H1_NR,
1934 .label = "GPH1",
1935 .to_irq = samsung_gpiolib_to_irq,
1936 },
1937 }, {
1938 .base = (S5P_VA_GPIO + 0xC40),
1939 .irq_base = IRQ_EINT(16),
1940 .chip = {
1941 .base = S5PC100_GPH2(0),
1942 .ngpio = S5PC100_GPIO_H2_NR,
1943 .label = "GPH2",
1944 .to_irq = samsung_gpiolib_to_irq,
1945 },
1946 }, {
1947 .base = (S5P_VA_GPIO + 0xC60),
1948 .irq_base = IRQ_EINT(24),
1949 .chip = {
1950 .base = S5PC100_GPH3(0),
1951 .ngpio = S5PC100_GPIO_H3_NR,
1952 .label = "GPH3",
1953 .to_irq = samsung_gpiolib_to_irq,
1954 },
1955 },
1956#endif
1957};
1958
1959/*
1960 * Followings are the gpio banks in S5PV210/S5PC110
1961 *
1962 * The 'config' member when left to NULL, is initialized to the default
b391f8cf 1963 * structure samsung_gpio_cfgs[3] in the init function below.
1b39d5f2
KK		 1964 *
1965 * The 'base' member is also initialized in the init function below.
1966 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1967 * uses the above macro and depends on the banks being listed in order here.
1968 */
1969
1970static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1971#ifdef CONFIG_CPU_S5PV210
1972 {
1973 .chip = {
1974 .base = S5PV210_GPA0(0),
1975 .ngpio = S5PV210_GPIO_A0_NR,
1976 .label = "GPA0",
1977 },
1978 }, {
1979 .chip = {
1980 .base = S5PV210_GPA1(0),
1981 .ngpio = S5PV210_GPIO_A1_NR,
1982 .label = "GPA1",
1983 },
1984 }, {
1985 .chip = {
1986 .base = S5PV210_GPB(0),
1987 .ngpio = S5PV210_GPIO_B_NR,
1988 .label = "GPB",
1989 },
1990 }, {
1991 .chip = {
1992 .base = S5PV210_GPC0(0),
1993 .ngpio = S5PV210_GPIO_C0_NR,
1994 .label = "GPC0",
1995 },
1996 }, {
1997 .chip = {
1998 .base = S5PV210_GPC1(0),
1999 .ngpio = S5PV210_GPIO_C1_NR,
2000 .label = "GPC1",
2001 },
2002 }, {
2003 .chip = {
2004 .base = S5PV210_GPD0(0),
2005 .ngpio = S5PV210_GPIO_D0_NR,
2006 .label = "GPD0",
2007 },
2008 }, {
2009 .chip = {
2010 .base = S5PV210_GPD1(0),
2011 .ngpio = S5PV210_GPIO_D1_NR,
2012 .label = "GPD1",
2013 },
2014 }, {
2015 .chip = {
2016 .base = S5PV210_GPE0(0),
2017 .ngpio = S5PV210_GPIO_E0_NR,
2018 .label = "GPE0",
2019 },
2020 }, {
2021 .chip = {
2022 .base = S5PV210_GPE1(0),
2023 .ngpio = S5PV210_GPIO_E1_NR,
2024 .label = "GPE1",
2025 },
2026 }, {
2027 .chip = {
2028 .base = S5PV210_GPF0(0),
2029 .ngpio = S5PV210_GPIO_F0_NR,
2030 .label = "GPF0",
2031 },
2032 }, {
2033 .chip = {
2034 .base = S5PV210_GPF1(0),
2035 .ngpio = S5PV210_GPIO_F1_NR,
2036 .label = "GPF1",
2037 },
2038 }, {
2039 .chip = {
2040 .base = S5PV210_GPF2(0),
2041 .ngpio = S5PV210_GPIO_F2_NR,
2042 .label = "GPF2",
2043 },
2044 }, {
2045 .chip = {
2046 .base = S5PV210_GPF3(0),
2047 .ngpio = S5PV210_GPIO_F3_NR,
2048 .label = "GPF3",
2049 },
2050 }, {
2051 .chip = {
2052 .base = S5PV210_GPG0(0),
2053 .ngpio = S5PV210_GPIO_G0_NR,
2054 .label = "GPG0",
2055 },
2056 }, {
2057 .chip = {
2058 .base = S5PV210_GPG1(0),
2059 .ngpio = S5PV210_GPIO_G1_NR,
2060 .label = "GPG1",
2061 },
2062 }, {
2063 .chip = {
2064 .base = S5PV210_GPG2(0),
2065 .ngpio = S5PV210_GPIO_G2_NR,
2066 .label = "GPG2",
2067 },
2068 }, {
2069 .chip = {
2070 .base = S5PV210_GPG3(0),
2071 .ngpio = S5PV210_GPIO_G3_NR,
2072 .label = "GPG3",
2073 },
2074 }, {
2075 .chip = {
2076 .base = S5PV210_GPI(0),
2077 .ngpio = S5PV210_GPIO_I_NR,
2078 .label = "GPI",
2079 },
2080 }, {
2081 .chip = {
2082 .base = S5PV210_GPJ0(0),
2083 .ngpio = S5PV210_GPIO_J0_NR,
2084 .label = "GPJ0",
2085 },
2086 }, {
2087 .chip = {
2088 .base = S5PV210_GPJ1(0),
2089 .ngpio = S5PV210_GPIO_J1_NR,
2090 .label = "GPJ1",
2091 },
2092 }, {
2093 .chip = {
2094 .base = S5PV210_GPJ2(0),
2095 .ngpio = S5PV210_GPIO_J2_NR,
2096 .label = "GPJ2",
2097 },
2098 }, {
2099 .chip = {
2100 .base = S5PV210_GPJ3(0),
2101 .ngpio = S5PV210_GPIO_J3_NR,
2102 .label = "GPJ3",
2103 },
2104 }, {
2105 .chip = {
2106 .base = S5PV210_GPJ4(0),
2107 .ngpio = S5PV210_GPIO_J4_NR,
2108 .label = "GPJ4",
2109 },
2110 }, {
2111 .chip = {
2112 .base = S5PV210_MP01(0),
2113 .ngpio = S5PV210_GPIO_MP01_NR,
2114 .label = "MP01",
2115 },
2116 }, {
2117 .chip = {
2118 .base = S5PV210_MP02(0),
2119 .ngpio = S5PV210_GPIO_MP02_NR,
2120 .label = "MP02",
2121 },
2122 }, {
2123 .chip = {
2124 .base = S5PV210_MP03(0),
2125 .ngpio = S5PV210_GPIO_MP03_NR,
2126 .label = "MP03",
2127 },
2128 }, {
2129 .chip = {
2130 .base = S5PV210_MP04(0),
2131 .ngpio = S5PV210_GPIO_MP04_NR,
2132 .label = "MP04",
2133 },
2134 }, {
2135 .chip = {
2136 .base = S5PV210_MP05(0),
2137 .ngpio = S5PV210_GPIO_MP05_NR,
2138 .label = "MP05",
2139 },
2140 }, {
2141 .base = (S5P_VA_GPIO + 0xC00),
2142 .irq_base = IRQ_EINT(0),
2143 .chip = {
2144 .base = S5PV210_GPH0(0),
2145 .ngpio = S5PV210_GPIO_H0_NR,
2146 .label = "GPH0",
2147 .to_irq = samsung_gpiolib_to_irq,
2148 },
2149 }, {
2150 .base = (S5P_VA_GPIO + 0xC20),
2151 .irq_base = IRQ_EINT(8),
2152 .chip = {
2153 .base = S5PV210_GPH1(0),
2154 .ngpio = S5PV210_GPIO_H1_NR,
2155 .label = "GPH1",
2156 .to_irq = samsung_gpiolib_to_irq,
2157 },
2158 }, {
2159 .base = (S5P_VA_GPIO + 0xC40),
2160 .irq_base = IRQ_EINT(16),
2161 .chip = {
2162 .base = S5PV210_GPH2(0),
2163 .ngpio = S5PV210_GPIO_H2_NR,
2164 .label = "GPH2",
2165 .to_irq = samsung_gpiolib_to_irq,
2166 },
2167 }, {
2168 .base = (S5P_VA_GPIO + 0xC60),
2169 .irq_base = IRQ_EINT(24),
2170 .chip = {
2171 .base = S5PV210_GPH3(0),
2172 .ngpio = S5PV210_GPIO_H3_NR,
2173 .label = "GPH3",
2174 .to_irq = samsung_gpiolib_to_irq,
2175 },
2176 },
2177#endif
2178};
2179
2180/*
a9696d84 2181 * Followings are the gpio banks in EXYNOS SoCs
1b39d5f2
KK		 2182 *
2183 * The 'config' member when left to NULL, is initialized to the default
a9696d84 2184 * structure exynos_gpio_cfg in the init function below.
1b39d5f2
KK		 2185 *
2186 * The 'base' member is also initialized in the init function below.
2187 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2188 * uses the above macro and depends on the banks being listed in order here.
2189 */
2190
1b39d5f2 2191#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2192static struct samsung_gpio_chip exynos4_gpios_1[] = {
1b39d5f2
KK		 2193 {
2194 .chip = {
2195 .base = EXYNOS4_GPA0(0),
2196 .ngpio = EXYNOS4_GPIO_A0_NR,
2197 .label = "GPA0",
2198 },
2199 }, {
2200 .chip = {
2201 .base = EXYNOS4_GPA1(0),
2202 .ngpio = EXYNOS4_GPIO_A1_NR,
2203 .label = "GPA1",
2204 },
2205 }, {
2206 .chip = {
2207 .base = EXYNOS4_GPB(0),
2208 .ngpio = EXYNOS4_GPIO_B_NR,
2209 .label = "GPB",
2210 },
2211 }, {
2212 .chip = {
2213 .base = EXYNOS4_GPC0(0),
2214 .ngpio = EXYNOS4_GPIO_C0_NR,
2215 .label = "GPC0",
2216 },
2217 }, {
2218 .chip = {
2219 .base = EXYNOS4_GPC1(0),
2220 .ngpio = EXYNOS4_GPIO_C1_NR,
2221 .label = "GPC1",
2222 },
2223 }, {
2224 .chip = {
2225 .base = EXYNOS4_GPD0(0),
2226 .ngpio = EXYNOS4_GPIO_D0_NR,
2227 .label = "GPD0",
2228 },
2229 }, {
2230 .chip = {
2231 .base = EXYNOS4_GPD1(0),
2232 .ngpio = EXYNOS4_GPIO_D1_NR,
2233 .label = "GPD1",
2234 },
2235 }, {
2236 .chip = {
2237 .base = EXYNOS4_GPE0(0),
2238 .ngpio = EXYNOS4_GPIO_E0_NR,
2239 .label = "GPE0",
2240 },
2241 }, {
2242 .chip = {
2243 .base = EXYNOS4_GPE1(0),
2244 .ngpio = EXYNOS4_GPIO_E1_NR,
2245 .label = "GPE1",
2246 },
2247 }, {
2248 .chip = {
2249 .base = EXYNOS4_GPE2(0),
2250 .ngpio = EXYNOS4_GPIO_E2_NR,
2251 .label = "GPE2",
2252 },
2253 }, {
2254 .chip = {
2255 .base = EXYNOS4_GPE3(0),
2256 .ngpio = EXYNOS4_GPIO_E3_NR,
2257 .label = "GPE3",
2258 },
2259 }, {
2260 .chip = {
2261 .base = EXYNOS4_GPE4(0),
2262 .ngpio = EXYNOS4_GPIO_E4_NR,
2263 .label = "GPE4",
2264 },
2265 }, {
2266 .chip = {
2267 .base = EXYNOS4_GPF0(0),
2268 .ngpio = EXYNOS4_GPIO_F0_NR,
2269 .label = "GPF0",
2270 },
2271 }, {
2272 .chip = {
2273 .base = EXYNOS4_GPF1(0),
2274 .ngpio = EXYNOS4_GPIO_F1_NR,
2275 .label = "GPF1",
2276 },
2277 }, {
2278 .chip = {
2279 .base = EXYNOS4_GPF2(0),
2280 .ngpio = EXYNOS4_GPIO_F2_NR,
2281 .label = "GPF2",
2282 },
2283 }, {
2284 .chip = {
2285 .base = EXYNOS4_GPF3(0),
2286 .ngpio = EXYNOS4_GPIO_F3_NR,
2287 .label = "GPF3",
2288 },
2289 },
1b39d5f2 2290};
2760f7ad 2291#endif
1b39d5f2 2292
1b39d5f2 2293#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2294static struct samsung_gpio_chip exynos4_gpios_2[] = {
1b39d5f2
KK		 2295 {
2296 .chip = {
2297 .base = EXYNOS4_GPJ0(0),
2298 .ngpio = EXYNOS4_GPIO_J0_NR,
2299 .label = "GPJ0",
2300 },
2301 }, {
2302 .chip = {
2303 .base = EXYNOS4_GPJ1(0),
2304 .ngpio = EXYNOS4_GPIO_J1_NR,
2305 .label = "GPJ1",
2306 },
2307 }, {
2308 .chip = {
2309 .base = EXYNOS4_GPK0(0),
2310 .ngpio = EXYNOS4_GPIO_K0_NR,
2311 .label = "GPK0",
2312 },
2313 }, {
2314 .chip = {
2315 .base = EXYNOS4_GPK1(0),
2316 .ngpio = EXYNOS4_GPIO_K1_NR,
2317 .label = "GPK1",
2318 },
2319 }, {
2320 .chip = {
2321 .base = EXYNOS4_GPK2(0),
2322 .ngpio = EXYNOS4_GPIO_K2_NR,
2323 .label = "GPK2",
2324 },
2325 }, {
2326 .chip = {
2327 .base = EXYNOS4_GPK3(0),
2328 .ngpio = EXYNOS4_GPIO_K3_NR,
2329 .label = "GPK3",
2330 },
2331 }, {
2332 .chip = {
2333 .base = EXYNOS4_GPL0(0),
2334 .ngpio = EXYNOS4_GPIO_L0_NR,
2335 .label = "GPL0",
2336 },
2337 }, {
2338 .chip = {
2339 .base = EXYNOS4_GPL1(0),
2340 .ngpio = EXYNOS4_GPIO_L1_NR,
2341 .label = "GPL1",
2342 },
2343 }, {
2344 .chip = {
2345 .base = EXYNOS4_GPL2(0),
2346 .ngpio = EXYNOS4_GPIO_L2_NR,
2347 .label = "GPL2",
2348 },
2349 }, {
b82cee24 2350 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2351 .chip = {
2352 .base = EXYNOS4_GPY0(0),
2353 .ngpio = EXYNOS4_GPIO_Y0_NR,
2354 .label = "GPY0",
2355 },
2356 }, {
b82cee24 2357 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2358 .chip = {
2359 .base = EXYNOS4_GPY1(0),
2360 .ngpio = EXYNOS4_GPIO_Y1_NR,
2361 .label = "GPY1",
2362 },
2363 }, {
b82cee24 2364 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2365 .chip = {
2366 .base = EXYNOS4_GPY2(0),
2367 .ngpio = EXYNOS4_GPIO_Y2_NR,
2368 .label = "GPY2",
2369 },
2370 }, {
b82cee24 2371 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2372 .chip = {
2373 .base = EXYNOS4_GPY3(0),
2374 .ngpio = EXYNOS4_GPIO_Y3_NR,
2375 .label = "GPY3",
2376 },
2377 }, {
b82cee24 2378 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2379 .chip = {
2380 .base = EXYNOS4_GPY4(0),
2381 .ngpio = EXYNOS4_GPIO_Y4_NR,
2382 .label = "GPY4",
2383 },
2384 }, {
b82cee24 2385 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2386 .chip = {
2387 .base = EXYNOS4_GPY5(0),
2388 .ngpio = EXYNOS4_GPIO_Y5_NR,
2389 .label = "GPY5",
2390 },
2391 }, {
b82cee24 2392 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2393 .chip = {
2394 .base = EXYNOS4_GPY6(0),
2395 .ngpio = EXYNOS4_GPIO_Y6_NR,
2396 .label = "GPY6",
2397 },
2398 }, {
b82cee24 2399 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2400 .irq_base = IRQ_EINT(0),
2401 .chip = {
2402 .base = EXYNOS4_GPX0(0),
2403 .ngpio = EXYNOS4_GPIO_X0_NR,
2404 .label = "GPX0",
2405 .to_irq = samsung_gpiolib_to_irq,
2406 },
2407 }, {
b82cee24 2408 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2409 .irq_base = IRQ_EINT(8),
2410 .chip = {
2411 .base = EXYNOS4_GPX1(0),
2412 .ngpio = EXYNOS4_GPIO_X1_NR,
2413 .label = "GPX1",
2414 .to_irq = samsung_gpiolib_to_irq,
2415 },
2416 }, {
b82cee24 2417 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2418 .irq_base = IRQ_EINT(16),
2419 .chip = {
2420 .base = EXYNOS4_GPX2(0),
2421 .ngpio = EXYNOS4_GPIO_X2_NR,
2422 .label = "GPX2",
2423 .to_irq = samsung_gpiolib_to_irq,
2424 },
2425 }, {
b82cee24 2426 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2427 .irq_base = IRQ_EINT(24),
2428 .chip = {
2429 .base = EXYNOS4_GPX3(0),
2430 .ngpio = EXYNOS4_GPIO_X3_NR,
2431 .label = "GPX3",
2432 .to_irq = samsung_gpiolib_to_irq,
2433 },
2434 },
1b39d5f2 2435};
2760f7ad 2436#endif
1b39d5f2 2437
1b39d5f2 2438#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2439static struct samsung_gpio_chip exynos4_gpios_3[] = {
1b39d5f2
KK		 2440 {
2441 .chip = {
2442 .base = EXYNOS4_GPZ(0),
2443 .ngpio = EXYNOS4_GPIO_Z_NR,
2444 .label = "GPZ",
2445 },
2446 },
1b39d5f2 2447};
2760f7ad 2448#endif
1b39d5f2 2449
a9696d84 2450#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2451static struct samsung_gpio_chip exynos5_gpios_1[] = {
a9696d84
SP		 2452 {
2453 .chip = {
2454 .base = EXYNOS5_GPA0(0),
2455 .ngpio = EXYNOS5_GPIO_A0_NR,
2456 .label = "GPA0",
2457 },
2458 }, {
2459 .chip = {
2460 .base = EXYNOS5_GPA1(0),
2461 .ngpio = EXYNOS5_GPIO_A1_NR,
2462 .label = "GPA1",
2463 },
2464 }, {
2465 .chip = {
2466 .base = EXYNOS5_GPA2(0),
2467 .ngpio = EXYNOS5_GPIO_A2_NR,
2468 .label = "GPA2",
2469 },
2470 }, {
2471 .chip = {
2472 .base = EXYNOS5_GPB0(0),
2473 .ngpio = EXYNOS5_GPIO_B0_NR,
2474 .label = "GPB0",
2475 },
2476 }, {
2477 .chip = {
2478 .base = EXYNOS5_GPB1(0),
2479 .ngpio = EXYNOS5_GPIO_B1_NR,
2480 .label = "GPB1",
2481 },
2482 }, {
2483 .chip = {
2484 .base = EXYNOS5_GPB2(0),
2485 .ngpio = EXYNOS5_GPIO_B2_NR,
2486 .label = "GPB2",
2487 },
2488 }, {
2489 .chip = {
2490 .base = EXYNOS5_GPB3(0),
2491 .ngpio = EXYNOS5_GPIO_B3_NR,
2492 .label = "GPB3",
2493 },
2494 }, {
2495 .chip = {
2496 .base = EXYNOS5_GPC0(0),
2497 .ngpio = EXYNOS5_GPIO_C0_NR,
2498 .label = "GPC0",
2499 },
2500 }, {
2501 .chip = {
2502 .base = EXYNOS5_GPC1(0),
2503 .ngpio = EXYNOS5_GPIO_C1_NR,
2504 .label = "GPC1",
2505 },
2506 }, {
2507 .chip = {
2508 .base = EXYNOS5_GPC2(0),
2509 .ngpio = EXYNOS5_GPIO_C2_NR,
2510 .label = "GPC2",
2511 },
2512 }, {
2513 .chip = {
2514 .base = EXYNOS5_GPC3(0),
2515 .ngpio = EXYNOS5_GPIO_C3_NR,
2516 .label = "GPC3",
2517 },
2518 }, {
2519 .chip = {
2520 .base = EXYNOS5_GPD0(0),
2521 .ngpio = EXYNOS5_GPIO_D0_NR,
2522 .label = "GPD0",
2523 },
2524 }, {
2525 .chip = {
2526 .base = EXYNOS5_GPD1(0),
2527 .ngpio = EXYNOS5_GPIO_D1_NR,
2528 .label = "GPD1",
2529 },
2530 }, {
2531 .chip = {
2532 .base = EXYNOS5_GPY0(0),
2533 .ngpio = EXYNOS5_GPIO_Y0_NR,
2534 .label = "GPY0",
2535 },
2536 }, {
2537 .chip = {
2538 .base = EXYNOS5_GPY1(0),
2539 .ngpio = EXYNOS5_GPIO_Y1_NR,
2540 .label = "GPY1",
2541 },
2542 }, {
2543 .chip = {
2544 .base = EXYNOS5_GPY2(0),
2545 .ngpio = EXYNOS5_GPIO_Y2_NR,
2546 .label = "GPY2",
2547 },
2548 }, {
2549 .chip = {
2550 .base = EXYNOS5_GPY3(0),
2551 .ngpio = EXYNOS5_GPIO_Y3_NR,
2552 .label = "GPY3",
2553 },
2554 }, {
2555 .chip = {
2556 .base = EXYNOS5_GPY4(0),
2557 .ngpio = EXYNOS5_GPIO_Y4_NR,
2558 .label = "GPY4",
2559 },
2560 }, {
2561 .chip = {
2562 .base = EXYNOS5_GPY5(0),
2563 .ngpio = EXYNOS5_GPIO_Y5_NR,
2564 .label = "GPY5",
2565 },
2566 }, {
2567 .chip = {
2568 .base = EXYNOS5_GPY6(0),
2569 .ngpio = EXYNOS5_GPIO_Y6_NR,
2570 .label = "GPY6",
2571 },
f7093f3e
SP		 2572 }, {
2573 .chip = {
2574 .base = EXYNOS5_GPC4(0),
2575 .ngpio = EXYNOS5_GPIO_C4_NR,
2576 .label = "GPC4",
2577 },
a9696d84
SP		 2578 }, {
2579 .config = &samsung_gpio_cfgs[9],
2580 .irq_base = IRQ_EINT(0),
2581 .chip = {
2582 .base = EXYNOS5_GPX0(0),
2583 .ngpio = EXYNOS5_GPIO_X0_NR,
2584 .label = "GPX0",
2585 .to_irq = samsung_gpiolib_to_irq,
2586 },
2587 }, {
2588 .config = &samsung_gpio_cfgs[9],
2589 .irq_base = IRQ_EINT(8),
2590 .chip = {
2591 .base = EXYNOS5_GPX1(0),
2592 .ngpio = EXYNOS5_GPIO_X1_NR,
2593 .label = "GPX1",
2594 .to_irq = samsung_gpiolib_to_irq,
2595 },
2596 }, {
2597 .config = &samsung_gpio_cfgs[9],
2598 .irq_base = IRQ_EINT(16),
2599 .chip = {
2600 .base = EXYNOS5_GPX2(0),
2601 .ngpio = EXYNOS5_GPIO_X2_NR,
2602 .label = "GPX2",
2603 .to_irq = samsung_gpiolib_to_irq,
2604 },
2605 }, {
2606 .config = &samsung_gpio_cfgs[9],
2607 .irq_base = IRQ_EINT(24),
2608 .chip = {
2609 .base = EXYNOS5_GPX3(0),
2610 .ngpio = EXYNOS5_GPIO_X3_NR,
2611 .label = "GPX3",
2612 .to_irq = samsung_gpiolib_to_irq,
2613 },
2614 },
a9696d84 2615};
9a5c7d6e 2616#endif
a9696d84 2617
a9696d84 2618#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2619static struct samsung_gpio_chip exynos5_gpios_2[] = {
a9696d84
SP		 2620 {
2621 .chip = {
2622 .base = EXYNOS5_GPE0(0),
2623 .ngpio = EXYNOS5_GPIO_E0_NR,
2624 .label = "GPE0",
2625 },
2626 }, {
2627 .chip = {
2628 .base = EXYNOS5_GPE1(0),
2629 .ngpio = EXYNOS5_GPIO_E1_NR,
2630 .label = "GPE1",
2631 },
2632 }, {
2633 .chip = {
2634 .base = EXYNOS5_GPF0(0),
2635 .ngpio = EXYNOS5_GPIO_F0_NR,
2636 .label = "GPF0",
2637 },
2638 }, {
2639 .chip = {
2640 .base = EXYNOS5_GPF1(0),
2641 .ngpio = EXYNOS5_GPIO_F1_NR,
2642 .label = "GPF1",
2643 },
2644 }, {
2645 .chip = {
2646 .base = EXYNOS5_GPG0(0),
2647 .ngpio = EXYNOS5_GPIO_G0_NR,
2648 .label = "GPG0",
2649 },
2650 }, {
2651 .chip = {
2652 .base = EXYNOS5_GPG1(0),
2653 .ngpio = EXYNOS5_GPIO_G1_NR,
2654 .label = "GPG1",
2655 },
2656 }, {
2657 .chip = {
2658 .base = EXYNOS5_GPG2(0),
2659 .ngpio = EXYNOS5_GPIO_G2_NR,
2660 .label = "GPG2",
2661 },
2662 }, {
2663 .chip = {
2664 .base = EXYNOS5_GPH0(0),
2665 .ngpio = EXYNOS5_GPIO_H0_NR,
2666 .label = "GPH0",
2667 },
2668 }, {
2669 .chip = {
2670 .base = EXYNOS5_GPH1(0),
2671 .ngpio = EXYNOS5_GPIO_H1_NR,
2672 .label = "GPH1",
2673
2674 },
2675 },
a9696d84 2676};
9a5c7d6e 2677#endif
a9696d84 2678
a9696d84 2679#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2680static struct samsung_gpio_chip exynos5_gpios_3[] = {
a9696d84
SP		 2681 {
2682 .chip = {
2683 .base = EXYNOS5_GPV0(0),
2684 .ngpio = EXYNOS5_GPIO_V0_NR,
2685 .label = "GPV0",
2686 },
2687 }, {
2688 .chip = {
2689 .base = EXYNOS5_GPV1(0),
2690 .ngpio = EXYNOS5_GPIO_V1_NR,
2691 .label = "GPV1",
2692 },
2693 }, {
2694 .chip = {
2695 .base = EXYNOS5_GPV2(0),
2696 .ngpio = EXYNOS5_GPIO_V2_NR,
2697 .label = "GPV2",
2698 },
2699 }, {
2700 .chip = {
2701 .base = EXYNOS5_GPV3(0),
2702 .ngpio = EXYNOS5_GPIO_V3_NR,
2703 .label = "GPV3",
2704 },
2705 }, {
2706 .chip = {
2707 .base = EXYNOS5_GPV4(0),
2708 .ngpio = EXYNOS5_GPIO_V4_NR,
2709 .label = "GPV4",
2710 },
2711 },
a9696d84 2712};
9a5c7d6e 2713#endif
a9696d84 2714
a9696d84 2715#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2716static struct samsung_gpio_chip exynos5_gpios_4[] = {
a9696d84
SP		 2717 {
2718 .chip = {
2719 .base = EXYNOS5_GPZ(0),
2720 .ngpio = EXYNOS5_GPIO_Z_NR,
2721 .label = "GPZ",
2722 },
2723 },
a9696d84 2724};
9a5c7d6e 2725#endif
a9696d84
SP		 2726
2727
2728#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2729static int exynos_gpio_xlate(struct gpio_chip *gc,
876cf5e7 2730 const struct of_phandle_args *gpiospec, u32 *flags)
659d73ad 2731{
876cf5e7 2732 unsigned int pin;
659d73ad
TA		 2733
2734 if (WARN_ON(gc->of_gpio_n_cells < 4))
2735 return -EINVAL;
2736
876cf5e7 2737 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
659d73ad
TA		 2738 return -EINVAL;
2739
876cf5e7
TA		 2740 if (gpiospec->args[0] > gc->ngpio)
2741 return -EINVAL;
2742
2743 pin = gc->base + gpiospec->args[0];
2744
2745 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
659d73ad 2746 pr_warn("gpio_xlate: failed to set pin function\n");
f447ed8b 2747 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
659d73ad 2748 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
876cf5e7 2749 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
659d73ad
TA		 2750 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2751
f447ed8b
OJ		 2752 if (flags)
2753 *flags = gpiospec->args[2] >> 16;
2754
876cf5e7 2755 return gpiospec->args[0];
659d73ad
TA		 2756}
2757
a9696d84 2758static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
659d73ad
TA		 2759 { .compatible = "samsung,exynos4-gpio", },
2760 {}
2761};
2762
a9696d84
SP		 2763static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2764 u64 base, u64 offset)
659d73ad
TA		 2765{
2766 struct gpio_chip *gc = &chip->chip;
2767 u64 address;
2768
2769 if (!of_have_populated_dt())
2770 return;
2771
2772 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2773 gc->of_node = of_find_matching_node_by_address(NULL,
a9696d84 2774 exynos_gpio_dt_match, address);
659d73ad
TA		 2775 if (!gc->of_node) {
2776 pr_info("gpio: device tree node not found for gpio controller"
2777 " with base address %08llx\n", address);
2778 return;
2779 }
2780 gc->of_gpio_n_cells = 4;
a9696d84 2781 gc->of_xlate = exynos_gpio_xlate;
659d73ad 2782}
a9696d84
SP		 2783#elif defined(CONFIG_ARCH_EXYNOS)
2784static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2785 u64 base, u64 offset)
659d73ad
TA		 2786{
2787 return;
2788}
a9696d84 2789#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
659d73ad 2790
fd454997
OJ		 2791static __init void exynos4_gpiolib_init(void)
2792{
2793#ifdef CONFIG_CPU_EXYNOS4210
2794 struct samsung_gpio_chip *chip;
2795 int i, nr_chips;
2796 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2797 int group = 0;
2798 void __iomem *gpx_base;
2799
2800 /* gpio part1 */
2801 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2802 if (gpio_base1 == NULL) {
2803 pr_err("unable to ioremap for gpio_base1\n");
2804 goto err_ioremap1;
2805 }
2806
2807 chip = exynos4_gpios_1;
2808 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2809
2810 for (i = 0; i < nr_chips; i++, chip++) {
2811 if (!chip->config) {
2812 chip->config = &exynos_gpio_cfg;
2813 chip->group = group++;
2814 }
2815 exynos_gpiolib_attach_ofnode(chip,
2816 EXYNOS4_PA_GPIO1, i * 0x20);
2817 }
2818 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2819 nr_chips, gpio_base1);
2820
2821 /* gpio part2 */
2822 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2823 if (gpio_base2 == NULL) {
2824 pr_err("unable to ioremap for gpio_base2\n");
2825 goto err_ioremap2;
2826 }
2827
2828 /* need to set base address for gpx */
2829 chip = &exynos4_gpios_2[16];
2830 gpx_base = gpio_base2 + 0xC00;
2831 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2832 chip->base = gpx_base;
2833
2834 chip = exynos4_gpios_2;
2835 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2836
2837 for (i = 0; i < nr_chips; i++, chip++) {
2838 if (!chip->config) {
2839 chip->config = &exynos_gpio_cfg;
2840 chip->group = group++;
2841 }
2842 exynos_gpiolib_attach_ofnode(chip,
2843 EXYNOS4_PA_GPIO2, i * 0x20);
2844 }
2845 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2846 nr_chips, gpio_base2);
2847
2848 /* gpio part3 */
2849 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2850 if (gpio_base3 == NULL) {
2851 pr_err("unable to ioremap for gpio_base3\n");
2852 goto err_ioremap3;
2853 }
2854
2855 chip = exynos4_gpios_3;
2856 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2857
2858 for (i = 0; i < nr_chips; i++, chip++) {
2859 if (!chip->config) {
2860 chip->config = &exynos_gpio_cfg;
2861 chip->group = group++;
2862 }
2863 exynos_gpiolib_attach_ofnode(chip,
2864 EXYNOS4_PA_GPIO3, i * 0x20);
2865 }
2866 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2867 nr_chips, gpio_base3);
2868
2869#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2870 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2871 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2872#endif
2873
2874 return;
2875
2876err_ioremap3:
2877 iounmap(gpio_base2);
2878err_ioremap2:
2879 iounmap(gpio_base1);
2880err_ioremap1:
2881 return;
2882#endif /* CONFIG_CPU_EXYNOS4210 */
2883}
2884
2885static __init void exynos5_gpiolib_init(void)
2886{
2887#ifdef CONFIG_SOC_EXYNOS5250
2888 struct samsung_gpio_chip *chip;
2889 int i, nr_chips;
2890 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2891 int group = 0;
2892 void __iomem *gpx_base;
2893
2894 /* gpio part1 */
2895 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2896 if (gpio_base1 == NULL) {
2897 pr_err("unable to ioremap for gpio_base1\n");
2898 goto err_ioremap1;
2899 }
2900
30b84288 2901 /* need to set base address for gpc4 */
f7093f3e 2902 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
30b84288 2903
fd454997 2904 /* need to set base address for gpx */
30b84288 2905 chip = &exynos5_gpios_1[21];
fd454997
OJ		 2906 gpx_base = gpio_base1 + 0xC00;
2907 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2908 chip->base = gpx_base;
2909
2910 chip = exynos5_gpios_1;
2911 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2912
2913 for (i = 0; i < nr_chips; i++, chip++) {
2914 if (!chip->config) {
2915 chip->config = &exynos_gpio_cfg;
2916 chip->group = group++;
2917 }
2918 exynos_gpiolib_attach_ofnode(chip,
2919 EXYNOS5_PA_GPIO1, i * 0x20);
2920 }
2921 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2922 nr_chips, gpio_base1);
2923
2924 /* gpio part2 */
2925 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2926 if (gpio_base2 == NULL) {
2927 pr_err("unable to ioremap for gpio_base2\n");
2928 goto err_ioremap2;
2929 }
2930
2931 chip = exynos5_gpios_2;
2932 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2933
2934 for (i = 0; i < nr_chips; i++, chip++) {
2935 if (!chip->config) {
2936 chip->config = &exynos_gpio_cfg;
2937 chip->group = group++;
2938 }
2939 exynos_gpiolib_attach_ofnode(chip,
2940 EXYNOS5_PA_GPIO2, i * 0x20);
2941 }
2942 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2943 nr_chips, gpio_base2);
2944
2945 /* gpio part3 */
2946 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2947 if (gpio_base3 == NULL) {
2948 pr_err("unable to ioremap for gpio_base3\n");
2949 goto err_ioremap3;
2950 }
2951
2952 /* need to set base address for gpv */
2953 exynos5_gpios_3[0].base = gpio_base3;
2954 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2955 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2956 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2957 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2958
2959 chip = exynos5_gpios_3;
2960 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2961
2962 for (i = 0; i < nr_chips; i++, chip++) {
2963 if (!chip->config) {
2964 chip->config = &exynos_gpio_cfg;
2965 chip->group = group++;
2966 }
2967 exynos_gpiolib_attach_ofnode(chip,
2968 EXYNOS5_PA_GPIO3, i * 0x20);
2969 }
2970 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2971 nr_chips, gpio_base3);
2972
2973 /* gpio part4 */
2974 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2975 if (gpio_base4 == NULL) {
2976 pr_err("unable to ioremap for gpio_base4\n");
2977 goto err_ioremap4;
2978 }
2979
2980 chip = exynos5_gpios_4;
2981 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2982
2983 for (i = 0; i < nr_chips; i++, chip++) {
2984 if (!chip->config) {
2985 chip->config = &exynos_gpio_cfg;
2986 chip->group = group++;
2987 }
2988 exynos_gpiolib_attach_ofnode(chip,
2989 EXYNOS5_PA_GPIO4, i * 0x20);
2990 }
2991 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2992 nr_chips, gpio_base4);
2993 return;
2994
2995err_ioremap4:
2996 iounmap(gpio_base3);
2997err_ioremap3:
2998 iounmap(gpio_base2);
2999err_ioremap2:
3000 iounmap(gpio_base1);
3001err_ioremap1:
3002 return;
3003
3004#endif /* CONFIG_SOC_EXYNOS5250 */
3005}
3006
1b39d5f2
KK		 3007/* TODO: cleanup soc_is_* */
3008static __init int samsung_gpiolib_init(void)
3009{
3010 struct samsung_gpio_chip *chip;
3011 int i, nr_chips;
3012 int group = 0;
3013
3014 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3015
3016 if (soc_is_s3c24xx()) {
3017 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3018 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3019 } else if (soc_is_s3c64xx()) {
3020 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3021 ARRAY_SIZE(s3c64xx_gpios_2bit),
3022 S3C64XX_VA_GPIO + 0xE0, 0x20);
3023 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3024 ARRAY_SIZE(s3c64xx_gpios_4bit),
3025 S3C64XX_VA_GPIO);
3026 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3027 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3028 } else if (soc_is_s5p6440()) {
3029 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3030 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3031 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3032 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3033 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3034 ARRAY_SIZE(s5p6440_gpios_4bit2));
3035 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3036 ARRAY_SIZE(s5p6440_gpios_rbank));
3037 } else if (soc_is_s5p6450()) {
3038 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3039 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3040 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3041 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3042 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3043 ARRAY_SIZE(s5p6450_gpios_4bit2));
3044 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3045 ARRAY_SIZE(s5p6450_gpios_rbank));
3046 } else if (soc_is_s5pc100()) {
3047 group = 0;
3048 chip = s5pc100_gpios_4bit;
3049 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3050
3051 for (i = 0; i < nr_chips; i++, chip++) {
3052 if (!chip->config) {
b391f8cf 3053 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3054 chip->group = group++;
3055 }
3056 }
3057 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3058#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3059 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3060#endif
3061 } else if (soc_is_s5pv210()) {
3062 group = 0;
3063 chip = s5pv210_gpios_4bit;
3064 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3065
3066 for (i = 0; i < nr_chips; i++, chip++) {
3067 if (!chip->config) {
b391f8cf 3068 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3069 chip->group = group++;
3070 }
3071 }
3072 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3073#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3074 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3075#endif
3076 } else if (soc_is_exynos4210()) {
fd454997 3077 exynos4_gpiolib_init();
a9696d84 3078 } else if (soc_is_exynos5250()) {
fd454997 3079 exynos5_gpiolib_init();
fbe92fcc
MB		 3080 } else {
3081 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3082 return -ENODEV;
1b39d5f2
KK		 3083 }
3084
3085 return 0;
3086}
3087core_initcall(samsung_gpiolib_init);
3088
3089int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3090{
3091 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3092 unsigned long flags;
3093 int offset;
3094 int ret;
3095
3096 if (!chip)
3097 return -EINVAL;
3098
3099 offset = pin - chip->chip.base;
3100
3101 samsung_gpio_lock(chip, flags);
3102 ret = samsung_gpio_do_setcfg(chip, offset, config);
3103 samsung_gpio_unlock(chip, flags);
3104
3105 return ret;
3106}
3107EXPORT_SYMBOL(s3c_gpio_cfgpin);
3108
3109int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3110 unsigned int cfg)
3111{
3112 int ret;
3113
3114 for (; nr > 0; nr--, start++) {
3115 ret = s3c_gpio_cfgpin(start, cfg);
3116 if (ret != 0)
3117 return ret;
3118 }
3119
3120 return 0;
3121}
3122EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3123
3124int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3125 unsigned int cfg, samsung_gpio_pull_t pull)
3126{
3127 int ret;
3128
3129 for (; nr > 0; nr--, start++) {
3130 s3c_gpio_setpull(start, pull);
3131 ret = s3c_gpio_cfgpin(start, cfg);
3132 if (ret != 0)
3133 return ret;
3134 }
3135
3136 return 0;
3137}
3138EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3139
3140unsigned s3c_gpio_getcfg(unsigned int pin)
3141{
3142 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3143 unsigned long flags;
3144 unsigned ret = 0;
3145 int offset;
3146
3147 if (chip) {
3148 offset = pin - chip->chip.base;
3149
3150 samsung_gpio_lock(chip, flags);
3151 ret = samsung_gpio_do_getcfg(chip, offset);
3152 samsung_gpio_unlock(chip, flags);
3153 }
3154
3155 return ret;
3156}
3157EXPORT_SYMBOL(s3c_gpio_getcfg);
3158
3159int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3160{
3161 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3162 unsigned long flags;
3163 int offset, ret;
3164
3165 if (!chip)
3166 return -EINVAL;
3167
3168 offset = pin - chip->chip.base;
3169
3170 samsung_gpio_lock(chip, flags);
3171 ret = samsung_gpio_do_setpull(chip, offset, pull);
3172 samsung_gpio_unlock(chip, flags);
3173
3174 return ret;
3175}
3176EXPORT_SYMBOL(s3c_gpio_setpull);
3177
3178samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3179{
3180 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3181 unsigned long flags;
3182 int offset;
3183 u32 pup = 0;
3184
3185 if (chip) {
3186 offset = pin - chip->chip.base;
3187
3188 samsung_gpio_lock(chip, flags);
3189 pup = samsung_gpio_do_getpull(chip, offset);
3190 samsung_gpio_unlock(chip, flags);
3191 }
3192
3193 return (__force samsung_gpio_pull_t)pup;
3194}
3195EXPORT_SYMBOL(s3c_gpio_getpull);
3196
1b39d5f2
KK		 3197#ifdef CONFIG_S5P_GPIO_DRVSTR
3198s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3199{
3200 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3201 unsigned int off;
3202 void __iomem *reg;
3203 int shift;
3204 u32 drvstr;
3205
3206 if (!chip)
3207 return -EINVAL;
3208
3209 off = pin - chip->chip.base;
3210 shift = off * 2;
3211 reg = chip->base + 0x0C;
3212
3213 drvstr = __raw_readl(reg);
3214 drvstr = drvstr >> shift;
3215 drvstr &= 0x3;
3216
3217 return (__force s5p_gpio_drvstr_t)drvstr;
3218}
3219EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3220
3221int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3222{
3223 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3224 unsigned int off;
3225 void __iomem *reg;
3226 int shift;
3227 u32 tmp;
3228
3229 if (!chip)
3230 return -EINVAL;
3231
3232 off = pin - chip->chip.base;
3233 shift = off * 2;
3234 reg = chip->base + 0x0C;
3235
3236 tmp = __raw_readl(reg);
3237 tmp &= ~(0x3 << shift);
3238 tmp |= drvstr << shift;
3239
3240 __raw_writel(tmp, reg);
3241
3242 return 0;
3243}
3244EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3245#endif /* CONFIG_S5P_GPIO_DRVSTR */
3246
3247#ifdef CONFIG_PLAT_S3C24XX
3248unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3249{
3250 unsigned long flags;
3251 unsigned long misccr;
3252
3253 local_irq_save(flags);
3254 misccr = __raw_readl(S3C24XX_MISCCR);
3255 misccr &= ~clear;
3256 misccr ^= change;
3257 __raw_writel(misccr, S3C24XX_MISCCR);
3258 local_irq_restore(flags);
3259
3260 return misccr;
3261}
3262EXPORT_SYMBOL(s3c2410_modify_misccr);
3263#endif
Linux kernel - Deliverables
This page took 0.19606 seconds and 5 git commands to generate.