[deliverable/linux.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

#define CACHE_NR_REGS	3
#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;

	int irq_base;
	unsigned norequest_mask;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct stmpe_gpio, chip);
}

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);

	return stmpe_gpio->irq_base + offset;
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.to_irq			= stmpe_gpio_to_irq,
	.request		= stmpe_gpio_request,
	.can_sleep		= 1,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 doesn't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801)
		return 0;

	if (type == IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[] = {
		[REG_RE]	= STMPE_IDX_GPRER_LSB,
		[REG_FE]	= STMPE_IDX_GPFER_LSB,
		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 doesn't have RE and FE registers */
		if ((stmpe->partnum == STMPE801) &&
				(i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;

			handle_nested_irq(stmpe_gpio->irq_base + line);
			stat &= ~(1 << bit);
		}

		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);

		/* Edge detect register is not present on 801 */
		if (stmpe->partnum != STMPE801)
			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
					+ i, status[i]);
	}

	return IRQ_HANDLED;
}

static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
{
	int base = stmpe_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
		irq_set_chip_data(irq, stmpe_gpio);
		irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
					 handle_simple_irq);
		irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(irq, IRQF_VALID);
#else
		irq_set_noprobe(irq);
#endif
	}

	return 0;
}

static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
{
	int base = stmpe_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
#ifdef CONFIG_ARM
		set_irq_flags(irq, 0);
#endif
		irq_set_chip_and_handler(irq, NULL, NULL);
		irq_set_chip_data(irq, NULL);
	}
}

static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio_platform_data *pdata;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq = 0;

	pdata = stmpe->pdata->gpio;

	irq = platform_get_irq(pdev, 0);

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.dev = &pdev->dev;
	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;

	if (pdata)
		stmpe_gpio->norequest_mask = pdata->norequest_mask;
	else if (np)
		of_property_read_u32(np, "st,norequest-mask",
				&stmpe_gpio->norequest_mask);

	if (irq >= 0)
		stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	else
		dev_info(&pdev->dev,
			"device configured in no-irq mode; "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	if (irq >= 0) {
		ret = stmpe_gpio_irq_init(stmpe_gpio);
		if (ret)
			goto out_disable;

		ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
				IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_removeirq;
		}
	}

	ret = gpiochip_add(&stmpe_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata && pdata->setup)
		pdata->setup(stmpe, stmpe_gpio->chip.base);

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_freeirq:
	if (irq >= 0)
		free_irq(irq, stmpe_gpio);
out_removeirq:
	if (irq >= 0)
		stmpe_gpio_irq_remove(stmpe_gpio);
out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
{
	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata && pdata->remove)
		pdata->remove(stmpe, stmpe_gpio->chip.base);

	ret = gpiochip_remove(&stmpe_gpio->chip);
	if (ret < 0) {
		dev_err(stmpe_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);

	if (irq >= 0) {
		free_irq(irq, stmpe_gpio);
		stmpe_gpio_irq_remove(stmpe_gpio);
	}
	platform_set_drvdata(pdev, NULL);
	kfree(stmpe_gpio);

	return 0;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver.name	= "stmpe-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= stmpe_gpio_probe,
	.remove		= __devexit_p(stmpe_gpio_remove),
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);

static void __exit stmpe_gpio_exit(void)
{
	platform_driver_unregister(&stmpe_gpio_driver);
}
module_exit(stmpe_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("STMPExxxx GPIO driver");
MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
	12	#include <linux/gpio.h>
	13	#include <linux/irq.h>
	14	#include <linux/interrupt.h>
86605cfe	15	#include <linux/of.h>
03f822f5 RV	16	#include <linux/mfd/stmpe.h>
	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
	22	enum { REG_RE, REG_FE, REG_IE };
	23
	24	#define CACHE_NR_REGS 3
	25	#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
	26
	27	struct stmpe_gpio {
	28	struct gpio_chip chip;
	29	struct stmpe *stmpe;
	30	struct device *dev;
	31	struct mutex irq_lock;
	32
	33	int irq_base;
b8e9cf0b	34	unsigned norequest_mask;
03f822f5 RV	35
	36	/* Caches of interrupt control registers for bus_lock */
	37	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	};
	40
	41	static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	42	{
	43	return container_of(chip, struct stmpe_gpio, chip);
	44	}
	45
	46	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	47	{
	48	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	49	struct stmpe *stmpe = stmpe_gpio->stmpe;
	50	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	51	u8 mask = 1 << (offset % 8);
	52	int ret;
	53
	54	ret = stmpe_reg_read(stmpe, reg);
	55	if (ret < 0)
	56	return ret;
	57
7535b8be	58	return !!(ret & mask);
03f822f5 RV	59	}
	60
	61	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	62	{
	63	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	64	struct stmpe *stmpe = stmpe_gpio->stmpe;
	65	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	66	u8 reg = stmpe->regs[which] - (offset / 8);
	67	u8 mask = 1 << (offset % 8);
	68
cccdceb9 VK	69	/*
	70	* Some variants have single register for gpio set/clear functionality.
	71	* For them we need to write 0 to clear and 1 to set.
	72	*/
	73	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	74	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	75	else
	76	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	77	}
	78
	79	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	80	unsigned offset, int val)
	81	{
	82	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	83	struct stmpe *stmpe = stmpe_gpio->stmpe;
	84	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	85	u8 mask = 1 << (offset % 8);
	86
	87	stmpe_gpio_set(chip, offset, val);
	88
	89	return stmpe_set_bits(stmpe, reg, mask, mask);
	90	}
	91
	92	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	93	unsigned offset)
	94	{
	95	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	96	struct stmpe *stmpe = stmpe_gpio->stmpe;
	97	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	98	u8 mask = 1 << (offset % 8);
	99
	100	return stmpe_set_bits(stmpe, reg, mask, 0);
	101	}
	102
	103	static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	104	{
	105	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	106
	107	return stmpe_gpio->irq_base + offset;
	108	}
	109
	110	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	111	{
	112	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	113	struct stmpe *stmpe = stmpe_gpio->stmpe;
	114
b8e9cf0b WS	115	if (stmpe_gpio->norequest_mask & (1 << offset))
	116	return -EINVAL;
	117
03f822f5 RV	118	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	119	}
	120
	121	static struct gpio_chip template_chip = {
	122	.label = "stmpe",
	123	.owner = THIS_MODULE,
	124	.direction_input = stmpe_gpio_direction_input,
	125	.get = stmpe_gpio_get,
	126	.direction_output = stmpe_gpio_direction_output,
	127	.set = stmpe_gpio_set,
	128	.to_irq = stmpe_gpio_to_irq,
	129	.request = stmpe_gpio_request,
	130	.can_sleep = 1,
	131	};
	132
2a866f39	133	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	134	{
2a866f39 LB	135	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
2a866f39 LB	136	int offset = d->irq - stmpe_gpio->irq_base;
03f822f5 RV	137	int regoffset = offset / 8;
	138	int mask = 1 << (offset % 8);
	139
	140	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	141	return -EINVAL;
	142
cccdceb9 VK	143	/* STMPE801 doesn't have RE and FE registers */
	144	if (stmpe_gpio->stmpe->partnum == STMPE801)
	145	return 0;
	146
03f822f5 RV	147	if (type == IRQ_TYPE_EDGE_RISING)
	148	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	149	else
	150	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	151
	152	if (type == IRQ_TYPE_EDGE_FALLING)
	153	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	154	else
	155	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	156
	157	return 0;
	158	}
	159
2a866f39	160	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	161	{
2a866f39	162	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	163
	164	mutex_lock(&stmpe_gpio->irq_lock);
	165	}
	166
2a866f39	167	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	168	{
2a866f39	169	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
03f822f5 RV	170	struct stmpe *stmpe = stmpe_gpio->stmpe;
	171	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	172	static const u8 regmap[] = {
	173	[REG_RE] = STMPE_IDX_GPRER_LSB,
	174	[REG_FE] = STMPE_IDX_GPFER_LSB,
	175	[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	176	};
	177	int i, j;
	178
	179	for (i = 0; i < CACHE_NR_REGS; i++) {
cccdceb9 VK	180	/* STMPE801 doesn't have RE and FE registers */
	181	if ((stmpe->partnum == STMPE801) &&
	182	(i != REG_IE))
	183	continue;
	184
03f822f5 RV	185	for (j = 0; j < num_banks; j++) {
	186	u8 old = stmpe_gpio->oldregs[i][j];
	187	u8 new = stmpe_gpio->regs[i][j];
	188
	189	if (new == old)
	190	continue;
	191
	192	stmpe_gpio->oldregs[i][j] = new;
	193	stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
	194	}
	195	}
	196
	197	mutex_unlock(&stmpe_gpio->irq_lock);
	198	}
	199
2a866f39	200	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	201	{
2a866f39 LB	202	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
2a866f39 LB	203	int offset = d->irq - stmpe_gpio->irq_base;
03f822f5 RV	204	int regoffset = offset / 8;
	205	int mask = 1 << (offset % 8);
	206
	207	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	208	}
	209
2a866f39	210	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	211	{
2a866f39 LB	212	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
2a866f39 LB	213	int offset = d->irq - stmpe_gpio->irq_base;
03f822f5 RV	214	int regoffset = offset / 8;
	215	int mask = 1 << (offset % 8);
	216
	217	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	218	}
	219
	220	static struct irq_chip stmpe_gpio_irq_chip = {
	221	.name = "stmpe-gpio",
2a866f39 LB	222	.irq_bus_lock = stmpe_gpio_irq_lock,
	223	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	224	.irq_mask = stmpe_gpio_irq_mask,
	225	.irq_unmask = stmpe_gpio_irq_unmask,
	226	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	227	};
	228
	229	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	230	{
	231	struct stmpe_gpio *stmpe_gpio = dev;
	232	struct stmpe *stmpe = stmpe_gpio->stmpe;
	233	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	234	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	235	u8 status[num_banks];
	236	int ret;
	237	int i;
	238
	239	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	240	if (ret < 0)
	241	return IRQ_NONE;
	242
	243	for (i = 0; i < num_banks; i++) {
	244	int bank = num_banks - i - 1;
	245	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	246	unsigned int stat = status[i];
	247
	248	stat &= enabled;
	249	if (!stat)
	250	continue;
	251
	252	while (stat) {
	253	int bit = __ffs(stat);
	254	int line = bank * 8 + bit;
	255
	256	handle_nested_irq(stmpe_gpio->irq_base + line);
	257	stat &= ~(1 << bit);
	258	}
	259
	260	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
cccdceb9 VK	261
	262	/* Edge detect register is not present on 801 */
	263	if (stmpe->partnum != STMPE801)
	264	stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
	265	+ i, status[i]);
03f822f5 RV	266	}
	267
	268	return IRQ_HANDLED;
	269	}
	270
	271	static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
	272	{
	273	int base = stmpe_gpio->irq_base;
	274	int irq;
	275
	276	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
b51804bc TG	277	irq_set_chip_data(irq, stmpe_gpio);
b51804bc TG	278	irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
03f822f5	279	handle_simple_irq);
b51804bc	280	irq_set_nested_thread(irq, 1);
03f822f5 RV	281	#ifdef CONFIG_ARM
	282	set_irq_flags(irq, IRQF_VALID);
	283	#else
b51804bc	284	irq_set_noprobe(irq);
03f822f5 RV	285	#endif
	286	}
	287
	288	return 0;
	289	}
	290
	291	static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
	292	{
	293	int base = stmpe_gpio->irq_base;
	294	int irq;
	295
	296	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
	297	#ifdef CONFIG_ARM
	298	set_irq_flags(irq, 0);
	299	#endif
b51804bc TG	300	irq_set_chip_and_handler(irq, NULL, NULL);
b51804bc TG	301	irq_set_chip_data(irq, NULL);
03f822f5 RV	302	}
	303	}
	304
	305	static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
	306	{
	307	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	308	struct device_node *np = pdev->dev.of_node;
03f822f5 RV	309	struct stmpe_gpio_platform_data *pdata;
	310	struct stmpe_gpio *stmpe_gpio;
	311	int ret;
38040c85	312	int irq = 0;
03f822f5 RV	313
03f822f5 RV	314	pdata = stmpe->pdata->gpio;
03f822f5 RV	315
03f822f5 RV	316	irq = platform_get_irq(pdev, 0);
03f822f5 RV	317
	318	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	319	if (!stmpe_gpio)
	320	return -ENOMEM;
	321
	322	mutex_init(&stmpe_gpio->irq_lock);
	323
	324	stmpe_gpio->dev = &pdev->dev;
	325	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	326	stmpe_gpio->chip = template_chip;
	327	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	328	stmpe_gpio->chip.dev = &pdev->dev;
	329	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
	330
86605cfe VKS	331	if (pdata)
	332	stmpe_gpio->norequest_mask = pdata->norequest_mask;
	333	else if (np)
	334	of_property_read_u32(np, "st,norequest-mask",
	335	&stmpe_gpio->norequest_mask);
	336
38040c85 CB	337	if (irq >= 0)
	338	stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	339	else
	340	dev_info(&pdev->dev,
	341	"device configured in no-irq mode; "
	342	"irqs are not available\n");
03f822f5 RV	343
	344	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	345	if (ret)
02bf0749	346	goto out_free;
03f822f5	347
38040c85 CB	348	if (irq >= 0) {
	349	ret = stmpe_gpio_irq_init(stmpe_gpio);
	350	if (ret)
	351	goto out_disable;
03f822f5	352
38040c85 CB	353	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
	354	IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
	355	if (ret) {
	356	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
	357	goto out_removeirq;
	358	}
03f822f5 RV	359	}
	360
	361	ret = gpiochip_add(&stmpe_gpio->chip);
	362	if (ret) {
	363	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	364	goto out_freeirq;
	365	}
	366
	367	if (pdata && pdata->setup)
	368	pdata->setup(stmpe, stmpe_gpio->chip.base);
	369
	370	platform_set_drvdata(pdev, stmpe_gpio);
	371
	372	return 0;
	373
	374	out_freeirq:
38040c85 CB	375	if (irq >= 0)
38040c85 CB	376	free_irq(irq, stmpe_gpio);
03f822f5	377	out_removeirq:
38040c85 CB	378	if (irq >= 0)
38040c85 CB	379	stmpe_gpio_irq_remove(stmpe_gpio);
02bf0749 VK	380	out_disable:
02bf0749 VK	381	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
03f822f5 RV	382	out_free:
	383	kfree(stmpe_gpio);
	384	return ret;
	385	}
	386
	387	static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
	388	{
	389	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	390	struct stmpe *stmpe = stmpe_gpio->stmpe;
	391	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	392	int irq = platform_get_irq(pdev, 0);
	393	int ret;
	394
	395	if (pdata && pdata->remove)
	396	pdata->remove(stmpe, stmpe_gpio->chip.base);
	397
	398	ret = gpiochip_remove(&stmpe_gpio->chip);
	399	if (ret < 0) {
	400	dev_err(stmpe_gpio->dev,
	401	"unable to remove gpiochip: %d\n", ret);
	402	return ret;
	403	}
	404
	405	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	406
38040c85 CB	407	if (irq >= 0) {
	408	free_irq(irq, stmpe_gpio);
	409	stmpe_gpio_irq_remove(stmpe_gpio);
	410	}
03f822f5 RV	411	platform_set_drvdata(pdev, NULL);
	412	kfree(stmpe_gpio);
	413
	414	return 0;
	415	}
	416
	417	static struct platform_driver stmpe_gpio_driver = {
	418	.driver.name = "stmpe-gpio",
	419	.driver.owner = THIS_MODULE,
	420	.probe = stmpe_gpio_probe,
	421	.remove = __devexit_p(stmpe_gpio_remove),
	422	};
	423
	424	static int __init stmpe_gpio_init(void)
	425	{
	426	return platform_driver_register(&stmpe_gpio_driver);
	427	}
	428	subsys_initcall(stmpe_gpio_init);
	429
	430	static void __exit stmpe_gpio_exit(void)
	431	{
	432	platform_driver_unregister(&stmpe_gpio_driver);
	433	}
	434	module_exit(stmpe_gpio_exit);
	435
	436	MODULE_LICENSE("GPL v2");
	437	MODULE_DESCRIPTION("STMPExxxx GPIO driver");
	438	MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");