Commit | Line | Data |
---|---|---|
3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
641d0342 | 20 | #include <linux/err.h> |
3c92db9a EG |
21 | #include <linux/init.h> |
22 | #include <linux/irq.h> | |
2e47b8b3 | 23 | #include <linux/interrupt.h> |
3c92db9a EG |
24 | #include <linux/io.h> |
25 | #include <linux/gpio.h> | |
5c1e2c9d | 26 | #include <linux/of_device.h> |
88d8951e SW |
27 | #include <linux/platform_device.h> |
28 | #include <linux/module.h> | |
6f74dc9b | 29 | #include <linux/irqdomain.h> |
de88cbb7 | 30 | #include <linux/irqchip/chained_irq.h> |
3e215d0a | 31 | #include <linux/pinctrl/consumer.h> |
8939ddc7 | 32 | #include <linux/pm.h> |
3c92db9a | 33 | |
3c92db9a EG |
34 | #define GPIO_BANK(x) ((x) >> 5) |
35 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
36 | #define GPIO_BIT(x) ((x) & 0x7) | |
37 | ||
5c1e2c9d SW |
38 | #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ |
39 | GPIO_PORT(x) * 4) | |
3c92db9a EG |
40 | |
41 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
42 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
43 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
44 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
45 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
46 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
47 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
48 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
49 | ||
5c1e2c9d SW |
50 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) |
51 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) | |
52 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) | |
53 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) | |
54 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) | |
55 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) | |
3c92db9a EG |
56 | |
57 | #define GPIO_INT_LVL_MASK 0x010101 | |
58 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
59 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
60 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
61 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
62 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
63 | ||
64 | struct tegra_gpio_bank { | |
65 | int bank; | |
66 | int irq; | |
67 | spinlock_t lvl_lock[4]; | |
8939ddc7 | 68 | #ifdef CONFIG_PM_SLEEP |
2e47b8b3 CC |
69 | u32 cnf[4]; |
70 | u32 out[4]; | |
71 | u32 oe[4]; | |
72 | u32 int_enb[4]; | |
73 | u32 int_lvl[4]; | |
203f31cb | 74 | u32 wake_enb[4]; |
2e47b8b3 | 75 | #endif |
3c92db9a EG |
76 | }; |
77 | ||
df231f28 | 78 | static struct device *dev; |
bdc93a77 | 79 | static struct irq_domain *irq_domain; |
88d8951e | 80 | static void __iomem *regs; |
3391811c | 81 | static u32 tegra_gpio_bank_count; |
5c1e2c9d SW |
82 | static u32 tegra_gpio_bank_stride; |
83 | static u32 tegra_gpio_upper_offset; | |
3391811c | 84 | static struct tegra_gpio_bank *tegra_gpio_banks; |
88d8951e SW |
85 | |
86 | static inline void tegra_gpio_writel(u32 val, u32 reg) | |
87 | { | |
88 | __raw_writel(val, regs + reg); | |
89 | } | |
90 | ||
91 | static inline u32 tegra_gpio_readl(u32 reg) | |
92 | { | |
93 | return __raw_readl(regs + reg); | |
94 | } | |
3c92db9a EG |
95 | |
96 | static int tegra_gpio_compose(int bank, int port, int bit) | |
97 | { | |
98 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
99 | } | |
100 | ||
101 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
102 | { | |
103 | u32 val; | |
104 | ||
105 | val = 0x100 << GPIO_BIT(gpio); | |
106 | if (value) | |
107 | val |= 1 << GPIO_BIT(gpio); | |
88d8951e | 108 | tegra_gpio_writel(val, reg); |
3c92db9a EG |
109 | } |
110 | ||
3e215d0a | 111 | static void tegra_gpio_enable(int gpio) |
3c92db9a EG |
112 | { |
113 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
114 | } | |
115 | ||
3e215d0a | 116 | static void tegra_gpio_disable(int gpio) |
3c92db9a EG |
117 | { |
118 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
119 | } | |
120 | ||
924a0987 | 121 | static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) |
3e215d0a SW |
122 | { |
123 | return pinctrl_request_gpio(offset); | |
124 | } | |
125 | ||
924a0987 | 126 | static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) |
3e215d0a SW |
127 | { |
128 | pinctrl_free_gpio(offset); | |
129 | tegra_gpio_disable(offset); | |
130 | } | |
131 | ||
3c92db9a EG |
132 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
133 | { | |
134 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
135 | } | |
136 | ||
137 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
138 | { | |
195812e4 LD |
139 | /* If gpio is in output mode then read from the out value */ |
140 | if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1) | |
141 | return (tegra_gpio_readl(GPIO_OUT(offset)) >> | |
142 | GPIO_BIT(offset)) & 0x1; | |
143 | ||
88d8951e | 144 | return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
3c92db9a EG |
145 | } |
146 | ||
147 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
148 | { | |
149 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
3e215d0a | 150 | tegra_gpio_enable(offset); |
3c92db9a EG |
151 | return 0; |
152 | } | |
153 | ||
154 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
155 | int value) | |
156 | { | |
157 | tegra_gpio_set(chip, offset, value); | |
158 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
3e215d0a | 159 | tegra_gpio_enable(offset); |
3c92db9a EG |
160 | return 0; |
161 | } | |
162 | ||
438a99c0 SW |
163 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
164 | { | |
bdc93a77 | 165 | return irq_find_mapping(irq_domain, offset); |
438a99c0 | 166 | } |
3c92db9a EG |
167 | |
168 | static struct gpio_chip tegra_gpio_chip = { | |
169 | .label = "tegra-gpio", | |
3e215d0a SW |
170 | .request = tegra_gpio_request, |
171 | .free = tegra_gpio_free, | |
3c92db9a EG |
172 | .direction_input = tegra_gpio_direction_input, |
173 | .get = tegra_gpio_get, | |
174 | .direction_output = tegra_gpio_direction_output, | |
175 | .set = tegra_gpio_set, | |
438a99c0 | 176 | .to_irq = tegra_gpio_to_irq, |
3c92db9a | 177 | .base = 0, |
3c92db9a EG |
178 | }; |
179 | ||
37337a8d | 180 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 181 | { |
6f74dc9b | 182 | int gpio = d->hwirq; |
3c92db9a | 183 | |
88d8951e | 184 | tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
3c92db9a EG |
185 | } |
186 | ||
37337a8d | 187 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 188 | { |
6f74dc9b | 189 | int gpio = d->hwirq; |
3c92db9a EG |
190 | |
191 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
192 | } | |
193 | ||
37337a8d | 194 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 195 | { |
6f74dc9b | 196 | int gpio = d->hwirq; |
3c92db9a EG |
197 | |
198 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
199 | } | |
200 | ||
37337a8d | 201 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 202 | { |
6f74dc9b | 203 | int gpio = d->hwirq; |
37337a8d | 204 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
3c92db9a EG |
205 | int port = GPIO_PORT(gpio); |
206 | int lvl_type; | |
207 | int val; | |
208 | unsigned long flags; | |
df231f28 | 209 | int ret; |
3c92db9a EG |
210 | |
211 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
212 | case IRQ_TYPE_EDGE_RISING: | |
213 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
214 | break; | |
215 | ||
216 | case IRQ_TYPE_EDGE_FALLING: | |
217 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
218 | break; | |
219 | ||
220 | case IRQ_TYPE_EDGE_BOTH: | |
221 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
222 | break; | |
223 | ||
224 | case IRQ_TYPE_LEVEL_HIGH: | |
225 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
226 | break; | |
227 | ||
228 | case IRQ_TYPE_LEVEL_LOW: | |
229 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
230 | break; | |
231 | ||
232 | default: | |
233 | return -EINVAL; | |
234 | } | |
235 | ||
e3a2e878 | 236 | ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio); |
df231f28 SW |
237 | if (ret) { |
238 | dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio); | |
239 | return ret; | |
240 | } | |
241 | ||
3c92db9a EG |
242 | spin_lock_irqsave(&bank->lvl_lock[port], flags); |
243 | ||
88d8951e | 244 | val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
3c92db9a EG |
245 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
246 | val |= lvl_type << GPIO_BIT(gpio); | |
88d8951e | 247 | tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); |
3c92db9a EG |
248 | |
249 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
250 | ||
d941136f SW |
251 | tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); |
252 | tegra_gpio_enable(gpio); | |
253 | ||
3c92db9a | 254 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
f170d71e | 255 | irq_set_handler_locked(d, handle_level_irq); |
3c92db9a | 256 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
f170d71e | 257 | irq_set_handler_locked(d, handle_edge_irq); |
3c92db9a EG |
258 | |
259 | return 0; | |
260 | } | |
261 | ||
df231f28 SW |
262 | static void tegra_gpio_irq_shutdown(struct irq_data *d) |
263 | { | |
264 | int gpio = d->hwirq; | |
265 | ||
e3a2e878 | 266 | gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio); |
df231f28 SW |
267 | } |
268 | ||
bd0b9ac4 | 269 | static void tegra_gpio_irq_handler(struct irq_desc *desc) |
3c92db9a | 270 | { |
3c92db9a EG |
271 | int port; |
272 | int pin; | |
273 | int unmasked = 0; | |
98022940 | 274 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476f8b4c | 275 | struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); |
3c92db9a | 276 | |
98022940 | 277 | chained_irq_enter(chip, desc); |
3c92db9a | 278 | |
3c92db9a EG |
279 | for (port = 0; port < 4; port++) { |
280 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
88d8951e SW |
281 | unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & |
282 | tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
283 | u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
3c92db9a EG |
284 | |
285 | for_each_set_bit(pin, &sta, 8) { | |
88d8951e | 286 | tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); |
3c92db9a EG |
287 | |
288 | /* if gpio is edge triggered, clear condition | |
20a8a968 | 289 | * before executing the handler so that we don't |
3c92db9a EG |
290 | * miss edges |
291 | */ | |
292 | if (lvl & (0x100 << pin)) { | |
293 | unmasked = 1; | |
98022940 | 294 | chained_irq_exit(chip, desc); |
3c92db9a EG |
295 | } |
296 | ||
297 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
298 | } | |
299 | } | |
300 | ||
301 | if (!unmasked) | |
98022940 | 302 | chained_irq_exit(chip, desc); |
3c92db9a EG |
303 | |
304 | } | |
305 | ||
8939ddc7 LD |
306 | #ifdef CONFIG_PM_SLEEP |
307 | static int tegra_gpio_resume(struct device *dev) | |
2e47b8b3 CC |
308 | { |
309 | unsigned long flags; | |
c8309ef6 CC |
310 | int b; |
311 | int p; | |
2e47b8b3 CC |
312 | |
313 | local_irq_save(flags); | |
314 | ||
3391811c | 315 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
316 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
317 | ||
318 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
319 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
320 | tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); |
321 | tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); | |
322 | tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); | |
323 | tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); | |
324 | tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); | |
2e47b8b3 CC |
325 | } |
326 | } | |
327 | ||
328 | local_irq_restore(flags); | |
8939ddc7 | 329 | return 0; |
2e47b8b3 CC |
330 | } |
331 | ||
8939ddc7 | 332 | static int tegra_gpio_suspend(struct device *dev) |
2e47b8b3 CC |
333 | { |
334 | unsigned long flags; | |
c8309ef6 CC |
335 | int b; |
336 | int p; | |
2e47b8b3 | 337 | |
2e47b8b3 | 338 | local_irq_save(flags); |
3391811c | 339 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
340 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
341 | ||
342 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
343 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
344 | bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); |
345 | bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); | |
346 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); | |
347 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
348 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
203f31cb JL |
349 | |
350 | /* Enable gpio irq for wake up source */ | |
351 | tegra_gpio_writel(bank->wake_enb[p], | |
352 | GPIO_INT_ENB(gpio)); | |
2e47b8b3 CC |
353 | } |
354 | } | |
355 | local_irq_restore(flags); | |
8939ddc7 | 356 | return 0; |
2e47b8b3 CC |
357 | } |
358 | ||
203f31cb | 359 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 360 | { |
37337a8d | 361 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
203f31cb JL |
362 | int gpio = d->hwirq; |
363 | u32 port, bit, mask; | |
364 | ||
365 | port = GPIO_PORT(gpio); | |
366 | bit = GPIO_BIT(gpio); | |
367 | mask = BIT(bit); | |
368 | ||
369 | if (enable) | |
370 | bank->wake_enb[port] |= mask; | |
371 | else | |
372 | bank->wake_enb[port] &= ~mask; | |
373 | ||
6845664a | 374 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
375 | } |
376 | #endif | |
3c92db9a EG |
377 | |
378 | static struct irq_chip tegra_gpio_irq_chip = { | |
379 | .name = "GPIO", | |
37337a8d LB |
380 | .irq_ack = tegra_gpio_irq_ack, |
381 | .irq_mask = tegra_gpio_irq_mask, | |
382 | .irq_unmask = tegra_gpio_irq_unmask, | |
383 | .irq_set_type = tegra_gpio_irq_set_type, | |
df231f28 | 384 | .irq_shutdown = tegra_gpio_irq_shutdown, |
8939ddc7 | 385 | #ifdef CONFIG_PM_SLEEP |
203f31cb | 386 | .irq_set_wake = tegra_gpio_irq_set_wake, |
2e47b8b3 | 387 | #endif |
3c92db9a EG |
388 | }; |
389 | ||
8939ddc7 LD |
390 | static const struct dev_pm_ops tegra_gpio_pm_ops = { |
391 | SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) | |
392 | }; | |
393 | ||
5c1e2c9d SW |
394 | struct tegra_gpio_soc_config { |
395 | u32 bank_stride; | |
396 | u32 upper_offset; | |
397 | }; | |
398 | ||
399 | static struct tegra_gpio_soc_config tegra20_gpio_config = { | |
400 | .bank_stride = 0x80, | |
401 | .upper_offset = 0x800, | |
402 | }; | |
403 | ||
404 | static struct tegra_gpio_soc_config tegra30_gpio_config = { | |
405 | .bank_stride = 0x100, | |
406 | .upper_offset = 0x80, | |
407 | }; | |
408 | ||
30373b63 | 409 | static const struct of_device_id tegra_gpio_of_match[] = { |
5c1e2c9d SW |
410 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
411 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, | |
412 | { }, | |
413 | }; | |
3c92db9a EG |
414 | |
415 | /* This lock class tells lockdep that GPIO irqs are in a different | |
416 | * category than their parents, so it won't report false recursion. | |
417 | */ | |
418 | static struct lock_class_key gpio_lock_class; | |
419 | ||
3836309d | 420 | static int tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 421 | { |
5c1e2c9d SW |
422 | const struct of_device_id *match; |
423 | struct tegra_gpio_soc_config *config; | |
88d8951e | 424 | struct resource *res; |
3c92db9a | 425 | struct tegra_gpio_bank *bank; |
f57f98a6 | 426 | int ret; |
47008001 | 427 | int gpio; |
3c92db9a EG |
428 | int i; |
429 | int j; | |
430 | ||
df231f28 SW |
431 | dev = &pdev->dev; |
432 | ||
5c1e2c9d | 433 | match = of_match_device(tegra_gpio_of_match, &pdev->dev); |
165b6c2f SW |
434 | if (!match) { |
435 | dev_err(&pdev->dev, "Error: No device match found\n"); | |
436 | return -ENODEV; | |
437 | } | |
438 | config = (struct tegra_gpio_soc_config *)match->data; | |
5c1e2c9d SW |
439 | |
440 | tegra_gpio_bank_stride = config->bank_stride; | |
441 | tegra_gpio_upper_offset = config->upper_offset; | |
442 | ||
3391811c SW |
443 | for (;;) { |
444 | res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); | |
445 | if (!res) | |
446 | break; | |
447 | tegra_gpio_bank_count++; | |
448 | } | |
449 | if (!tegra_gpio_bank_count) { | |
450 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
451 | return -ENODEV; | |
452 | } | |
453 | ||
454 | tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; | |
455 | ||
456 | tegra_gpio_banks = devm_kzalloc(&pdev->dev, | |
457 | tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), | |
458 | GFP_KERNEL); | |
c88a73b3 | 459 | if (!tegra_gpio_banks) |
3391811c | 460 | return -ENODEV; |
3391811c | 461 | |
d0235677 LW |
462 | irq_domain = irq_domain_add_linear(pdev->dev.of_node, |
463 | tegra_gpio_chip.ngpio, | |
bdc93a77 | 464 | &irq_domain_simple_ops, NULL); |
d0235677 LW |
465 | if (!irq_domain) |
466 | return -ENODEV; | |
6f74dc9b | 467 | |
3391811c | 468 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
88d8951e SW |
469 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
470 | if (!res) { | |
471 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
472 | return -ENODEV; | |
473 | } | |
474 | ||
475 | bank = &tegra_gpio_banks[i]; | |
476 | bank->bank = i; | |
477 | bank->irq = res->start; | |
478 | } | |
479 | ||
480 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
641d0342 TR |
481 | regs = devm_ioremap_resource(&pdev->dev, res); |
482 | if (IS_ERR(regs)) | |
483 | return PTR_ERR(regs); | |
88d8951e | 484 | |
4a3398ee | 485 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
486 | for (j = 0; j < 4; j++) { |
487 | int gpio = tegra_gpio_compose(i, j, 0); | |
88d8951e | 488 | tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); |
3c92db9a EG |
489 | } |
490 | } | |
491 | ||
88d8951e | 492 | tegra_gpio_chip.of_node = pdev->dev.of_node; |
df221227 | 493 | |
f57f98a6 SW |
494 | ret = gpiochip_add(&tegra_gpio_chip); |
495 | if (ret < 0) { | |
496 | irq_domain_remove(irq_domain); | |
497 | return ret; | |
498 | } | |
3c92db9a | 499 | |
3391811c | 500 | for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { |
d0235677 | 501 | int irq = irq_create_mapping(irq_domain, gpio); |
47008001 | 502 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 503 | |
47008001 | 504 | bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; |
3c92db9a | 505 | |
47008001 SW |
506 | irq_set_lockdep_class(irq, &gpio_lock_class); |
507 | irq_set_chip_data(irq, bank); | |
508 | irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, | |
f38c02f3 | 509 | handle_simple_irq); |
3c92db9a EG |
510 | } |
511 | ||
3391811c | 512 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
513 | bank = &tegra_gpio_banks[i]; |
514 | ||
e88d251d RK |
515 | irq_set_chained_handler_and_data(bank->irq, |
516 | tegra_gpio_irq_handler, bank); | |
3c92db9a EG |
517 | |
518 | for (j = 0; j < 4; j++) | |
519 | spin_lock_init(&bank->lvl_lock[j]); | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
88d8951e SW |
525 | static struct platform_driver tegra_gpio_driver = { |
526 | .driver = { | |
527 | .name = "tegra-gpio", | |
8939ddc7 | 528 | .pm = &tegra_gpio_pm_ops, |
88d8951e SW |
529 | .of_match_table = tegra_gpio_of_match, |
530 | }, | |
531 | .probe = tegra_gpio_probe, | |
532 | }; | |
533 | ||
534 | static int __init tegra_gpio_init(void) | |
535 | { | |
536 | return platform_driver_register(&tegra_gpio_driver); | |
537 | } | |
3c92db9a EG |
538 | postcore_initcall(tegra_gpio_init); |
539 | ||
540 | #ifdef CONFIG_DEBUG_FS | |
541 | ||
542 | #include <linux/debugfs.h> | |
543 | #include <linux/seq_file.h> | |
544 | ||
545 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
546 | { | |
547 | int i; | |
548 | int j; | |
549 | ||
4a3398ee | 550 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
551 | for (j = 0; j < 4; j++) { |
552 | int gpio = tegra_gpio_compose(i, j, 0); | |
2e47b8b3 CC |
553 | seq_printf(s, |
554 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
555 | i, j, | |
88d8951e SW |
556 | tegra_gpio_readl(GPIO_CNF(gpio)), |
557 | tegra_gpio_readl(GPIO_OE(gpio)), | |
558 | tegra_gpio_readl(GPIO_OUT(gpio)), | |
559 | tegra_gpio_readl(GPIO_IN(gpio)), | |
560 | tegra_gpio_readl(GPIO_INT_STA(gpio)), | |
561 | tegra_gpio_readl(GPIO_INT_ENB(gpio)), | |
562 | tegra_gpio_readl(GPIO_INT_LVL(gpio))); | |
3c92db9a EG |
563 | } |
564 | } | |
565 | return 0; | |
566 | } | |
567 | ||
568 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
569 | { | |
570 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
571 | } | |
572 | ||
573 | static const struct file_operations debug_fops = { | |
574 | .open = dbg_gpio_open, | |
575 | .read = seq_read, | |
576 | .llseek = seq_lseek, | |
577 | .release = single_release, | |
578 | }; | |
579 | ||
580 | static int __init tegra_gpio_debuginit(void) | |
581 | { | |
582 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
583 | NULL, NULL, &debug_fops); | |
584 | return 0; | |
585 | } | |
586 | late_initcall(tegra_gpio_debuginit); | |
587 | #endif |