[deliverable/linux.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#include <asm/mach/irq.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};

static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	/* If gpio is in output mode then read from the out value */
	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
		return (tegra_gpio_readl(GPIO_OUT(offset)) >>
				GPIO_BIT(offset)) & 0x1;

	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static struct of_device_id tegra_gpio_of_match[] = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int tegra_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	if (match)
		config = (struct tegra_gpio_soc_config *)match->data;
	else
		config = &tegra20_gpio_config;

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks) {
		dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
		return -ENODEV;
	}

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Missing MEM resource\n");
		return -ENODEV;
	}

	regs = devm_request_and_ioremap(&pdev->dev, res);
	if (!regs) {
		dev_err(&pdev->dev, "Couldn't ioremap regs\n");
		return -ENODEV;
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	tegra_gpio_chip.of_node = pdev->dev.of_node;
#endif

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.owner	= THIS_MODULE,
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23	#include <linux/io.h>
3c92db9a EG	24	#include <linux/gpio.h>
5c1e2c9d	25	#include <linux/of_device.h>
88d8951e SW	26	#include <linux/platform_device.h>
88d8951e SW	27	#include <linux/module.h>
6f74dc9b	28	#include <linux/irqdomain.h>
3e215d0a	29	#include <linux/pinctrl/consumer.h>
8939ddc7	30	#include <linux/pm.h>
3c92db9a	31
98022940 WD	32	#include <asm/mach/irq.h>
98022940 WD	33
3c92db9a EG	34	#define GPIO_BANK(x) ((x) >> 5)
	35	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	36	#define GPIO_BIT(x) ((x) & 0x7)
	37
5c1e2c9d SW	38	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	39	GPIO_PORT(x) * 4)
3c92db9a EG	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
5c1e2c9d SW	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
8939ddc7	68	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
	74	#endif
3c92db9a EG	75	};
3c92db9a EG	76
bdc93a77	77	static struct irq_domain *irq_domain;
88d8951e	78	static void __iomem *regs;
3391811c	79	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	80	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	81	static u32 tegra_gpio_upper_offset;
3391811c	82	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	83
	84	static inline void tegra_gpio_writel(u32 val, u32 reg)
	85	{
	86	__raw_writel(val, regs + reg);
	87	}
	88
	89	static inline u32 tegra_gpio_readl(u32 reg)
	90	{
	91	return __raw_readl(regs + reg);
	92	}
3c92db9a EG	93
	94	static int tegra_gpio_compose(int bank, int port, int bit)
	95	{
	96	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	97	}
	98
	99	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	100	{
	101	u32 val;
	102
	103	val = 0x100 << GPIO_BIT(gpio);
	104	if (value)
	105	val \|= 1 << GPIO_BIT(gpio);
88d8951e	106	tegra_gpio_writel(val, reg);
3c92db9a EG	107	}
3c92db9a EG	108
3e215d0a	109	static void tegra_gpio_enable(int gpio)
3c92db9a EG	110	{
	111	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	112	}
	113
3e215d0a	114	static void tegra_gpio_disable(int gpio)
3c92db9a EG	115	{
	116	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	117	}
	118
924a0987	119	static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	120	{
	121	return pinctrl_request_gpio(offset);
	122	}
	123
924a0987	124	static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	125	{
	126	pinctrl_free_gpio(offset);
	127	tegra_gpio_disable(offset);
	128	}
	129
3c92db9a EG	130	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	131	{
	132	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	133	}
	134
	135	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	136	{
195812e4 LD	137	/* If gpio is in output mode then read from the out value */
	138	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
	139	return (tegra_gpio_readl(GPIO_OUT(offset)) >>
	140	GPIO_BIT(offset)) & 0x1;
	141
88d8951e	142	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	143	}
	144
	145	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	146	{
	147	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	148	tegra_gpio_enable(offset);
3c92db9a EG	149	return 0;
	150	}
	151
	152	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	153	int value)
	154	{
	155	tegra_gpio_set(chip, offset, value);
	156	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	157	tegra_gpio_enable(offset);
3c92db9a EG	158	return 0;
	159	}
	160
438a99c0 SW	161	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	162	{
bdc93a77	163	return irq_find_mapping(irq_domain, offset);
438a99c0	164	}
3c92db9a EG	165
	166	static struct gpio_chip tegra_gpio_chip = {
	167	.label = "tegra-gpio",
3e215d0a SW	168	.request = tegra_gpio_request,
3e215d0a SW	169	.free = tegra_gpio_free,
3c92db9a EG	170	.direction_input = tegra_gpio_direction_input,
	171	.get = tegra_gpio_get,
	172	.direction_output = tegra_gpio_direction_output,
	173	.set = tegra_gpio_set,
438a99c0	174	.to_irq = tegra_gpio_to_irq,
3c92db9a	175	.base = 0,
3c92db9a EG	176	};
3c92db9a EG	177
37337a8d	178	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	179	{
6f74dc9b	180	int gpio = d->hwirq;
3c92db9a	181
88d8951e	182	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	183	}
3c92db9a EG	184
37337a8d	185	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	186	{
6f74dc9b	187	int gpio = d->hwirq;
3c92db9a EG	188
	189	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	190	}
	191
37337a8d	192	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	193	{
6f74dc9b	194	int gpio = d->hwirq;
3c92db9a EG	195
	196	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	197	}
	198
37337a8d	199	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	200	{
6f74dc9b	201	int gpio = d->hwirq;
37337a8d	202	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	203	int port = GPIO_PORT(gpio);
	204	int lvl_type;
	205	int val;
	206	unsigned long flags;
	207
	208	switch (type & IRQ_TYPE_SENSE_MASK) {
	209	case IRQ_TYPE_EDGE_RISING:
	210	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	211	break;
	212
	213	case IRQ_TYPE_EDGE_FALLING:
	214	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	215	break;
	216
	217	case IRQ_TYPE_EDGE_BOTH:
	218	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	219	break;
	220
	221	case IRQ_TYPE_LEVEL_HIGH:
	222	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	223	break;
	224
	225	case IRQ_TYPE_LEVEL_LOW:
	226	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	227	break;
	228
	229	default:
	230	return -EINVAL;
	231	}
	232
	233	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	234
88d8951e	235	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	236	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	237	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	238	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	239
	240	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	241
d941136f SW	242	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	243	tegra_gpio_enable(gpio);
	244
3c92db9a	245	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	246	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	247	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	248	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	249
	250	return 0;
	251	}
	252
	253	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	254	{
	255	struct tegra_gpio_bank *bank;
	256	int port;
	257	int pin;
	258	int unmasked = 0;
98022940	259	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	260
98022940	261	chained_irq_enter(chip, desc);
3c92db9a	262
6845664a	263	bank = irq_get_handler_data(irq);
3c92db9a EG	264
	265	for (port = 0; port < 4; port++) {
	266	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	267	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	268	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	269	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	270
3c92db9a EG	271	for_each_set_bit(pin, &sta, 8) {
88d8951e	272	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	273
	274	/* if gpio is edge triggered, clear condition
	275	* before executing the hander so that we don't
	276	* miss edges
	277	*/
	278	if (lvl & (0x100 << pin)) {
	279	unmasked = 1;
98022940	280	chained_irq_exit(chip, desc);
3c92db9a EG	281	}
	282
	283	generic_handle_irq(gpio_to_irq(gpio + pin));
	284	}
	285	}
	286
	287	if (!unmasked)
98022940	288	chained_irq_exit(chip, desc);
3c92db9a EG	289
	290	}
	291
8939ddc7 LD	292	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	293	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	294	{
2e47b8b3 CC	295	unsigned long flags;
c8309ef6 CC	296	int b;
c8309ef6 CC	297	int p;
2e47b8b3 CC	298
	299	local_irq_save(flags);
	300
3391811c	301	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	302	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	303
	304	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	305	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	306	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	307	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	308	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	309	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	310	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	311	}
	312	}
	313
	314	local_irq_restore(flags);
8939ddc7	315	return 0;
2e47b8b3 CC	316	}
2e47b8b3 CC	317
8939ddc7	318	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	319	{
2e47b8b3 CC	320	unsigned long flags;
c8309ef6 CC	321	int b;
c8309ef6 CC	322	int p;
2e47b8b3	323
2e47b8b3	324	local_irq_save(flags);
3391811c	325	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	326	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	327
	328	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	329	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	330	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	331	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	332	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	333	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	334	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
2e47b8b3 CC	335	}
	336	}
	337	local_irq_restore(flags);
8939ddc7	338	return 0;
2e47b8b3 CC	339	}
2e47b8b3 CC	340
37337a8d	341	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	342	{
37337a8d	343	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	344	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	345	}
2e47b8b3 CC	346	#endif
3c92db9a EG	347
	348	static struct irq_chip tegra_gpio_irq_chip = {
	349	.name = "GPIO",
37337a8d LB	350	.irq_ack = tegra_gpio_irq_ack,
	351	.irq_mask = tegra_gpio_irq_mask,
	352	.irq_unmask = tegra_gpio_irq_unmask,
	353	.irq_set_type = tegra_gpio_irq_set_type,
8939ddc7	354	#ifdef CONFIG_PM_SLEEP
37337a8d	355	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	356	#endif
3c92db9a EG	357	};
3c92db9a EG	358
8939ddc7 LD	359	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	360	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	361	};
	362
5c1e2c9d SW	363	struct tegra_gpio_soc_config {
	364	u32 bank_stride;
	365	u32 upper_offset;
	366	};
	367
	368	static struct tegra_gpio_soc_config tegra20_gpio_config = {
	369	.bank_stride = 0x80,
	370	.upper_offset = 0x800,
	371	};
	372
	373	static struct tegra_gpio_soc_config tegra30_gpio_config = {
	374	.bank_stride = 0x100,
	375	.upper_offset = 0x80,
	376	};
	377
aeca8ad1	378	static struct of_device_id tegra_gpio_of_match[] = {
5c1e2c9d SW	379	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	380	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	381	{ },
	382	};
3c92db9a EG	383
	384	/* This lock class tells lockdep that GPIO irqs are in a different
	385	* category than their parents, so it won't report false recursion.
	386	*/
	387	static struct lock_class_key gpio_lock_class;
	388
3836309d	389	static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	390	{
5c1e2c9d SW	391	const struct of_device_id *match;
5c1e2c9d SW	392	struct tegra_gpio_soc_config *config;
88d8951e	393	struct resource *res;
3c92db9a	394	struct tegra_gpio_bank *bank;
47008001	395	int gpio;
3c92db9a EG	396	int i;
	397	int j;
	398
5c1e2c9d SW	399	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	400	if (match)
	401	config = (struct tegra_gpio_soc_config *)match->data;
	402	else
	403	config = &tegra20_gpio_config;
	404
	405	tegra_gpio_bank_stride = config->bank_stride;
	406	tegra_gpio_upper_offset = config->upper_offset;
	407
3391811c SW	408	for (;;) {
	409	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	410	if (!res)
	411	break;
	412	tegra_gpio_bank_count++;
	413	}
	414	if (!tegra_gpio_bank_count) {
	415	dev_err(&pdev->dev, "Missing IRQ resource\n");
	416	return -ENODEV;
	417	}
	418
	419	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	420
	421	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	422	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	423	GFP_KERNEL);
	424	if (!tegra_gpio_banks) {
	425	dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
	426	return -ENODEV;
	427	}
	428
d0235677 LW	429	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	430	tegra_gpio_chip.ngpio,
bdc93a77	431	&irq_domain_simple_ops, NULL);
d0235677 LW	432	if (!irq_domain)
d0235677 LW	433	return -ENODEV;
6f74dc9b	434
3391811c	435	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	436	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	437	if (!res) {
	438	dev_err(&pdev->dev, "Missing IRQ resource\n");
	439	return -ENODEV;
	440	}
	441
	442	bank = &tegra_gpio_banks[i];
	443	bank->bank = i;
	444	bank->irq = res->start;
	445	}
	446
	447	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	448	if (!res) {
	449	dev_err(&pdev->dev, "Missing MEM resource\n");
	450	return -ENODEV;
	451	}
	452
aedd4fdf	453	regs = devm_request_and_ioremap(&pdev->dev, res);
88d8951e SW	454	if (!regs) {
	455	dev_err(&pdev->dev, "Couldn't ioremap regs\n");
	456	return -ENODEV;
	457	}
	458
4a3398ee	459	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	460	for (j = 0; j < 4; j++) {
3c92db9a EG	461	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	462	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	463	}
	464	}
	465
df221227	466	#ifdef CONFIG_OF_GPIO
88d8951e SW	467	tegra_gpio_chip.of_node = pdev->dev.of_node;
88d8951e SW	468	#endif
df221227	469
3c92db9a EG	470	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	471
3391811c	472	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	473	int irq = irq_create_mapping(irq_domain, gpio);
47008001	474	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	475
47008001	476	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	477
47008001 SW	478	irq_set_lockdep_class(irq, &gpio_lock_class);
	479	irq_set_chip_data(irq, bank);
	480	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	481	handle_simple_irq);
47008001	482	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	483	}
3c92db9a EG	484
3391811c	485	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	486	bank = &tegra_gpio_banks[i];
3c92db9a EG	487
6845664a TG	488	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	489	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	490
	491	for (j = 0; j < 4; j++)
	492	spin_lock_init(&bank->lvl_lock[j]);
	493	}
	494
	495	return 0;
	496	}
	497
88d8951e SW	498	static struct platform_driver tegra_gpio_driver = {
	499	.driver = {
	500	.name = "tegra-gpio",
	501	.owner = THIS_MODULE,
8939ddc7	502	.pm = &tegra_gpio_pm_ops,
88d8951e SW	503	.of_match_table = tegra_gpio_of_match,
	504	},
	505	.probe = tegra_gpio_probe,
	506	};
	507
	508	static int __init tegra_gpio_init(void)
	509	{
	510	return platform_driver_register(&tegra_gpio_driver);
	511	}
3c92db9a EG	512	postcore_initcall(tegra_gpio_init);
	513
	514	#ifdef CONFIG_DEBUG_FS
	515
	516	#include <linux/debugfs.h>
	517	#include <linux/seq_file.h>
	518
	519	static int dbg_gpio_show(struct seq_file s, void unused)
	520	{
	521	int i;
	522	int j;
	523
4a3398ee	524	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	525	for (j = 0; j < 4; j++) {
3c92db9a EG	526	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	527	seq_printf(s,
	528	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	529	i, j,
88d8951e SW	530	tegra_gpio_readl(GPIO_CNF(gpio)),
	531	tegra_gpio_readl(GPIO_OE(gpio)),
	532	tegra_gpio_readl(GPIO_OUT(gpio)),
	533	tegra_gpio_readl(GPIO_IN(gpio)),
	534	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	535	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	536	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	537	}
	538	}
	539	return 0;
	540	}
	541
	542	static int dbg_gpio_open(struct inode inode, struct file file)
	543	{
	544	return single_open(file, dbg_gpio_show, &inode->i_private);
	545	}
	546
	547	static const struct file_operations debug_fops = {
	548	.open = dbg_gpio_open,
	549	.read = seq_read,
	550	.llseek = seq_lseek,
	551	.release = single_release,
	552	};
	553
	554	static int __init tegra_gpio_debuginit(void)
	555	{
	556	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	557	NULL, NULL, &debug_fops);
	558	return 0;
	559	}
	560	late_initcall(tegra_gpio_debuginit);
	561	#endif