Commit | Line | Data |
---|---|---|
3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
2e47b8b3 | 22 | #include <linux/interrupt.h> |
3c92db9a EG |
23 | #include <linux/io.h> |
24 | #include <linux/gpio.h> | |
df221227 | 25 | #include <linux/of.h> |
88d8951e SW |
26 | #include <linux/platform_device.h> |
27 | #include <linux/module.h> | |
3c92db9a | 28 | |
98022940 WD |
29 | #include <asm/mach/irq.h> |
30 | ||
ea5abbd2 | 31 | #include <mach/gpio-tegra.h> |
3c92db9a | 32 | #include <mach/iomap.h> |
2ea67fd1 | 33 | #include <mach/suspend.h> |
3c92db9a EG |
34 | |
35 | #define GPIO_BANK(x) ((x) >> 5) | |
36 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
37 | #define GPIO_BIT(x) ((x) & 0x7) | |
38 | ||
88d8951e | 39 | #define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4) |
3c92db9a EG |
40 | |
41 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
42 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
43 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
44 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
45 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
46 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
47 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
48 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
49 | ||
50 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) | |
51 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) | |
52 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) | |
53 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) | |
54 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) | |
55 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) | |
56 | ||
57 | #define GPIO_INT_LVL_MASK 0x010101 | |
58 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
59 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
60 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
61 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
62 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
63 | ||
64 | struct tegra_gpio_bank { | |
65 | int bank; | |
66 | int irq; | |
67 | spinlock_t lvl_lock[4]; | |
2e47b8b3 CC |
68 | #ifdef CONFIG_PM |
69 | u32 cnf[4]; | |
70 | u32 out[4]; | |
71 | u32 oe[4]; | |
72 | u32 int_enb[4]; | |
73 | u32 int_lvl[4]; | |
74 | #endif | |
3c92db9a EG |
75 | }; |
76 | ||
77 | ||
88d8951e SW |
78 | static void __iomem *regs; |
79 | static struct tegra_gpio_bank tegra_gpio_banks[7]; | |
80 | ||
81 | static inline void tegra_gpio_writel(u32 val, u32 reg) | |
82 | { | |
83 | __raw_writel(val, regs + reg); | |
84 | } | |
85 | ||
86 | static inline u32 tegra_gpio_readl(u32 reg) | |
87 | { | |
88 | return __raw_readl(regs + reg); | |
89 | } | |
3c92db9a EG |
90 | |
91 | static int tegra_gpio_compose(int bank, int port, int bit) | |
92 | { | |
93 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
94 | } | |
95 | ||
96 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
97 | { | |
98 | u32 val; | |
99 | ||
100 | val = 0x100 << GPIO_BIT(gpio); | |
101 | if (value) | |
102 | val |= 1 << GPIO_BIT(gpio); | |
88d8951e | 103 | tegra_gpio_writel(val, reg); |
3c92db9a EG |
104 | } |
105 | ||
106 | void tegra_gpio_enable(int gpio) | |
107 | { | |
108 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
109 | } | |
110 | ||
111 | void tegra_gpio_disable(int gpio) | |
112 | { | |
113 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
114 | } | |
115 | ||
116 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
117 | { | |
118 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
119 | } | |
120 | ||
121 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
122 | { | |
88d8951e | 123 | return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
3c92db9a EG |
124 | } |
125 | ||
126 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
127 | { | |
128 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
129 | return 0; | |
130 | } | |
131 | ||
132 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
133 | int value) | |
134 | { | |
135 | tegra_gpio_set(chip, offset, value); | |
136 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
137 | return 0; | |
138 | } | |
139 | ||
438a99c0 SW |
140 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
141 | { | |
142 | return TEGRA_GPIO_TO_IRQ(offset); | |
143 | } | |
3c92db9a EG |
144 | |
145 | static struct gpio_chip tegra_gpio_chip = { | |
146 | .label = "tegra-gpio", | |
147 | .direction_input = tegra_gpio_direction_input, | |
148 | .get = tegra_gpio_get, | |
149 | .direction_output = tegra_gpio_direction_output, | |
150 | .set = tegra_gpio_set, | |
438a99c0 | 151 | .to_irq = tegra_gpio_to_irq, |
3c92db9a | 152 | .base = 0, |
2e47b8b3 | 153 | .ngpio = TEGRA_NR_GPIOS, |
3c92db9a EG |
154 | }; |
155 | ||
37337a8d | 156 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 157 | { |
37337a8d | 158 | int gpio = d->irq - INT_GPIO_BASE; |
3c92db9a | 159 | |
88d8951e | 160 | tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
3c92db9a EG |
161 | } |
162 | ||
37337a8d | 163 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 164 | { |
37337a8d | 165 | int gpio = d->irq - INT_GPIO_BASE; |
3c92db9a EG |
166 | |
167 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
168 | } | |
169 | ||
37337a8d | 170 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 171 | { |
37337a8d | 172 | int gpio = d->irq - INT_GPIO_BASE; |
3c92db9a EG |
173 | |
174 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
175 | } | |
176 | ||
37337a8d | 177 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 178 | { |
37337a8d LB |
179 | int gpio = d->irq - INT_GPIO_BASE; |
180 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
3c92db9a EG |
181 | int port = GPIO_PORT(gpio); |
182 | int lvl_type; | |
183 | int val; | |
184 | unsigned long flags; | |
185 | ||
186 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
187 | case IRQ_TYPE_EDGE_RISING: | |
188 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
189 | break; | |
190 | ||
191 | case IRQ_TYPE_EDGE_FALLING: | |
192 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
193 | break; | |
194 | ||
195 | case IRQ_TYPE_EDGE_BOTH: | |
196 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
197 | break; | |
198 | ||
199 | case IRQ_TYPE_LEVEL_HIGH: | |
200 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
201 | break; | |
202 | ||
203 | case IRQ_TYPE_LEVEL_LOW: | |
204 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
205 | break; | |
206 | ||
207 | default: | |
208 | return -EINVAL; | |
209 | } | |
210 | ||
211 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
212 | ||
88d8951e | 213 | val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
3c92db9a EG |
214 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
215 | val |= lvl_type << GPIO_BIT(gpio); | |
88d8951e | 216 | tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); |
3c92db9a EG |
217 | |
218 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
219 | ||
220 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 221 | __irq_set_handler_locked(d->irq, handle_level_irq); |
3c92db9a | 222 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 223 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
3c92db9a EG |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
228 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
229 | { | |
230 | struct tegra_gpio_bank *bank; | |
231 | int port; | |
232 | int pin; | |
233 | int unmasked = 0; | |
98022940 | 234 | struct irq_chip *chip = irq_desc_get_chip(desc); |
3c92db9a | 235 | |
98022940 | 236 | chained_irq_enter(chip, desc); |
3c92db9a | 237 | |
6845664a | 238 | bank = irq_get_handler_data(irq); |
3c92db9a EG |
239 | |
240 | for (port = 0; port < 4; port++) { | |
241 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
88d8951e SW |
242 | unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & |
243 | tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
244 | u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
3c92db9a EG |
245 | |
246 | for_each_set_bit(pin, &sta, 8) { | |
88d8951e | 247 | tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); |
3c92db9a EG |
248 | |
249 | /* if gpio is edge triggered, clear condition | |
250 | * before executing the hander so that we don't | |
251 | * miss edges | |
252 | */ | |
253 | if (lvl & (0x100 << pin)) { | |
254 | unmasked = 1; | |
98022940 | 255 | chained_irq_exit(chip, desc); |
3c92db9a EG |
256 | } |
257 | ||
258 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
259 | } | |
260 | } | |
261 | ||
262 | if (!unmasked) | |
98022940 | 263 | chained_irq_exit(chip, desc); |
3c92db9a EG |
264 | |
265 | } | |
266 | ||
2e47b8b3 CC |
267 | #ifdef CONFIG_PM |
268 | void tegra_gpio_resume(void) | |
269 | { | |
270 | unsigned long flags; | |
c8309ef6 CC |
271 | int b; |
272 | int p; | |
2e47b8b3 CC |
273 | |
274 | local_irq_save(flags); | |
275 | ||
276 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { | |
277 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; | |
278 | ||
279 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
280 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
281 | tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); |
282 | tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); | |
283 | tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); | |
284 | tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); | |
285 | tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); | |
2e47b8b3 CC |
286 | } |
287 | } | |
288 | ||
289 | local_irq_restore(flags); | |
2e47b8b3 CC |
290 | } |
291 | ||
292 | void tegra_gpio_suspend(void) | |
293 | { | |
294 | unsigned long flags; | |
c8309ef6 CC |
295 | int b; |
296 | int p; | |
2e47b8b3 | 297 | |
2e47b8b3 CC |
298 | local_irq_save(flags); |
299 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { | |
300 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; | |
301 | ||
302 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
303 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
304 | bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); |
305 | bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); | |
306 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); | |
307 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
308 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
2e47b8b3 CC |
309 | } |
310 | } | |
311 | local_irq_restore(flags); | |
312 | } | |
313 | ||
37337a8d | 314 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 315 | { |
37337a8d | 316 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
6845664a | 317 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
318 | } |
319 | #endif | |
3c92db9a EG |
320 | |
321 | static struct irq_chip tegra_gpio_irq_chip = { | |
322 | .name = "GPIO", | |
37337a8d LB |
323 | .irq_ack = tegra_gpio_irq_ack, |
324 | .irq_mask = tegra_gpio_irq_mask, | |
325 | .irq_unmask = tegra_gpio_irq_unmask, | |
326 | .irq_set_type = tegra_gpio_irq_set_type, | |
2e47b8b3 | 327 | #ifdef CONFIG_PM |
37337a8d | 328 | .irq_set_wake = tegra_gpio_wake_enable, |
2e47b8b3 | 329 | #endif |
3c92db9a EG |
330 | }; |
331 | ||
332 | ||
333 | /* This lock class tells lockdep that GPIO irqs are in a different | |
334 | * category than their parents, so it won't report false recursion. | |
335 | */ | |
336 | static struct lock_class_key gpio_lock_class; | |
337 | ||
88d8951e | 338 | static int __devinit tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 339 | { |
88d8951e | 340 | struct resource *res; |
3c92db9a | 341 | struct tegra_gpio_bank *bank; |
47008001 | 342 | int gpio; |
3c92db9a EG |
343 | int i; |
344 | int j; | |
345 | ||
88d8951e SW |
346 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { |
347 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); | |
348 | if (!res) { | |
349 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
350 | return -ENODEV; | |
351 | } | |
352 | ||
353 | bank = &tegra_gpio_banks[i]; | |
354 | bank->bank = i; | |
355 | bank->irq = res->start; | |
356 | } | |
357 | ||
358 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
359 | if (!res) { | |
360 | dev_err(&pdev->dev, "Missing MEM resource\n"); | |
361 | return -ENODEV; | |
362 | } | |
363 | ||
aedd4fdf | 364 | regs = devm_request_and_ioremap(&pdev->dev, res); |
88d8951e SW |
365 | if (!regs) { |
366 | dev_err(&pdev->dev, "Couldn't ioremap regs\n"); | |
367 | return -ENODEV; | |
368 | } | |
369 | ||
3c92db9a EG |
370 | for (i = 0; i < 7; i++) { |
371 | for (j = 0; j < 4; j++) { | |
372 | int gpio = tegra_gpio_compose(i, j, 0); | |
88d8951e | 373 | tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); |
3c92db9a EG |
374 | } |
375 | } | |
376 | ||
df221227 | 377 | #ifdef CONFIG_OF_GPIO |
88d8951e SW |
378 | tegra_gpio_chip.of_node = pdev->dev.of_node; |
379 | #endif | |
df221227 | 380 | |
3c92db9a EG |
381 | gpiochip_add(&tegra_gpio_chip); |
382 | ||
47008001 SW |
383 | for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) { |
384 | int irq = TEGRA_GPIO_TO_IRQ(gpio); | |
385 | /* No validity check; all Tegra GPIOs are valid IRQs */ | |
3c92db9a | 386 | |
47008001 | 387 | bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; |
3c92db9a | 388 | |
47008001 SW |
389 | irq_set_lockdep_class(irq, &gpio_lock_class); |
390 | irq_set_chip_data(irq, bank); | |
391 | irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, | |
f38c02f3 | 392 | handle_simple_irq); |
47008001 | 393 | set_irq_flags(irq, IRQF_VALID); |
3c92db9a EG |
394 | } |
395 | ||
396 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { | |
397 | bank = &tegra_gpio_banks[i]; | |
398 | ||
6845664a TG |
399 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
400 | irq_set_handler_data(bank->irq, bank); | |
3c92db9a EG |
401 | |
402 | for (j = 0; j < 4; j++) | |
403 | spin_lock_init(&bank->lvl_lock[j]); | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
88d8951e SW |
409 | static struct of_device_id tegra_gpio_of_match[] __devinitdata = { |
410 | { .compatible = "nvidia,tegra20-gpio", }, | |
411 | { }, | |
412 | }; | |
413 | ||
414 | static struct platform_driver tegra_gpio_driver = { | |
415 | .driver = { | |
416 | .name = "tegra-gpio", | |
417 | .owner = THIS_MODULE, | |
418 | .of_match_table = tegra_gpio_of_match, | |
419 | }, | |
420 | .probe = tegra_gpio_probe, | |
421 | }; | |
422 | ||
423 | static int __init tegra_gpio_init(void) | |
424 | { | |
425 | return platform_driver_register(&tegra_gpio_driver); | |
426 | } | |
3c92db9a EG |
427 | postcore_initcall(tegra_gpio_init); |
428 | ||
632095ea OJ |
429 | void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) |
430 | { | |
431 | int i; | |
432 | ||
433 | for (i = 0; i < num; i++) { | |
434 | int gpio = table[i].gpio; | |
435 | ||
436 | if (table[i].enable) | |
437 | tegra_gpio_enable(gpio); | |
438 | else | |
439 | tegra_gpio_disable(gpio); | |
440 | } | |
441 | } | |
442 | ||
3c92db9a EG |
443 | #ifdef CONFIG_DEBUG_FS |
444 | ||
445 | #include <linux/debugfs.h> | |
446 | #include <linux/seq_file.h> | |
447 | ||
448 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
449 | { | |
450 | int i; | |
451 | int j; | |
452 | ||
453 | for (i = 0; i < 7; i++) { | |
454 | for (j = 0; j < 4; j++) { | |
455 | int gpio = tegra_gpio_compose(i, j, 0); | |
2e47b8b3 CC |
456 | seq_printf(s, |
457 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
458 | i, j, | |
88d8951e SW |
459 | tegra_gpio_readl(GPIO_CNF(gpio)), |
460 | tegra_gpio_readl(GPIO_OE(gpio)), | |
461 | tegra_gpio_readl(GPIO_OUT(gpio)), | |
462 | tegra_gpio_readl(GPIO_IN(gpio)), | |
463 | tegra_gpio_readl(GPIO_INT_STA(gpio)), | |
464 | tegra_gpio_readl(GPIO_INT_ENB(gpio)), | |
465 | tegra_gpio_readl(GPIO_INT_LVL(gpio))); | |
3c92db9a EG |
466 | } |
467 | } | |
468 | return 0; | |
469 | } | |
470 | ||
471 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
472 | { | |
473 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
474 | } | |
475 | ||
476 | static const struct file_operations debug_fops = { | |
477 | .open = dbg_gpio_open, | |
478 | .read = seq_read, | |
479 | .llseek = seq_lseek, | |
480 | .release = single_release, | |
481 | }; | |
482 | ||
483 | static int __init tegra_gpio_debuginit(void) | |
484 | { | |
485 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
486 | NULL, NULL, &debug_fops); | |
487 | return 0; | |
488 | } | |
489 | late_initcall(tegra_gpio_debuginit); | |
490 | #endif |