[deliverable/linux.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#include <asm/mach/irq.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};

static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int __devinit tegra_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	if (match)
		config = (struct tegra_gpio_soc_config *)match->data;
	else
		config = &tegra20_gpio_config;

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks) {
		dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
		return -ENODEV;
	}

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Missing MEM resource\n");
		return -ENODEV;
	}

	regs = devm_request_and_ioremap(&pdev->dev, res);
	if (!regs) {
		dev_err(&pdev->dev, "Couldn't ioremap regs\n");
		return -ENODEV;
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	tegra_gpio_chip.of_node = pdev->dev.of_node;
#endif

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.owner	= THIS_MODULE,
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23	#include <linux/io.h>
3c92db9a EG	24	#include <linux/gpio.h>
5c1e2c9d	25	#include <linux/of_device.h>
88d8951e SW	26	#include <linux/platform_device.h>
88d8951e SW	27	#include <linux/module.h>
6f74dc9b	28	#include <linux/irqdomain.h>
3e215d0a	29	#include <linux/pinctrl/consumer.h>
8939ddc7	30	#include <linux/pm.h>
3c92db9a	31
98022940 WD	32	#include <asm/mach/irq.h>
98022940 WD	33
3c92db9a EG	34	#define GPIO_BANK(x) ((x) >> 5)
	35	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	36	#define GPIO_BIT(x) ((x) & 0x7)
	37
5c1e2c9d SW	38	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	39	GPIO_PORT(x) * 4)
3c92db9a EG	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
5c1e2c9d SW	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
8939ddc7	68	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
	74	#endif
3c92db9a EG	75	};
3c92db9a EG	76
bdc93a77	77	static struct irq_domain *irq_domain;
88d8951e	78	static void __iomem *regs;
3391811c	79	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	80	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	81	static u32 tegra_gpio_upper_offset;
3391811c	82	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	83
	84	static inline void tegra_gpio_writel(u32 val, u32 reg)
	85	{
	86	__raw_writel(val, regs + reg);
	87	}
	88
	89	static inline u32 tegra_gpio_readl(u32 reg)
	90	{
	91	return __raw_readl(regs + reg);
	92	}
3c92db9a EG	93
	94	static int tegra_gpio_compose(int bank, int port, int bit)
	95	{
	96	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	97	}
	98
	99	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	100	{
	101	u32 val;
	102
	103	val = 0x100 << GPIO_BIT(gpio);
	104	if (value)
	105	val \|= 1 << GPIO_BIT(gpio);
88d8951e	106	tegra_gpio_writel(val, reg);
3c92db9a EG	107	}
3c92db9a EG	108
3e215d0a	109	static void tegra_gpio_enable(int gpio)
3c92db9a EG	110	{
	111	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	112	}
	113
3e215d0a	114	static void tegra_gpio_disable(int gpio)
3c92db9a EG	115	{
	116	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	117	}
	118
924a0987	119	static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	120	{
	121	return pinctrl_request_gpio(offset);
	122	}
	123
924a0987	124	static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	125	{
	126	pinctrl_free_gpio(offset);
	127	tegra_gpio_disable(offset);
	128	}
	129
3c92db9a EG	130	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	131	{
	132	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	133	}
	134
	135	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	136	{
88d8951e	137	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	138	}
	139
	140	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	141	{
	142	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	143	tegra_gpio_enable(offset);
3c92db9a EG	144	return 0;
	145	}
	146
	147	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	148	int value)
	149	{
	150	tegra_gpio_set(chip, offset, value);
	151	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	152	tegra_gpio_enable(offset);
3c92db9a EG	153	return 0;
	154	}
	155
438a99c0 SW	156	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	157	{
bdc93a77	158	return irq_find_mapping(irq_domain, offset);
438a99c0	159	}
3c92db9a EG	160
	161	static struct gpio_chip tegra_gpio_chip = {
	162	.label = "tegra-gpio",
3e215d0a SW	163	.request = tegra_gpio_request,
3e215d0a SW	164	.free = tegra_gpio_free,
3c92db9a EG	165	.direction_input = tegra_gpio_direction_input,
	166	.get = tegra_gpio_get,
	167	.direction_output = tegra_gpio_direction_output,
	168	.set = tegra_gpio_set,
438a99c0	169	.to_irq = tegra_gpio_to_irq,
3c92db9a	170	.base = 0,
3c92db9a EG	171	};
3c92db9a EG	172
37337a8d	173	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	174	{
6f74dc9b	175	int gpio = d->hwirq;
3c92db9a	176
88d8951e	177	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	178	}
3c92db9a EG	179
37337a8d	180	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	181	{
6f74dc9b	182	int gpio = d->hwirq;
3c92db9a EG	183
	184	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	185	}
	186
37337a8d	187	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	188	{
6f74dc9b	189	int gpio = d->hwirq;
3c92db9a EG	190
	191	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	192	}
	193
37337a8d	194	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	195	{
6f74dc9b	196	int gpio = d->hwirq;
37337a8d	197	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	198	int port = GPIO_PORT(gpio);
	199	int lvl_type;
	200	int val;
	201	unsigned long flags;
	202
	203	switch (type & IRQ_TYPE_SENSE_MASK) {
	204	case IRQ_TYPE_EDGE_RISING:
	205	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	206	break;
	207
	208	case IRQ_TYPE_EDGE_FALLING:
	209	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	210	break;
	211
	212	case IRQ_TYPE_EDGE_BOTH:
	213	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	214	break;
	215
	216	case IRQ_TYPE_LEVEL_HIGH:
	217	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	218	break;
	219
	220	case IRQ_TYPE_LEVEL_LOW:
	221	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	222	break;
	223
	224	default:
	225	return -EINVAL;
	226	}
	227
	228	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	229
88d8951e	230	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	231	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	232	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	233	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	234
	235	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	236
d941136f SW	237	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	238	tegra_gpio_enable(gpio);
	239
3c92db9a	240	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	241	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	242	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	243	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	244
	245	return 0;
	246	}
	247
	248	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	249	{
	250	struct tegra_gpio_bank *bank;
	251	int port;
	252	int pin;
	253	int unmasked = 0;
98022940	254	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	255
98022940	256	chained_irq_enter(chip, desc);
3c92db9a	257
6845664a	258	bank = irq_get_handler_data(irq);
3c92db9a EG	259
	260	for (port = 0; port < 4; port++) {
	261	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	262	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	263	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	264	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	265
3c92db9a EG	266	for_each_set_bit(pin, &sta, 8) {
88d8951e	267	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	268
	269	/* if gpio is edge triggered, clear condition
	270	* before executing the hander so that we don't
	271	* miss edges
	272	*/
	273	if (lvl & (0x100 << pin)) {
	274	unmasked = 1;
98022940	275	chained_irq_exit(chip, desc);
3c92db9a EG	276	}
	277
	278	generic_handle_irq(gpio_to_irq(gpio + pin));
	279	}
	280	}
	281
	282	if (!unmasked)
98022940	283	chained_irq_exit(chip, desc);
3c92db9a EG	284
	285	}
	286
8939ddc7 LD	287	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	288	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	289	{
2e47b8b3 CC	290	unsigned long flags;
c8309ef6 CC	291	int b;
c8309ef6 CC	292	int p;
2e47b8b3 CC	293
	294	local_irq_save(flags);
	295
3391811c	296	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	297	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	298
	299	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	300	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	301	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	302	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	303	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	304	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	305	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	306	}
	307	}
	308
	309	local_irq_restore(flags);
8939ddc7	310	return 0;
2e47b8b3 CC	311	}
2e47b8b3 CC	312
8939ddc7	313	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	314	{
2e47b8b3 CC	315	unsigned long flags;
c8309ef6 CC	316	int b;
c8309ef6 CC	317	int p;
2e47b8b3	318
2e47b8b3	319	local_irq_save(flags);
3391811c	320	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	321	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	322
	323	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	324	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	325	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	326	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	327	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	328	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	329	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
2e47b8b3 CC	330	}
	331	}
	332	local_irq_restore(flags);
8939ddc7	333	return 0;
2e47b8b3 CC	334	}
2e47b8b3 CC	335
37337a8d	336	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	337	{
37337a8d	338	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	339	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	340	}
2e47b8b3 CC	341	#endif
3c92db9a EG	342
	343	static struct irq_chip tegra_gpio_irq_chip = {
	344	.name = "GPIO",
37337a8d LB	345	.irq_ack = tegra_gpio_irq_ack,
	346	.irq_mask = tegra_gpio_irq_mask,
	347	.irq_unmask = tegra_gpio_irq_unmask,
	348	.irq_set_type = tegra_gpio_irq_set_type,
8939ddc7	349	#ifdef CONFIG_PM_SLEEP
37337a8d	350	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	351	#endif
3c92db9a EG	352	};
3c92db9a EG	353
8939ddc7 LD	354	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	355	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	356	};
	357
5c1e2c9d SW	358	struct tegra_gpio_soc_config {
	359	u32 bank_stride;
	360	u32 upper_offset;
	361	};
	362
	363	static struct tegra_gpio_soc_config tegra20_gpio_config = {
	364	.bank_stride = 0x80,
	365	.upper_offset = 0x800,
	366	};
	367
	368	static struct tegra_gpio_soc_config tegra30_gpio_config = {
	369	.bank_stride = 0x100,
	370	.upper_offset = 0x80,
	371	};
	372
	373	static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	374	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	375	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	376	{ },
	377	};
3c92db9a EG	378
	379	/* This lock class tells lockdep that GPIO irqs are in a different
	380	* category than their parents, so it won't report false recursion.
	381	*/
	382	static struct lock_class_key gpio_lock_class;
	383
88d8951e	384	static int __devinit tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	385	{
5c1e2c9d SW	386	const struct of_device_id *match;
5c1e2c9d SW	387	struct tegra_gpio_soc_config *config;
88d8951e	388	struct resource *res;
3c92db9a	389	struct tegra_gpio_bank *bank;
47008001	390	int gpio;
3c92db9a EG	391	int i;
	392	int j;
	393
5c1e2c9d SW	394	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	395	if (match)
	396	config = (struct tegra_gpio_soc_config *)match->data;
	397	else
	398	config = &tegra20_gpio_config;
	399
	400	tegra_gpio_bank_stride = config->bank_stride;
	401	tegra_gpio_upper_offset = config->upper_offset;
	402
3391811c SW	403	for (;;) {
	404	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	405	if (!res)
	406	break;
	407	tegra_gpio_bank_count++;
	408	}
	409	if (!tegra_gpio_bank_count) {
	410	dev_err(&pdev->dev, "Missing IRQ resource\n");
	411	return -ENODEV;
	412	}
	413
	414	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	415
	416	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	417	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	418	GFP_KERNEL);
	419	if (!tegra_gpio_banks) {
	420	dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
	421	return -ENODEV;
	422	}
	423
d0235677 LW	424	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	425	tegra_gpio_chip.ngpio,
bdc93a77	426	&irq_domain_simple_ops, NULL);
d0235677 LW	427	if (!irq_domain)
d0235677 LW	428	return -ENODEV;
6f74dc9b	429
3391811c	430	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	431	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	432	if (!res) {
	433	dev_err(&pdev->dev, "Missing IRQ resource\n");
	434	return -ENODEV;
	435	}
	436
	437	bank = &tegra_gpio_banks[i];
	438	bank->bank = i;
	439	bank->irq = res->start;
	440	}
	441
	442	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	443	if (!res) {
	444	dev_err(&pdev->dev, "Missing MEM resource\n");
	445	return -ENODEV;
	446	}
	447
aedd4fdf	448	regs = devm_request_and_ioremap(&pdev->dev, res);
88d8951e SW	449	if (!regs) {
	450	dev_err(&pdev->dev, "Couldn't ioremap regs\n");
	451	return -ENODEV;
	452	}
	453
4a3398ee	454	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	455	for (j = 0; j < 4; j++) {
3c92db9a EG	456	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	457	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	458	}
	459	}
	460
df221227	461	#ifdef CONFIG_OF_GPIO
88d8951e SW	462	tegra_gpio_chip.of_node = pdev->dev.of_node;
88d8951e SW	463	#endif
df221227	464
3c92db9a EG	465	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	466
3391811c	467	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	468	int irq = irq_create_mapping(irq_domain, gpio);
47008001	469	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	470
47008001	471	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	472
47008001 SW	473	irq_set_lockdep_class(irq, &gpio_lock_class);
	474	irq_set_chip_data(irq, bank);
	475	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	476	handle_simple_irq);
47008001	477	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	478	}
3c92db9a EG	479
3391811c	480	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	481	bank = &tegra_gpio_banks[i];
3c92db9a EG	482
6845664a TG	483	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	484	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	485
	486	for (j = 0; j < 4; j++)
	487	spin_lock_init(&bank->lvl_lock[j]);
	488	}
	489
	490	return 0;
	491	}
	492
88d8951e SW	493	static struct platform_driver tegra_gpio_driver = {
	494	.driver = {
	495	.name = "tegra-gpio",
	496	.owner = THIS_MODULE,
8939ddc7	497	.pm = &tegra_gpio_pm_ops,
88d8951e SW	498	.of_match_table = tegra_gpio_of_match,
	499	},
	500	.probe = tegra_gpio_probe,
	501	};
	502
	503	static int __init tegra_gpio_init(void)
	504	{
	505	return platform_driver_register(&tegra_gpio_driver);
	506	}
3c92db9a EG	507	postcore_initcall(tegra_gpio_init);
	508
	509	#ifdef CONFIG_DEBUG_FS
	510
	511	#include <linux/debugfs.h>
	512	#include <linux/seq_file.h>
	513
	514	static int dbg_gpio_show(struct seq_file s, void unused)
	515	{
	516	int i;
	517	int j;
	518
4a3398ee	519	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	520	for (j = 0; j < 4; j++) {
3c92db9a EG	521	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	522	seq_printf(s,
	523	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	524	i, j,
88d8951e SW	525	tegra_gpio_readl(GPIO_CNF(gpio)),
	526	tegra_gpio_readl(GPIO_OE(gpio)),
	527	tegra_gpio_readl(GPIO_OUT(gpio)),
	528	tegra_gpio_readl(GPIO_IN(gpio)),
	529	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	530	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	531	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	532	}
	533	}
	534	return 0;
	535	}
	536
	537	static int dbg_gpio_open(struct inode inode, struct file file)
	538	{
	539	return single_open(file, dbg_gpio_show, &inode->i_private);
	540	}
	541
	542	static const struct file_operations debug_fops = {
	543	.open = dbg_gpio_open,
	544	.read = seq_read,
	545	.llseek = seq_lseek,
	546	.release = single_release,
	547	};
	548
	549	static int __init tegra_gpio_debuginit(void)
	550	{
	551	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	552	NULL, NULL, &debug_fops);
	553	return 0;
	554	}
	555	late_initcall(tegra_gpio_debuginit);
	556	#endif