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9caf1f22 JH |
1 | /* |
2 | * Toumaz Xenif TZ1090 GPIO handling. | |
3 | * | |
4 | * Copyright (C) 2008-2013 Imagination Technologies Ltd. | |
5 | * | |
6 | * Based on ARM PXA code and others. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/bitops.h> | |
14 | #include <linux/export.h> | |
15 | #include <linux/gpio.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/irqdomain.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/pinctrl/consumer.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/syscore_ops.h> | |
26 | #include <asm/global_lock.h> | |
27 | ||
28 | /* Register offsets from bank base address */ | |
29 | #define REG_GPIO_DIR 0x00 | |
30 | #define REG_GPIO_IRQ_PLRT 0x20 | |
31 | #define REG_GPIO_IRQ_TYPE 0x30 | |
32 | #define REG_GPIO_IRQ_EN 0x40 | |
33 | #define REG_GPIO_IRQ_STS 0x50 | |
34 | #define REG_GPIO_BIT_EN 0x60 | |
35 | #define REG_GPIO_DIN 0x70 | |
36 | #define REG_GPIO_DOUT 0x80 | |
37 | ||
38 | /* REG_GPIO_IRQ_PLRT */ | |
39 | #define REG_GPIO_IRQ_PLRT_LOW 0 | |
40 | #define REG_GPIO_IRQ_PLRT_HIGH 1 | |
41 | ||
42 | /* REG_GPIO_IRQ_TYPE */ | |
43 | #define REG_GPIO_IRQ_TYPE_LEVEL 0 | |
44 | #define REG_GPIO_IRQ_TYPE_EDGE 1 | |
45 | ||
46 | /** | |
47 | * struct tz1090_gpio_bank - GPIO bank private data | |
48 | * @chip: Generic GPIO chip for GPIO bank | |
49 | * @domain: IRQ domain for GPIO bank (may be NULL) | |
50 | * @reg: Base of registers, offset for this GPIO bank | |
51 | * @irq: IRQ number for GPIO bank | |
52 | * @label: Debug GPIO bank label, used for storage of chip->label | |
53 | * | |
54 | * This is the main private data for a GPIO bank. It encapsulates a gpio_chip, | |
55 | * and the callbacks for the gpio_chip can access the private data with the | |
56 | * to_bank() macro below. | |
57 | */ | |
58 | struct tz1090_gpio_bank { | |
59 | struct gpio_chip chip; | |
60 | struct irq_domain *domain; | |
61 | void __iomem *reg; | |
62 | int irq; | |
63 | char label[16]; | |
64 | }; | |
65 | #define to_bank(c) container_of(c, struct tz1090_gpio_bank, chip) | |
66 | ||
67 | /** | |
68 | * struct tz1090_gpio - Overall GPIO device private data | |
69 | * @dev: Device (from platform device) | |
70 | * @reg: Base of GPIO registers | |
71 | * | |
72 | * Represents the overall GPIO device. This structure is actually only | |
73 | * temporary, and used during init. | |
74 | */ | |
75 | struct tz1090_gpio { | |
76 | struct device *dev; | |
77 | void __iomem *reg; | |
78 | }; | |
79 | ||
80 | /** | |
81 | * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank | |
82 | * @priv: Overall GPIO device private data | |
83 | * @node: Device tree node specific to this GPIO bank | |
84 | * @index: Index of bank in range 0-2 | |
85 | */ | |
86 | struct tz1090_gpio_bank_info { | |
87 | struct tz1090_gpio *priv; | |
88 | struct device_node *node; | |
89 | unsigned int index; | |
90 | }; | |
91 | ||
92 | /* Convenience register accessors */ | |
93 | static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank, | |
94 | unsigned int reg_offs, u32 data) | |
95 | { | |
96 | iowrite32(data, bank->reg + reg_offs); | |
97 | } | |
98 | ||
99 | static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank, | |
100 | unsigned int reg_offs) | |
101 | { | |
102 | return ioread32(bank->reg + reg_offs); | |
103 | } | |
104 | ||
105 | /* caller must hold LOCK2 */ | |
106 | static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, | |
107 | unsigned int reg_offs, | |
108 | unsigned int offset) | |
109 | { | |
110 | u32 value; | |
111 | ||
112 | value = tz1090_gpio_read(bank, reg_offs); | |
113 | value &= ~BIT(offset); | |
114 | tz1090_gpio_write(bank, reg_offs, value); | |
115 | } | |
116 | ||
117 | static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, | |
118 | unsigned int reg_offs, | |
119 | unsigned int offset) | |
120 | { | |
121 | int lstat; | |
122 | ||
123 | __global_lock2(lstat); | |
124 | _tz1090_gpio_clear_bit(bank, reg_offs, offset); | |
125 | __global_unlock2(lstat); | |
126 | } | |
127 | ||
128 | /* caller must hold LOCK2 */ | |
129 | static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, | |
130 | unsigned int reg_offs, | |
131 | unsigned int offset) | |
132 | { | |
133 | u32 value; | |
134 | ||
135 | value = tz1090_gpio_read(bank, reg_offs); | |
136 | value |= BIT(offset); | |
137 | tz1090_gpio_write(bank, reg_offs, value); | |
138 | } | |
139 | ||
140 | static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, | |
141 | unsigned int reg_offs, | |
142 | unsigned int offset) | |
143 | { | |
144 | int lstat; | |
145 | ||
146 | __global_lock2(lstat); | |
147 | _tz1090_gpio_set_bit(bank, reg_offs, offset); | |
148 | __global_unlock2(lstat); | |
149 | } | |
150 | ||
151 | /* caller must hold LOCK2 */ | |
152 | static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, | |
153 | unsigned int reg_offs, | |
154 | unsigned int offset, | |
155 | bool val) | |
156 | { | |
157 | u32 value; | |
158 | ||
159 | value = tz1090_gpio_read(bank, reg_offs); | |
160 | value &= ~BIT(offset); | |
161 | if (val) | |
162 | value |= BIT(offset); | |
163 | tz1090_gpio_write(bank, reg_offs, value); | |
164 | } | |
165 | ||
166 | static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, | |
167 | unsigned int reg_offs, | |
168 | unsigned int offset, | |
169 | bool val) | |
170 | { | |
171 | int lstat; | |
172 | ||
173 | __global_lock2(lstat); | |
174 | _tz1090_gpio_mod_bit(bank, reg_offs, offset, val); | |
175 | __global_unlock2(lstat); | |
176 | } | |
177 | ||
178 | static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank, | |
179 | unsigned int reg_offs, | |
180 | unsigned int offset) | |
181 | { | |
182 | return tz1090_gpio_read(bank, reg_offs) & BIT(offset); | |
183 | } | |
184 | ||
185 | /* GPIO chip callbacks */ | |
186 | ||
187 | static int tz1090_gpio_direction_input(struct gpio_chip *chip, | |
188 | unsigned int offset) | |
189 | { | |
190 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
191 | tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static int tz1090_gpio_direction_output(struct gpio_chip *chip, | |
197 | unsigned int offset, int output_value) | |
198 | { | |
199 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
200 | int lstat; | |
201 | ||
202 | __global_lock2(lstat); | |
203 | _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); | |
204 | _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset); | |
205 | __global_unlock2(lstat); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Return GPIO level | |
212 | */ | |
213 | static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
214 | { | |
215 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
216 | ||
217 | return tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset); | |
218 | } | |
219 | ||
220 | /* | |
221 | * Set output GPIO level | |
222 | */ | |
223 | static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
224 | int output_value) | |
225 | { | |
226 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
227 | ||
228 | tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); | |
229 | } | |
230 | ||
231 | static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset) | |
232 | { | |
233 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
234 | int ret; | |
235 | ||
236 | ret = pinctrl_request_gpio(chip->base + offset); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
240 | tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); | |
241 | tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
247 | { | |
248 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
249 | ||
250 | pinctrl_free_gpio(chip->base + offset); | |
251 | ||
252 | tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset); | |
253 | } | |
254 | ||
255 | static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) | |
256 | { | |
257 | struct tz1090_gpio_bank *bank = to_bank(chip); | |
258 | ||
259 | if (!bank->domain) | |
260 | return -EINVAL; | |
261 | ||
262 | return irq_create_mapping(bank->domain, offset); | |
263 | } | |
264 | ||
265 | /* IRQ chip handlers */ | |
266 | ||
267 | /* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */ | |
268 | static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data) | |
269 | { | |
270 | return (struct tz1090_gpio_bank *)data->domain->host_data; | |
271 | } | |
272 | ||
273 | static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank, | |
274 | unsigned int offset) | |
275 | { | |
276 | tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset); | |
277 | } | |
278 | ||
279 | static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank, | |
280 | unsigned int offset, bool enable) | |
281 | { | |
282 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable); | |
283 | } | |
284 | ||
285 | static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank, | |
286 | unsigned int offset, unsigned int polarity) | |
287 | { | |
288 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity); | |
289 | } | |
290 | ||
291 | static int tz1090_gpio_valid_handler(struct irq_desc *desc) | |
292 | { | |
293 | return desc->handle_irq == handle_level_irq || | |
294 | desc->handle_irq == handle_edge_irq; | |
295 | } | |
296 | ||
297 | static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank, | |
298 | unsigned int offset, unsigned int type) | |
299 | { | |
300 | tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type); | |
301 | } | |
302 | ||
303 | /* set polarity to trigger on next edge, whether rising or falling */ | |
304 | static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank, | |
305 | unsigned int offset) | |
306 | { | |
307 | unsigned int value_p, value_i; | |
308 | int lstat; | |
309 | ||
310 | /* | |
311 | * Set the GPIO's interrupt polarity to the opposite of the current | |
312 | * input value so that the next edge triggers an interrupt. | |
313 | */ | |
314 | __global_lock2(lstat); | |
315 | value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN); | |
316 | value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT); | |
317 | value_p &= ~BIT(offset); | |
318 | value_p |= value_i & BIT(offset); | |
319 | tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p); | |
320 | __global_unlock2(lstat); | |
321 | } | |
322 | ||
323 | static void gpio_ack_irq(struct irq_data *data) | |
324 | { | |
325 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
326 | ||
327 | tz1090_gpio_irq_clear(bank, data->hwirq); | |
328 | } | |
329 | ||
330 | static void gpio_mask_irq(struct irq_data *data) | |
331 | { | |
332 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
333 | ||
334 | tz1090_gpio_irq_enable(bank, data->hwirq, false); | |
335 | } | |
336 | ||
337 | static void gpio_unmask_irq(struct irq_data *data) | |
338 | { | |
339 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
340 | ||
341 | tz1090_gpio_irq_enable(bank, data->hwirq, true); | |
342 | } | |
343 | ||
344 | static unsigned int gpio_startup_irq(struct irq_data *data) | |
345 | { | |
346 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
347 | irq_hw_number_t hw = data->hwirq; | |
348 | struct irq_desc *desc = irq_to_desc(data->irq); | |
349 | ||
350 | /* | |
351 | * This warning indicates that the type of the irq hasn't been set | |
352 | * before enabling the irq. This would normally be done by passing some | |
353 | * trigger flags to request_irq(). | |
354 | */ | |
355 | WARN(!tz1090_gpio_valid_handler(desc), | |
356 | "irq type not set before enabling gpio irq %d", data->irq); | |
357 | ||
358 | tz1090_gpio_irq_clear(bank, hw); | |
359 | tz1090_gpio_irq_enable(bank, hw, true); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type) | |
364 | { | |
365 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
366 | unsigned int type; | |
367 | unsigned int polarity; | |
368 | ||
369 | switch (flow_type) { | |
370 | case IRQ_TYPE_EDGE_BOTH: | |
371 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
372 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
373 | break; | |
374 | case IRQ_TYPE_EDGE_RISING: | |
375 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
376 | polarity = REG_GPIO_IRQ_PLRT_HIGH; | |
377 | break; | |
378 | case IRQ_TYPE_EDGE_FALLING: | |
379 | type = REG_GPIO_IRQ_TYPE_EDGE; | |
380 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
381 | break; | |
382 | case IRQ_TYPE_LEVEL_HIGH: | |
383 | type = REG_GPIO_IRQ_TYPE_LEVEL; | |
384 | polarity = REG_GPIO_IRQ_PLRT_HIGH; | |
385 | break; | |
386 | case IRQ_TYPE_LEVEL_LOW: | |
387 | type = REG_GPIO_IRQ_TYPE_LEVEL; | |
388 | polarity = REG_GPIO_IRQ_PLRT_LOW; | |
389 | break; | |
390 | default: | |
391 | return -EINVAL; | |
392 | } | |
393 | ||
394 | tz1090_gpio_irq_type(bank, data->hwirq, type); | |
395 | if (type == REG_GPIO_IRQ_TYPE_LEVEL) | |
396 | __irq_set_handler_locked(data->irq, handle_level_irq); | |
397 | else | |
398 | __irq_set_handler_locked(data->irq, handle_edge_irq); | |
399 | ||
400 | if (flow_type == IRQ_TYPE_EDGE_BOTH) | |
401 | tz1090_gpio_irq_next_edge(bank, data->hwirq); | |
402 | else | |
403 | tz1090_gpio_irq_polarity(bank, data->hwirq, polarity); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | #ifdef CONFIG_SUSPEND | |
409 | static int gpio_set_irq_wake(struct irq_data *data, unsigned int on) | |
410 | { | |
411 | struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); | |
412 | ||
413 | #ifdef CONFIG_PM_DEBUG | |
414 | pr_info("irq_wake irq%d state:%d\n", data->irq, on); | |
415 | #endif | |
416 | ||
417 | /* wake on gpio block interrupt */ | |
418 | return irq_set_irq_wake(bank->irq, on); | |
419 | } | |
420 | #else | |
421 | #define gpio_set_irq_wake NULL | |
422 | #endif | |
423 | ||
424 | /* gpio virtual interrupt functions */ | |
425 | static struct irq_chip gpio_irq_chip = { | |
426 | .irq_startup = gpio_startup_irq, | |
427 | .irq_ack = gpio_ack_irq, | |
428 | .irq_mask = gpio_mask_irq, | |
429 | .irq_unmask = gpio_unmask_irq, | |
430 | .irq_set_type = gpio_set_irq_type, | |
431 | .irq_set_wake = gpio_set_irq_wake, | |
432 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
433 | }; | |
434 | ||
435 | static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
436 | { | |
437 | irq_hw_number_t hw; | |
438 | unsigned int irq_stat, irq_no; | |
439 | struct tz1090_gpio_bank *bank; | |
440 | struct irq_desc *child_desc; | |
441 | ||
442 | bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc); | |
443 | irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) & | |
444 | tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) & | |
445 | tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) & | |
446 | 0x3FFFFFFF; /* 30 bits only */ | |
447 | ||
448 | for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) { | |
449 | if (!(irq_stat & 1)) | |
450 | continue; | |
451 | ||
452 | irq_no = irq_linear_revmap(bank->domain, hw); | |
453 | child_desc = irq_to_desc(irq_no); | |
454 | ||
455 | /* Toggle edge for pin with both edges triggering enabled */ | |
456 | if (irqd_get_trigger_type(&child_desc->irq_data) | |
457 | == IRQ_TYPE_EDGE_BOTH) | |
458 | tz1090_gpio_irq_next_edge(bank, hw); | |
459 | ||
460 | BUG_ON(!tz1090_gpio_valid_handler(child_desc)); | |
461 | generic_handle_irq_desc(irq_no, child_desc); | |
462 | } | |
463 | } | |
464 | ||
465 | static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
466 | irq_hw_number_t hw) | |
467 | { | |
468 | irq_set_chip(irq, &gpio_irq_chip); | |
469 | return 0; | |
470 | } | |
471 | ||
472 | static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = { | |
473 | .map = tz1090_gpio_irq_map, | |
474 | .xlate = irq_domain_xlate_twocell, | |
475 | }; | |
476 | ||
477 | static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) | |
478 | { | |
479 | struct device_node *np = info->node; | |
480 | struct device *dev = info->priv->dev; | |
481 | struct tz1090_gpio_bank *bank; | |
482 | ||
483 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); | |
484 | if (!bank) { | |
485 | dev_err(dev, "unable to allocate driver data\n"); | |
486 | return -ENOMEM; | |
487 | } | |
488 | ||
489 | /* Offset the main registers to the first register in this bank */ | |
490 | bank->reg = info->priv->reg + info->index * 4; | |
491 | ||
492 | /* Set up GPIO chip */ | |
493 | snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u", | |
494 | info->index); | |
495 | bank->chip.label = bank->label; | |
496 | bank->chip.dev = dev; | |
497 | bank->chip.direction_input = tz1090_gpio_direction_input; | |
498 | bank->chip.direction_output = tz1090_gpio_direction_output; | |
499 | bank->chip.get = tz1090_gpio_get; | |
500 | bank->chip.set = tz1090_gpio_set; | |
501 | bank->chip.free = tz1090_gpio_free; | |
502 | bank->chip.request = tz1090_gpio_request; | |
503 | bank->chip.to_irq = tz1090_gpio_to_irq; | |
504 | bank->chip.of_node = np; | |
505 | ||
506 | /* GPIO numbering from 0 */ | |
507 | bank->chip.base = info->index * 30; | |
508 | bank->chip.ngpio = 30; | |
509 | ||
510 | /* Add the GPIO bank */ | |
511 | gpiochip_add(&bank->chip); | |
512 | ||
513 | /* Get the GPIO bank IRQ if provided */ | |
514 | bank->irq = irq_of_parse_and_map(np, 0); | |
515 | ||
516 | /* The interrupt is optional (it may be used by another core on chip) */ | |
517 | if (bank->irq < 0) { | |
518 | dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n", | |
519 | info->index); | |
520 | return 0; | |
521 | } | |
522 | ||
523 | dev_info(dev, "Setting up IRQs for GPIO bank %u\n", | |
524 | info->index); | |
525 | ||
526 | /* | |
527 | * Initialise all interrupts to disabled so we don't get | |
528 | * spurious ones on a dirty boot and hit the BUG_ON in the | |
529 | * handler. | |
530 | */ | |
531 | tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0); | |
532 | ||
533 | /* Add a virtual IRQ for each GPIO */ | |
534 | bank->domain = irq_domain_add_linear(np, | |
535 | bank->chip.ngpio, | |
536 | &tz1090_gpio_irq_domain_ops, | |
537 | bank); | |
538 | ||
539 | /* Setup chained handler for this GPIO bank */ | |
540 | irq_set_handler_data(bank->irq, bank); | |
541 | irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static void tz1090_gpio_register_banks(struct tz1090_gpio *priv) | |
547 | { | |
548 | struct device_node *np = priv->dev->of_node; | |
549 | struct device_node *node; | |
550 | ||
551 | for_each_available_child_of_node(np, node) { | |
552 | struct tz1090_gpio_bank_info info; | |
553 | u32 addr; | |
554 | int ret; | |
555 | ||
556 | ret = of_property_read_u32(node, "reg", &addr); | |
557 | if (ret) { | |
558 | dev_err(priv->dev, "invalid reg on %s\n", | |
559 | node->full_name); | |
560 | continue; | |
561 | } | |
562 | if (addr >= 3) { | |
563 | dev_err(priv->dev, "index %u in %s out of range\n", | |
564 | addr, node->full_name); | |
565 | continue; | |
566 | } | |
567 | ||
568 | info.index = addr; | |
569 | info.node = of_node_get(node); | |
570 | info.priv = priv; | |
571 | ||
572 | ret = tz1090_gpio_bank_probe(&info); | |
573 | if (ret) { | |
574 | dev_err(priv->dev, "failure registering %s\n", | |
575 | node->full_name); | |
576 | of_node_put(node); | |
577 | continue; | |
578 | } | |
579 | } | |
580 | } | |
581 | ||
582 | static int tz1090_gpio_probe(struct platform_device *pdev) | |
583 | { | |
584 | struct device_node *np = pdev->dev.of_node; | |
585 | struct resource *res_regs; | |
586 | struct tz1090_gpio priv; | |
587 | ||
588 | if (!np) { | |
589 | dev_err(&pdev->dev, "must be instantiated via devicetree\n"); | |
590 | return -ENOENT; | |
591 | } | |
592 | ||
593 | res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
594 | if (!res_regs) { | |
595 | dev_err(&pdev->dev, "cannot find registers resource\n"); | |
596 | return -ENOENT; | |
597 | } | |
598 | ||
599 | priv.dev = &pdev->dev; | |
600 | ||
601 | /* Ioremap the registers */ | |
602 | priv.reg = devm_ioremap(&pdev->dev, res_regs->start, | |
603 | res_regs->end - res_regs->start); | |
604 | if (!priv.reg) { | |
605 | dev_err(&pdev->dev, "unable to ioremap registers\n"); | |
606 | return -ENOMEM; | |
607 | } | |
608 | ||
609 | /* Look for banks */ | |
610 | tz1090_gpio_register_banks(&priv); | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | static struct of_device_id tz1090_gpio_of_match[] = { | |
616 | { .compatible = "img,tz1090-gpio" }, | |
617 | { }, | |
618 | }; | |
619 | ||
620 | static struct platform_driver tz1090_gpio_driver = { | |
621 | .driver = { | |
622 | .name = "tz1090-gpio", | |
623 | .owner = THIS_MODULE, | |
624 | .of_match_table = tz1090_gpio_of_match, | |
625 | }, | |
626 | .probe = tz1090_gpio_probe, | |
627 | }; | |
628 | ||
629 | static int __init tz1090_gpio_init(void) | |
630 | { | |
631 | return platform_driver_register(&tz1090_gpio_driver); | |
632 | } | |
633 | subsys_initcall(tz1090_gpio_init); |