[deliverable/linux.git] / drivers / gpio / gpio-xlp.c

/*
 * Copyright (C) 2003-2015 Broadcom Corporation
 * All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/interrupt.h>

/*
 * XLP GPIO has multiple 32 bit registers for each feature where each register
 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
 * require 3 32-bit registers for each feature.
 * Here we only define offset of the first register for each feature. Offset of
 * the registers for pins greater than 32 can be calculated as following(Use
 * GPIO_INT_STAT as example):
 *
 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
 * reg_addr = addr + offset;
 *
 * where addr is base address of the that feature register and gpio is the pin.
 */
#define GPIO_OUTPUT_EN		0x00
#define GPIO_PADDRV		0x08
#define GPIO_INT_EN00		0x18
#define GPIO_INT_EN10		0x20
#define GPIO_INT_EN20		0x28
#define GPIO_INT_EN30		0x30
#define GPIO_INT_POL		0x38
#define GPIO_INT_TYPE		0x40
#define GPIO_INT_STAT		0x48

#define GPIO_9XX_BYTESWAP	0X00
#define GPIO_9XX_CTRL		0X04
#define GPIO_9XX_OUTPUT_EN	0x14
#define GPIO_9XX_PADDRV		0x24
/*
 * Only for 4 interrupt enable reg are defined for now,
 * total reg available are 12.
 */
#define GPIO_9XX_INT_EN00	0x44
#define GPIO_9XX_INT_EN10	0x54
#define GPIO_9XX_INT_EN20	0x64
#define GPIO_9XX_INT_EN30	0x74
#define GPIO_9XX_INT_POL	0x104
#define GPIO_9XX_INT_TYPE	0x114
#define GPIO_9XX_INT_STAT	0x124

#define GPIO_3XX_INT_EN00	0x18
#define GPIO_3XX_INT_EN10	0x20
#define GPIO_3XX_INT_EN20	0x28
#define GPIO_3XX_INT_EN30	0x30
#define GPIO_3XX_INT_POL	0x78
#define GPIO_3XX_INT_TYPE	0x80
#define GPIO_3XX_INT_STAT	0x88

/* Interrupt type register mask */
#define XLP_GPIO_IRQ_TYPE_LVL	0x0
#define XLP_GPIO_IRQ_TYPE_EDGE	0x1

/* Interrupt polarity register mask */
#define XLP_GPIO_IRQ_POL_HIGH	0x0
#define XLP_GPIO_IRQ_POL_LOW	0x1

#define XLP_GPIO_REGSZ		32
#define XLP_GPIO_IRQ_BASE	768
#define XLP_MAX_NR_GPIO		96

/* XLP variants supported by this driver */
enum {
	XLP_GPIO_VARIANT_XLP832 = 1,
	XLP_GPIO_VARIANT_XLP316,
	XLP_GPIO_VARIANT_XLP208,
	XLP_GPIO_VARIANT_XLP980,
	XLP_GPIO_VARIANT_XLP532
};

struct xlp_gpio_priv {
	struct gpio_chip chip;
	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
	void __iomem *gpio_intr_en;	/* pointer to first intr enable reg */
	void __iomem *gpio_intr_stat;	/* pointer to first intr status reg */
	void __iomem *gpio_intr_type;	/* pointer to first intr type reg */
	void __iomem *gpio_intr_pol;	/* pointer to first intr polarity reg */
	void __iomem *gpio_out_en;	/* pointer to first output enable reg */
	void __iomem *gpio_paddrv;	/* pointer to first pad drive reg */
	spinlock_t lock;
};

static struct xlp_gpio_priv *gpio_chip_to_xlp_priv(struct gpio_chip *gc)
{
	return container_of(gc, struct xlp_gpio_priv, chip);
}

static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
{
	u32 pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	return !!(readl(addr + regset) & BIT(pos));
}

static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
{
	u32 value, pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	value = readl(addr + regset);

	if (state)
		value |= BIT(pos);
	else
		value &= ~BIT(pos);

	writel(value, addr + regset);
}

static void xlp_gpio_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void xlp_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void xlp_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
	__set_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
	int pol, irq_type;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	default:
		return -EINVAL;
	}

	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);

	return 0;
}

static struct irq_chip xlp_gpio_irq_chip = {
	.name		= "XLP-GPIO",
	.irq_mask_ack	= xlp_gpio_irq_mask_ack,
	.irq_disable	= xlp_gpio_irq_disable,
	.irq_set_type	= xlp_gpio_set_irq_type,
	.irq_unmask	= xlp_gpio_irq_unmask,
	.flags		= IRQCHIP_ONESHOT_SAFE,
};

static irqreturn_t xlp_gpio_generic_handler(int irq, void *data)
{
	struct xlp_gpio_priv *priv = data;
	int gpio, regoff;
	u32 gpio_stat;

	regoff = -1;
	gpio_stat = 0;
	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
		if (regoff != gpio / XLP_GPIO_REGSZ) {
			regoff = gpio / XLP_GPIO_REGSZ;
			gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
		}
		if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
			generic_handle_irq(irq_find_mapping(
						priv->chip.irqdomain, gpio));
	}

	return IRQ_HANDLED;
}

static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);

	return 0;
}

static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);

	return 0;
}

static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);

	BUG_ON(gpio >= gc->ngpio);
	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
}

static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
}

static const struct of_device_id xlp_gpio_of_ids[] = {
	{
		.compatible = "netlogic,xlp832-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP832,
	},
	{
		.compatible = "netlogic,xlp316-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP316,
	},
	{
		.compatible = "netlogic,xlp208-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP208,
	},
	{
		.compatible = "netlogic,xlp980-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP980,
	},
	{
		.compatible = "netlogic,xlp532-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP532,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);

static int xlp_gpio_probe(struct platform_device *pdev)
{
	struct gpio_chip *gc;
	struct resource *iores;
	struct xlp_gpio_priv *priv;
	const struct of_device_id *of_id;
	void __iomem *gpio_base;
	int irq_base, irq, err;
	int ngpio;
	u32 soc_type;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores)
		return -ENODEV;

	priv = devm_kzalloc(&pdev->dev,	sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	gpio_base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(gpio_base))
		return PTR_ERR(gpio_base);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
	if (!of_id) {
		dev_err(&pdev->dev, "Failed to get soc type!\n");
		return -ENODEV;
	}

	soc_type = (uintptr_t) of_id->data;

	switch (soc_type) {
	case XLP_GPIO_VARIANT_XLP832:
		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
		ngpio = 41;
		break;
	case XLP_GPIO_VARIANT_XLP208:
	case XLP_GPIO_VARIANT_XLP316:
		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;

		ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
		break;
	case XLP_GPIO_VARIANT_XLP980:
	case XLP_GPIO_VARIANT_XLP532:
		priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;

		ngpio = (soc_type == XLP_GPIO_VARIANT_XLP980) ? 66 : 67;
		break;
	default:
		dev_err(&pdev->dev, "Unknown Processor type!\n");
		return -ENODEV;
	}

	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);

	gc = &priv->chip;

	gc->owner = THIS_MODULE;
	gc->label = dev_name(&pdev->dev);
	gc->base = 0;
	gc->dev = &pdev->dev;
	gc->ngpio = ngpio;
	gc->of_node = pdev->dev.of_node;
	gc->direction_output = xlp_gpio_dir_output;
	gc->direction_input = xlp_gpio_dir_input;
	gc->set = xlp_gpio_set;
	gc->get = xlp_gpio_get;

	spin_lock_init(&priv->lock);

	err = devm_request_irq(&pdev->dev, irq, xlp_gpio_generic_handler,
			IRQ_TYPE_NONE, pdev->name, priv);
	if (err)
		return err;

	irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
	if (irq_base < 0) {
		dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
		return err;
	}

	err = gpiochip_add(gc);
	if (err < 0)
		goto out_free_desc;

	err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
				handle_level_irq, IRQ_TYPE_NONE);
	if (err) {
		dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
		goto out_gpio_remove;
	}

	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);

	return 0;

out_gpio_remove:
	gpiochip_remove(gc);
out_free_desc:
	irq_free_descs(irq_base, gc->ngpio);
	return err;
}

static struct platform_driver xlp_gpio_driver = {
	.driver		= {
		.name	= "xlp-gpio",
		.of_match_table = xlp_gpio_of_ids,
	},
	.probe		= xlp_gpio_probe,
};
module_platform_driver(xlp_gpio_driver);

MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ff718800 KP	1	/*
	2	* Copyright (C) 2003-2015 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/gpio.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/of_device.h>
	18	#include <linux/module.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
	21
	22	/*
	23	* XLP GPIO has multiple 32 bit registers for each feature where each register
	24	* controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
	25	* require 3 32-bit registers for each feature.
	26	* Here we only define offset of the first register for each feature. Offset of
	27	* the registers for pins greater than 32 can be calculated as following(Use
	28	* GPIO_INT_STAT as example):
	29	*
	30	* offset = (gpio / XLP_GPIO_REGSZ) * 4;
	31	* reg_addr = addr + offset;
	32	*
	33	* where addr is base address of the that feature register and gpio is the pin.
	34	*/
	35	#define GPIO_OUTPUT_EN 0x00
	36	#define GPIO_PADDRV 0x08
	37	#define GPIO_INT_EN00 0x18
	38	#define GPIO_INT_EN10 0x20
	39	#define GPIO_INT_EN20 0x28
	40	#define GPIO_INT_EN30 0x30
	41	#define GPIO_INT_POL 0x38
	42	#define GPIO_INT_TYPE 0x40
	43	#define GPIO_INT_STAT 0x48
	44
	45	#define GPIO_9XX_BYTESWAP 0X00
	46	#define GPIO_9XX_CTRL 0X04
	47	#define GPIO_9XX_OUTPUT_EN 0x14
	48	#define GPIO_9XX_PADDRV 0x24
	49	/*
	50	* Only for 4 interrupt enable reg are defined for now,
	51	* total reg available are 12.
	52	*/
	53	#define GPIO_9XX_INT_EN00 0x44
	54	#define GPIO_9XX_INT_EN10 0x54
	55	#define GPIO_9XX_INT_EN20 0x64
	56	#define GPIO_9XX_INT_EN30 0x74
	57	#define GPIO_9XX_INT_POL 0x104
	58	#define GPIO_9XX_INT_TYPE 0x114
	59	#define GPIO_9XX_INT_STAT 0x124
	60
	61	#define GPIO_3XX_INT_EN00 0x18
	62	#define GPIO_3XX_INT_EN10 0x20
	63	#define GPIO_3XX_INT_EN20 0x28
	64	#define GPIO_3XX_INT_EN30 0x30
65	#define GPIO_3XX_INT_POL 0x78
66	#define GPIO_3XX_INT_TYPE 0x80
67	#define GPIO_3XX_INT_STAT 0x88
68
69	/* Interrupt type register mask */
70	#define XLP_GPIO_IRQ_TYPE_LVL 0x0
71	#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
72
73	/* Interrupt polarity register mask */
74	#define XLP_GPIO_IRQ_POL_HIGH 0x0
75	#define XLP_GPIO_IRQ_POL_LOW 0x1
76
77	#define XLP_GPIO_REGSZ 32
78	#define XLP_GPIO_IRQ_BASE 768
79	#define XLP_MAX_NR_GPIO 96
80
81	/* XLP variants supported by this driver */
82	enum {
83	XLP_GPIO_VARIANT_XLP832 = 1,
84	XLP_GPIO_VARIANT_XLP316,
85	XLP_GPIO_VARIANT_XLP208,
86	XLP_GPIO_VARIANT_XLP980,
87	XLP_GPIO_VARIANT_XLP532
88	};
89
90	struct xlp_gpio_priv {
91	struct gpio_chip chip;
92	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
93	void __iomem gpio_intr_en; / pointer to first intr enable reg */
94	void __iomem gpio_intr_stat; / pointer to first intr status reg */
95	void __iomem gpio_intr_type; / pointer to first intr type reg */
96	void __iomem gpio_intr_pol; / pointer to first intr polarity reg */
97	void __iomem gpio_out_en; / pointer to first output enable reg */
98	void __iomem gpio_paddrv; / pointer to first pad drive reg */
99	spinlock_t lock;
100	};
101
102	static struct xlp_gpio_priv gpio_chip_to_xlp_priv(struct gpio_chip gc)
103	{
104	return container_of(gc, struct xlp_gpio_priv, chip);
105	}
106
107	static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
108	{
109	u32 pos, regset;
110
111	pos = gpio % XLP_GPIO_REGSZ;
112	regset = (gpio / XLP_GPIO_REGSZ) * 4;
113	return !!(readl(addr + regset) & BIT(pos));
114	}
115
116	static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
117	{
118	u32 value, pos, regset;
119
120	pos = gpio % XLP_GPIO_REGSZ;
121	regset = (gpio / XLP_GPIO_REGSZ) * 4;
122	value = readl(addr + regset);
123
124	if (state)
125	value \|= BIT(pos);
126	else
127	value &= ~BIT(pos);
128
129	writel(value, addr + regset);
130	}
131
132	static void xlp_gpio_irq_disable(struct irq_data *d)
133	{
134	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
135	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
136	unsigned long flags;
137
138	spin_lock_irqsave(&priv->lock, flags);
139	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
140	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
141	spin_unlock_irqrestore(&priv->lock, flags);
142	}
143
144	static void xlp_gpio_irq_mask_ack(struct irq_data *d)
145	{
146	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
147	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
148	unsigned long flags;
149
150	spin_lock_irqsave(&priv->lock, flags);
151	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
152	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
153	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
154	spin_unlock_irqrestore(&priv->lock, flags);
155	}
156
157	static void xlp_gpio_irq_unmask(struct irq_data *d)
158	{
159	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
161	unsigned long flags;
162
163	spin_lock_irqsave(&priv->lock, flags);
164	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
165	__set_bit(d->hwirq, priv->gpio_enabled_mask);
166	spin_unlock_irqrestore(&priv->lock, flags);
167	}
168
169	static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
170	{
171	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
173	int pol, irq_type;
174
175	switch (type) {
176	case IRQ_TYPE_EDGE_RISING:
177	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
178	pol = XLP_GPIO_IRQ_POL_HIGH;
179	break;
180	case IRQ_TYPE_EDGE_FALLING:
181	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
182	pol = XLP_GPIO_IRQ_POL_LOW;
183	break;
184	case IRQ_TYPE_LEVEL_HIGH:
185	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
186	pol = XLP_GPIO_IRQ_POL_HIGH;
187	break;
188	case IRQ_TYPE_LEVEL_LOW:
189	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
190	pol = XLP_GPIO_IRQ_POL_LOW;
191	break;
192	default:
193	return -EINVAL;
194	}
195
196	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
197	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
198
199	return 0;
200	}
201
202	static struct irq_chip xlp_gpio_irq_chip = {
203	.name = "XLP-GPIO",
204	.irq_mask_ack = xlp_gpio_irq_mask_ack,
205	.irq_disable = xlp_gpio_irq_disable,
206	.irq_set_type = xlp_gpio_set_irq_type,
207	.irq_unmask = xlp_gpio_irq_unmask,
208	.flags = IRQCHIP_ONESHOT_SAFE,
209	};
210
211	static irqreturn_t xlp_gpio_generic_handler(int irq, void *data)
212	{
213	struct xlp_gpio_priv *priv = data;
214	int gpio, regoff;
215	u32 gpio_stat;
216
217	regoff = -1;
218	gpio_stat = 0;
219	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
220	if (regoff != gpio / XLP_GPIO_REGSZ) {
221	regoff = gpio / XLP_GPIO_REGSZ;
222	gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
223	}
224	if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
225	generic_handle_irq(irq_find_mapping(
226	priv->chip.irqdomain, gpio));
227	}
228
229	return IRQ_HANDLED;
230	}
231
232	static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
233	{
234	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
235
236	BUG_ON(gpio >= gc->ngpio);
237	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
238
239	return 0;
240	}
241
242	static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
243	{
244	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
245
246	BUG_ON(gpio >= gc->ngpio);
247	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
248
249	return 0;
250	}
251
252	static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
253	{
254	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
255
256	BUG_ON(gpio >= gc->ngpio);
257	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
258	}
259
260	static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
261	{
262	struct xlp_gpio_priv *priv = gpio_chip_to_xlp_priv(gc);
263
264	BUG_ON(gpio >= gc->ngpio);
265	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
266	}
267
268	static const struct of_device_id xlp_gpio_of_ids[] = {
269	{
270	.compatible = "netlogic,xlp832-gpio",
271	.data = (void *)XLP_GPIO_VARIANT_XLP832,
272	},
273	{
274	.compatible = "netlogic,xlp316-gpio",
275	.data = (void *)XLP_GPIO_VARIANT_XLP316,
276	},
277	{
278	.compatible = "netlogic,xlp208-gpio",
279	.data = (void *)XLP_GPIO_VARIANT_XLP208,
280	},
281	{
282	.compatible = "netlogic,xlp980-gpio",
283	.data = (void *)XLP_GPIO_VARIANT_XLP980,
284	},
285	{
286	.compatible = "netlogic,xlp532-gpio",
287	.data = (void *)XLP_GPIO_VARIANT_XLP532,
288	},
289	{ /* sentinel */ },
290	};
291	MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
292
293	static int xlp_gpio_probe(struct platform_device *pdev)
294	{
295	struct gpio_chip *gc;
296	struct resource *iores;
297	struct xlp_gpio_priv *priv;
298	const struct of_device_id *of_id;
299	void __iomem *gpio_base;
300	int irq_base, irq, err;
301	int ngpio;
302	u32 soc_type;
303
304	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
305	if (!iores)
306	return -ENODEV;
307
308	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
309	if (!priv)
310	return -ENOMEM;
311
312	gpio_base = devm_ioremap_resource(&pdev->dev, iores);
313	if (IS_ERR(gpio_base))
314	return PTR_ERR(gpio_base);
315
316	irq = platform_get_irq(pdev, 0);
317	if (irq < 0)
318	return irq;
319
320	of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
321	if (!of_id) {
322	dev_err(&pdev->dev, "Failed to get soc type!\n");
323	return -ENODEV;
324	}
325
326	soc_type = (uintptr_t) of_id->data;
327
328	switch (soc_type) {
329	case XLP_GPIO_VARIANT_XLP832:
330	priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
331	priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
332	priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
333	priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
334	priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
335	priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
336	ngpio = 41;
337	break;
338	case XLP_GPIO_VARIANT_XLP208:
339	case XLP_GPIO_VARIANT_XLP316:
340	priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
341	priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
342	priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
343	priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
344	priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
345	priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
346
347	ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
348	break;
349	case XLP_GPIO_VARIANT_XLP980:
350	case XLP_GPIO_VARIANT_XLP532:
351	priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
352	priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
353	priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
354	priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
355	priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
356	priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
357
358	ngpio = (soc_type == XLP_GPIO_VARIANT_XLP980) ? 66 : 67;
359	break;
360	default:
361	dev_err(&pdev->dev, "Unknown Processor type!\n");
362	return -ENODEV;
363	}
364
365	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
366
367	gc = &priv->chip;
368
b8a3f52e AL	369	gc->owner = THIS_MODULE;
b8a3f52e AL	370	gc->label = dev_name(&pdev->dev);
ff718800 KP	371	gc->base = 0;
	372	gc->dev = &pdev->dev;
	373	gc->ngpio = ngpio;
	374	gc->of_node = pdev->dev.of_node;
	375	gc->direction_output = xlp_gpio_dir_output;
	376	gc->direction_input = xlp_gpio_dir_input;
	377	gc->set = xlp_gpio_set;
	378	gc->get = xlp_gpio_get;
	379
	380	spin_lock_init(&priv->lock);
	381
	382	err = devm_request_irq(&pdev->dev, irq, xlp_gpio_generic_handler,
	383	IRQ_TYPE_NONE, pdev->name, priv);
	384	if (err)
	385	return err;
	386
	387	irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
	388	if (irq_base < 0) {
	389	dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
	390	return err;
	391	}
	392
	393	err = gpiochip_add(gc);
	394	if (err < 0)
	395	goto out_free_desc;
	396
	397	err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
	398	handle_level_irq, IRQ_TYPE_NONE);
	399	if (err) {
	400	dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
	401	goto out_gpio_remove;
	402	}
	403
	404	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
	405
	406	return 0;
	407
	408	out_gpio_remove:
	409	gpiochip_remove(gc);
	410	out_free_desc:
	411	irq_free_descs(irq_base, gc->ngpio);
	412	return err;
	413	}
	414
	415	static struct platform_driver xlp_gpio_driver = {
	416	.driver = {
	417	.name = "xlp-gpio",
	418	.of_match_table = xlp_gpio_of_ids,
	419	},
	420	.probe = xlp_gpio_probe,
	421	};
	422	module_platform_driver(xlp_gpio_driver);
	423
	424	MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
	425	MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
	426	MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
	427	MODULE_LICENSE("GPL v2");