Commit | Line | Data |
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35570ac6 RR |
1 | /* |
2 | * timbgpio.c timberdale FPGA GPIO driver | |
3 | * Copyright (c) 2009 Intel Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | /* Supports: | |
20 | * Timberdale FPGA GPIO | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/platform_device.h> | |
e46dccff | 26 | #include <linux/mfd/core.h> |
e3cb91ce | 27 | #include <linux/irq.h> |
35570ac6 RR |
28 | #include <linux/io.h> |
29 | #include <linux/timb_gpio.h> | |
30 | #include <linux/interrupt.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
35570ac6 RR |
32 | |
33 | #define DRIVER_NAME "timb-gpio" | |
34 | ||
35 | #define TGPIOVAL 0x00 | |
36 | #define TGPIODIR 0x04 | |
37 | #define TGPIO_IER 0x08 | |
38 | #define TGPIO_ISR 0x0c | |
39 | #define TGPIO_IPR 0x10 | |
40 | #define TGPIO_ICR 0x14 | |
41 | #define TGPIO_FLR 0x18 | |
42 | #define TGPIO_LVR 0x1c | |
8c35c89a RR |
43 | #define TGPIO_VER 0x20 |
44 | #define TGPIO_BFLR 0x24 | |
35570ac6 RR |
45 | |
46 | struct timbgpio { | |
47 | void __iomem *membase; | |
48 | spinlock_t lock; /* mutual exclusion */ | |
49 | struct gpio_chip gpio; | |
50 | int irq_base; | |
76d800a5 | 51 | unsigned long last_ier; |
35570ac6 RR |
52 | }; |
53 | ||
54 | static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, | |
55 | unsigned offset, bool enabled) | |
56 | { | |
57 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
58 | u32 reg; | |
59 | ||
60 | spin_lock(&tgpio->lock); | |
61 | reg = ioread32(tgpio->membase + offset); | |
62 | ||
63 | if (enabled) | |
64 | reg |= (1 << index); | |
65 | else | |
66 | reg &= ~(1 << index); | |
67 | ||
68 | iowrite32(reg, tgpio->membase + offset); | |
69 | spin_unlock(&tgpio->lock); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
74 | static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |
75 | { | |
76 | return timbgpio_update_bit(gpio, nr, TGPIODIR, true); | |
77 | } | |
78 | ||
79 | static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) | |
80 | { | |
81 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
82 | u32 value; | |
83 | ||
84 | value = ioread32(tgpio->membase + TGPIOVAL); | |
85 | return (value & (1 << nr)) ? 1 : 0; | |
86 | } | |
87 | ||
88 | static int timbgpio_gpio_direction_output(struct gpio_chip *gpio, | |
89 | unsigned nr, int val) | |
90 | { | |
91 | return timbgpio_update_bit(gpio, nr, TGPIODIR, false); | |
92 | } | |
93 | ||
94 | static void timbgpio_gpio_set(struct gpio_chip *gpio, | |
95 | unsigned nr, int val) | |
96 | { | |
97 | timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); | |
98 | } | |
99 | ||
100 | static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) | |
101 | { | |
102 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
103 | ||
104 | if (tgpio->irq_base <= 0) | |
105 | return -EINVAL; | |
106 | ||
107 | return tgpio->irq_base + offset; | |
108 | } | |
109 | ||
110 | /* | |
111 | * GPIO IRQ | |
112 | */ | |
a1f5f22a | 113 | static void timbgpio_irq_disable(struct irq_data *d) |
35570ac6 | 114 | { |
a1f5f22a LB |
115 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
116 | int offset = d->irq - tgpio->irq_base; | |
76d800a5 | 117 | unsigned long flags; |
35570ac6 | 118 | |
76d800a5 TH |
119 | spin_lock_irqsave(&tgpio->lock, flags); |
120 | tgpio->last_ier &= ~(1 << offset); | |
121 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); | |
122 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
35570ac6 RR |
123 | } |
124 | ||
a1f5f22a | 125 | static void timbgpio_irq_enable(struct irq_data *d) |
35570ac6 | 126 | { |
a1f5f22a LB |
127 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
128 | int offset = d->irq - tgpio->irq_base; | |
76d800a5 | 129 | unsigned long flags; |
35570ac6 | 130 | |
76d800a5 TH |
131 | spin_lock_irqsave(&tgpio->lock, flags); |
132 | tgpio->last_ier |= 1 << offset; | |
133 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); | |
134 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
35570ac6 RR |
135 | } |
136 | ||
a1f5f22a | 137 | static int timbgpio_irq_type(struct irq_data *d, unsigned trigger) |
35570ac6 | 138 | { |
a1f5f22a LB |
139 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
140 | int offset = d->irq - tgpio->irq_base; | |
35570ac6 | 141 | unsigned long flags; |
8c35c89a RR |
142 | u32 lvr, flr, bflr = 0; |
143 | u32 ver; | |
2a481800 | 144 | int ret = 0; |
35570ac6 RR |
145 | |
146 | if (offset < 0 || offset > tgpio->gpio.ngpio) | |
147 | return -EINVAL; | |
148 | ||
8c35c89a RR |
149 | ver = ioread32(tgpio->membase + TGPIO_VER); |
150 | ||
35570ac6 RR |
151 | spin_lock_irqsave(&tgpio->lock, flags); |
152 | ||
153 | lvr = ioread32(tgpio->membase + TGPIO_LVR); | |
154 | flr = ioread32(tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
155 | if (ver > 2) |
156 | bflr = ioread32(tgpio->membase + TGPIO_BFLR); | |
35570ac6 RR |
157 | |
158 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
8c35c89a | 159 | bflr &= ~(1 << offset); |
35570ac6 RR |
160 | flr &= ~(1 << offset); |
161 | if (trigger & IRQ_TYPE_LEVEL_HIGH) | |
162 | lvr |= 1 << offset; | |
163 | else | |
164 | lvr &= ~(1 << offset); | |
165 | } | |
166 | ||
8c35c89a | 167 | if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
2a481800 JL |
168 | if (ver < 3) { |
169 | ret = -EINVAL; | |
170 | goto out; | |
171 | } | |
8c35c89a RR |
172 | else { |
173 | flr |= 1 << offset; | |
174 | bflr |= 1 << offset; | |
175 | } | |
176 | } else { | |
177 | bflr &= ~(1 << offset); | |
35570ac6 | 178 | flr |= 1 << offset; |
35570ac6 | 179 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
35570ac6 | 180 | lvr &= ~(1 << offset); |
8c35c89a RR |
181 | else |
182 | lvr |= 1 << offset; | |
35570ac6 RR |
183 | } |
184 | ||
185 | iowrite32(lvr, tgpio->membase + TGPIO_LVR); | |
186 | iowrite32(flr, tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
187 | if (ver > 2) |
188 | iowrite32(bflr, tgpio->membase + TGPIO_BFLR); | |
189 | ||
35570ac6 | 190 | iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); |
35570ac6 | 191 | |
2a481800 JL |
192 | out: |
193 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
194 | return ret; | |
35570ac6 RR |
195 | } |
196 | ||
7f5db6a8 | 197 | static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) |
35570ac6 | 198 | { |
b51804bc | 199 | struct timbgpio *tgpio = irq_get_handler_data(irq); |
35570ac6 RR |
200 | unsigned long ipr; |
201 | int offset; | |
202 | ||
7f5db6a8 | 203 | desc->irq_data.chip->irq_ack(irq_get_irq_data(irq)); |
35570ac6 RR |
204 | ipr = ioread32(tgpio->membase + TGPIO_IPR); |
205 | iowrite32(ipr, tgpio->membase + TGPIO_ICR); | |
206 | ||
76d800a5 TH |
207 | /* |
208 | * Some versions of the hardware trash the IER register if more than | |
209 | * one interrupt is received simultaneously. | |
210 | */ | |
211 | iowrite32(0, tgpio->membase + TGPIO_IER); | |
212 | ||
984b3f57 | 213 | for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) |
35570ac6 | 214 | generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); |
76d800a5 TH |
215 | |
216 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); | |
35570ac6 RR |
217 | } |
218 | ||
219 | static struct irq_chip timbgpio_irqchip = { | |
220 | .name = "GPIO", | |
a1f5f22a LB |
221 | .irq_enable = timbgpio_irq_enable, |
222 | .irq_disable = timbgpio_irq_disable, | |
223 | .irq_set_type = timbgpio_irq_type, | |
35570ac6 RR |
224 | }; |
225 | ||
226 | static int __devinit timbgpio_probe(struct platform_device *pdev) | |
227 | { | |
228 | int err, i; | |
229 | struct gpio_chip *gc; | |
230 | struct timbgpio *tgpio; | |
231 | struct resource *iomem; | |
e46dccff | 232 | struct timbgpio_platform_data *pdata = mfd_get_data(pdev); |
35570ac6 RR |
233 | int irq = platform_get_irq(pdev, 0); |
234 | ||
235 | if (!pdata || pdata->nr_pins > 32) { | |
236 | err = -EINVAL; | |
237 | goto err_mem; | |
238 | } | |
239 | ||
240 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
241 | if (!iomem) { | |
242 | err = -EINVAL; | |
243 | goto err_mem; | |
244 | } | |
245 | ||
246 | tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL); | |
247 | if (!tgpio) { | |
248 | err = -EINVAL; | |
249 | goto err_mem; | |
250 | } | |
251 | tgpio->irq_base = pdata->irq_base; | |
252 | ||
253 | spin_lock_init(&tgpio->lock); | |
254 | ||
255 | if (!request_mem_region(iomem->start, resource_size(iomem), | |
256 | DRIVER_NAME)) { | |
257 | err = -EBUSY; | |
258 | goto err_request; | |
259 | } | |
260 | ||
261 | tgpio->membase = ioremap(iomem->start, resource_size(iomem)); | |
262 | if (!tgpio->membase) { | |
263 | err = -ENOMEM; | |
264 | goto err_ioremap; | |
265 | } | |
266 | ||
267 | gc = &tgpio->gpio; | |
268 | ||
269 | gc->label = dev_name(&pdev->dev); | |
270 | gc->owner = THIS_MODULE; | |
271 | gc->dev = &pdev->dev; | |
272 | gc->direction_input = timbgpio_gpio_direction_input; | |
273 | gc->get = timbgpio_gpio_get; | |
274 | gc->direction_output = timbgpio_gpio_direction_output; | |
275 | gc->set = timbgpio_gpio_set; | |
276 | gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL; | |
277 | gc->dbg_show = NULL; | |
278 | gc->base = pdata->gpio_base; | |
279 | gc->ngpio = pdata->nr_pins; | |
280 | gc->can_sleep = 0; | |
281 | ||
282 | err = gpiochip_add(gc); | |
283 | if (err) | |
284 | goto err_chipadd; | |
285 | ||
286 | platform_set_drvdata(pdev, tgpio); | |
287 | ||
288 | /* make sure to disable interrupts */ | |
289 | iowrite32(0x0, tgpio->membase + TGPIO_IER); | |
290 | ||
291 | if (irq < 0 || tgpio->irq_base <= 0) | |
292 | return 0; | |
293 | ||
294 | for (i = 0; i < pdata->nr_pins; i++) { | |
b51804bc | 295 | irq_set_chip_and_handler_name(tgpio->irq_base + i, |
35570ac6 | 296 | &timbgpio_irqchip, handle_simple_irq, "mux"); |
b51804bc | 297 | irq_set_chip_data(tgpio->irq_base + i, tgpio); |
35570ac6 RR |
298 | #ifdef CONFIG_ARM |
299 | set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE); | |
300 | #endif | |
301 | } | |
302 | ||
b51804bc TG |
303 | irq_set_handler_data(irq, tgpio); |
304 | irq_set_chained_handler(irq, timbgpio_irq); | |
35570ac6 RR |
305 | |
306 | return 0; | |
307 | ||
308 | err_chipadd: | |
309 | iounmap(tgpio->membase); | |
310 | err_ioremap: | |
311 | release_mem_region(iomem->start, resource_size(iomem)); | |
312 | err_request: | |
313 | kfree(tgpio); | |
314 | err_mem: | |
315 | printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err); | |
316 | ||
317 | return err; | |
318 | } | |
319 | ||
320 | static int __devexit timbgpio_remove(struct platform_device *pdev) | |
321 | { | |
322 | int err; | |
35570ac6 RR |
323 | struct timbgpio *tgpio = platform_get_drvdata(pdev); |
324 | struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
325 | int irq = platform_get_irq(pdev, 0); | |
326 | ||
327 | if (irq >= 0 && tgpio->irq_base > 0) { | |
328 | int i; | |
e46dccff | 329 | for (i = 0; i < tgpio->gpio.ngpio; i++) { |
b51804bc TG |
330 | irq_set_chip(tgpio->irq_base + i, NULL); |
331 | irq_set_chip_data(tgpio->irq_base + i, NULL); | |
35570ac6 RR |
332 | } |
333 | ||
b51804bc TG |
334 | irq_set_handler(irq, NULL); |
335 | irq_set_handler_data(irq, NULL); | |
35570ac6 RR |
336 | } |
337 | ||
338 | err = gpiochip_remove(&tgpio->gpio); | |
339 | if (err) | |
340 | printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n"); | |
341 | ||
342 | iounmap(tgpio->membase); | |
343 | release_mem_region(iomem->start, resource_size(iomem)); | |
344 | kfree(tgpio); | |
345 | ||
346 | platform_set_drvdata(pdev, NULL); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static struct platform_driver timbgpio_platform_driver = { | |
352 | .driver = { | |
353 | .name = DRIVER_NAME, | |
354 | .owner = THIS_MODULE, | |
355 | }, | |
356 | .probe = timbgpio_probe, | |
357 | .remove = timbgpio_remove, | |
358 | }; | |
359 | ||
360 | /*--------------------------------------------------------------------------*/ | |
361 | ||
362 | static int __init timbgpio_init(void) | |
363 | { | |
364 | return platform_driver_register(&timbgpio_platform_driver); | |
365 | } | |
366 | ||
367 | static void __exit timbgpio_exit(void) | |
368 | { | |
369 | platform_driver_unregister(&timbgpio_platform_driver); | |
370 | } | |
371 | ||
372 | module_init(timbgpio_init); | |
373 | module_exit(timbgpio_exit); | |
374 | ||
375 | MODULE_DESCRIPTION("Timberdale GPIO driver"); | |
376 | MODULE_LICENSE("GPL v2"); | |
377 | MODULE_AUTHOR("Mocean Laboratories"); | |
378 | MODULE_ALIAS("platform:"DRIVER_NAME); | |
379 |