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35570ac6 RR |
1 | /* |
2 | * timbgpio.c timberdale FPGA GPIO driver | |
3 | * Copyright (c) 2009 Intel Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | /* Supports: | |
20 | * Timberdale FPGA GPIO | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/platform_device.h> | |
e3cb91ce | 26 | #include <linux/irq.h> |
35570ac6 RR |
27 | #include <linux/io.h> |
28 | #include <linux/timb_gpio.h> | |
29 | #include <linux/interrupt.h> | |
30 | ||
31 | #define DRIVER_NAME "timb-gpio" | |
32 | ||
33 | #define TGPIOVAL 0x00 | |
34 | #define TGPIODIR 0x04 | |
35 | #define TGPIO_IER 0x08 | |
36 | #define TGPIO_ISR 0x0c | |
37 | #define TGPIO_IPR 0x10 | |
38 | #define TGPIO_ICR 0x14 | |
39 | #define TGPIO_FLR 0x18 | |
40 | #define TGPIO_LVR 0x1c | |
8c35c89a RR |
41 | #define TGPIO_VER 0x20 |
42 | #define TGPIO_BFLR 0x24 | |
35570ac6 RR |
43 | |
44 | struct timbgpio { | |
45 | void __iomem *membase; | |
46 | spinlock_t lock; /* mutual exclusion */ | |
47 | struct gpio_chip gpio; | |
48 | int irq_base; | |
49 | }; | |
50 | ||
51 | static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, | |
52 | unsigned offset, bool enabled) | |
53 | { | |
54 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
55 | u32 reg; | |
56 | ||
57 | spin_lock(&tgpio->lock); | |
58 | reg = ioread32(tgpio->membase + offset); | |
59 | ||
60 | if (enabled) | |
61 | reg |= (1 << index); | |
62 | else | |
63 | reg &= ~(1 << index); | |
64 | ||
65 | iowrite32(reg, tgpio->membase + offset); | |
66 | spin_unlock(&tgpio->lock); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |
72 | { | |
73 | return timbgpio_update_bit(gpio, nr, TGPIODIR, true); | |
74 | } | |
75 | ||
76 | static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) | |
77 | { | |
78 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
79 | u32 value; | |
80 | ||
81 | value = ioread32(tgpio->membase + TGPIOVAL); | |
82 | return (value & (1 << nr)) ? 1 : 0; | |
83 | } | |
84 | ||
85 | static int timbgpio_gpio_direction_output(struct gpio_chip *gpio, | |
86 | unsigned nr, int val) | |
87 | { | |
88 | return timbgpio_update_bit(gpio, nr, TGPIODIR, false); | |
89 | } | |
90 | ||
91 | static void timbgpio_gpio_set(struct gpio_chip *gpio, | |
92 | unsigned nr, int val) | |
93 | { | |
94 | timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); | |
95 | } | |
96 | ||
97 | static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) | |
98 | { | |
99 | struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); | |
100 | ||
101 | if (tgpio->irq_base <= 0) | |
102 | return -EINVAL; | |
103 | ||
104 | return tgpio->irq_base + offset; | |
105 | } | |
106 | ||
107 | /* | |
108 | * GPIO IRQ | |
109 | */ | |
110 | static void timbgpio_irq_disable(unsigned irq) | |
111 | { | |
112 | struct timbgpio *tgpio = get_irq_chip_data(irq); | |
113 | int offset = irq - tgpio->irq_base; | |
114 | ||
115 | timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0); | |
116 | } | |
117 | ||
118 | static void timbgpio_irq_enable(unsigned irq) | |
119 | { | |
120 | struct timbgpio *tgpio = get_irq_chip_data(irq); | |
121 | int offset = irq - tgpio->irq_base; | |
122 | ||
123 | timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1); | |
124 | } | |
125 | ||
126 | static int timbgpio_irq_type(unsigned irq, unsigned trigger) | |
127 | { | |
128 | struct timbgpio *tgpio = get_irq_chip_data(irq); | |
129 | int offset = irq - tgpio->irq_base; | |
130 | unsigned long flags; | |
8c35c89a RR |
131 | u32 lvr, flr, bflr = 0; |
132 | u32 ver; | |
35570ac6 RR |
133 | |
134 | if (offset < 0 || offset > tgpio->gpio.ngpio) | |
135 | return -EINVAL; | |
136 | ||
8c35c89a RR |
137 | ver = ioread32(tgpio->membase + TGPIO_VER); |
138 | ||
35570ac6 RR |
139 | spin_lock_irqsave(&tgpio->lock, flags); |
140 | ||
141 | lvr = ioread32(tgpio->membase + TGPIO_LVR); | |
142 | flr = ioread32(tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
143 | if (ver > 2) |
144 | bflr = ioread32(tgpio->membase + TGPIO_BFLR); | |
35570ac6 RR |
145 | |
146 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
8c35c89a | 147 | bflr &= ~(1 << offset); |
35570ac6 RR |
148 | flr &= ~(1 << offset); |
149 | if (trigger & IRQ_TYPE_LEVEL_HIGH) | |
150 | lvr |= 1 << offset; | |
151 | else | |
152 | lvr &= ~(1 << offset); | |
153 | } | |
154 | ||
8c35c89a RR |
155 | if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
156 | if (ver < 3) | |
157 | return -EINVAL; | |
158 | else { | |
159 | flr |= 1 << offset; | |
160 | bflr |= 1 << offset; | |
161 | } | |
162 | } else { | |
163 | bflr &= ~(1 << offset); | |
35570ac6 | 164 | flr |= 1 << offset; |
35570ac6 | 165 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
35570ac6 | 166 | lvr &= ~(1 << offset); |
8c35c89a RR |
167 | else |
168 | lvr |= 1 << offset; | |
35570ac6 RR |
169 | } |
170 | ||
171 | iowrite32(lvr, tgpio->membase + TGPIO_LVR); | |
172 | iowrite32(flr, tgpio->membase + TGPIO_FLR); | |
8c35c89a RR |
173 | if (ver > 2) |
174 | iowrite32(bflr, tgpio->membase + TGPIO_BFLR); | |
175 | ||
35570ac6 RR |
176 | iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); |
177 | spin_unlock_irqrestore(&tgpio->lock, flags); | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) | |
183 | { | |
184 | struct timbgpio *tgpio = get_irq_data(irq); | |
185 | unsigned long ipr; | |
186 | int offset; | |
187 | ||
188 | desc->chip->ack(irq); | |
189 | ipr = ioread32(tgpio->membase + TGPIO_IPR); | |
190 | iowrite32(ipr, tgpio->membase + TGPIO_ICR); | |
191 | ||
984b3f57 | 192 | for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) |
35570ac6 RR |
193 | generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); |
194 | } | |
195 | ||
196 | static struct irq_chip timbgpio_irqchip = { | |
197 | .name = "GPIO", | |
198 | .enable = timbgpio_irq_enable, | |
199 | .disable = timbgpio_irq_disable, | |
200 | .set_type = timbgpio_irq_type, | |
201 | }; | |
202 | ||
203 | static int __devinit timbgpio_probe(struct platform_device *pdev) | |
204 | { | |
205 | int err, i; | |
206 | struct gpio_chip *gc; | |
207 | struct timbgpio *tgpio; | |
208 | struct resource *iomem; | |
209 | struct timbgpio_platform_data *pdata = pdev->dev.platform_data; | |
210 | int irq = platform_get_irq(pdev, 0); | |
211 | ||
212 | if (!pdata || pdata->nr_pins > 32) { | |
213 | err = -EINVAL; | |
214 | goto err_mem; | |
215 | } | |
216 | ||
217 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
218 | if (!iomem) { | |
219 | err = -EINVAL; | |
220 | goto err_mem; | |
221 | } | |
222 | ||
223 | tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL); | |
224 | if (!tgpio) { | |
225 | err = -EINVAL; | |
226 | goto err_mem; | |
227 | } | |
228 | tgpio->irq_base = pdata->irq_base; | |
229 | ||
230 | spin_lock_init(&tgpio->lock); | |
231 | ||
232 | if (!request_mem_region(iomem->start, resource_size(iomem), | |
233 | DRIVER_NAME)) { | |
234 | err = -EBUSY; | |
235 | goto err_request; | |
236 | } | |
237 | ||
238 | tgpio->membase = ioremap(iomem->start, resource_size(iomem)); | |
239 | if (!tgpio->membase) { | |
240 | err = -ENOMEM; | |
241 | goto err_ioremap; | |
242 | } | |
243 | ||
244 | gc = &tgpio->gpio; | |
245 | ||
246 | gc->label = dev_name(&pdev->dev); | |
247 | gc->owner = THIS_MODULE; | |
248 | gc->dev = &pdev->dev; | |
249 | gc->direction_input = timbgpio_gpio_direction_input; | |
250 | gc->get = timbgpio_gpio_get; | |
251 | gc->direction_output = timbgpio_gpio_direction_output; | |
252 | gc->set = timbgpio_gpio_set; | |
253 | gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL; | |
254 | gc->dbg_show = NULL; | |
255 | gc->base = pdata->gpio_base; | |
256 | gc->ngpio = pdata->nr_pins; | |
257 | gc->can_sleep = 0; | |
258 | ||
259 | err = gpiochip_add(gc); | |
260 | if (err) | |
261 | goto err_chipadd; | |
262 | ||
263 | platform_set_drvdata(pdev, tgpio); | |
264 | ||
265 | /* make sure to disable interrupts */ | |
266 | iowrite32(0x0, tgpio->membase + TGPIO_IER); | |
267 | ||
268 | if (irq < 0 || tgpio->irq_base <= 0) | |
269 | return 0; | |
270 | ||
271 | for (i = 0; i < pdata->nr_pins; i++) { | |
272 | set_irq_chip_and_handler_name(tgpio->irq_base + i, | |
273 | &timbgpio_irqchip, handle_simple_irq, "mux"); | |
274 | set_irq_chip_data(tgpio->irq_base + i, tgpio); | |
275 | #ifdef CONFIG_ARM | |
276 | set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE); | |
277 | #endif | |
278 | } | |
279 | ||
280 | set_irq_data(irq, tgpio); | |
281 | set_irq_chained_handler(irq, timbgpio_irq); | |
282 | ||
283 | return 0; | |
284 | ||
285 | err_chipadd: | |
286 | iounmap(tgpio->membase); | |
287 | err_ioremap: | |
288 | release_mem_region(iomem->start, resource_size(iomem)); | |
289 | err_request: | |
290 | kfree(tgpio); | |
291 | err_mem: | |
292 | printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err); | |
293 | ||
294 | return err; | |
295 | } | |
296 | ||
297 | static int __devexit timbgpio_remove(struct platform_device *pdev) | |
298 | { | |
299 | int err; | |
300 | struct timbgpio_platform_data *pdata = pdev->dev.platform_data; | |
301 | struct timbgpio *tgpio = platform_get_drvdata(pdev); | |
302 | struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
303 | int irq = platform_get_irq(pdev, 0); | |
304 | ||
305 | if (irq >= 0 && tgpio->irq_base > 0) { | |
306 | int i; | |
307 | for (i = 0; i < pdata->nr_pins; i++) { | |
308 | set_irq_chip(tgpio->irq_base + i, NULL); | |
309 | set_irq_chip_data(tgpio->irq_base + i, NULL); | |
310 | } | |
311 | ||
312 | set_irq_handler(irq, NULL); | |
313 | set_irq_data(irq, NULL); | |
314 | } | |
315 | ||
316 | err = gpiochip_remove(&tgpio->gpio); | |
317 | if (err) | |
318 | printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n"); | |
319 | ||
320 | iounmap(tgpio->membase); | |
321 | release_mem_region(iomem->start, resource_size(iomem)); | |
322 | kfree(tgpio); | |
323 | ||
324 | platform_set_drvdata(pdev, NULL); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static struct platform_driver timbgpio_platform_driver = { | |
330 | .driver = { | |
331 | .name = DRIVER_NAME, | |
332 | .owner = THIS_MODULE, | |
333 | }, | |
334 | .probe = timbgpio_probe, | |
335 | .remove = timbgpio_remove, | |
336 | }; | |
337 | ||
338 | /*--------------------------------------------------------------------------*/ | |
339 | ||
340 | static int __init timbgpio_init(void) | |
341 | { | |
342 | return platform_driver_register(&timbgpio_platform_driver); | |
343 | } | |
344 | ||
345 | static void __exit timbgpio_exit(void) | |
346 | { | |
347 | platform_driver_unregister(&timbgpio_platform_driver); | |
348 | } | |
349 | ||
350 | module_init(timbgpio_init); | |
351 | module_exit(timbgpio_exit); | |
352 | ||
353 | MODULE_DESCRIPTION("Timberdale GPIO driver"); | |
354 | MODULE_LICENSE("GPL v2"); | |
355 | MODULE_AUTHOR("Mocean Laboratories"); | |
356 | MODULE_ALIAS("platform:"DRIVER_NAME); | |
357 |