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Merge remote-tracking branch 'sound-asoc/for-next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
c632d799 54#include "amdgpu_ttm.h"
97b2e202 55#include "amdgpu_gds.h"
1f7371b2 56#include "amd_powerplay.h"
a8fe58ce 57#include "amdgpu_acp.h"
97b2e202 58
b80d8475
AD		 59#include "gpu_scheduler.h"
60
97b2e202
AD		 61/*
62 * Modules parameters.
63 */
64extern int amdgpu_modeset;
65extern int amdgpu_vram_limit;
66extern int amdgpu_gart_size;
67extern int amdgpu_benchmarking;
68extern int amdgpu_testing;
69extern int amdgpu_audio;
70extern int amdgpu_disp_priority;
71extern int amdgpu_hw_i2c;
72extern int amdgpu_pcie_gen2;
73extern int amdgpu_msi;
74extern int amdgpu_lockup_timeout;
75extern int amdgpu_dpm;
76extern int amdgpu_smc_load_fw;
77extern int amdgpu_aspm;
78extern int amdgpu_runtime_pm;
97b2e202
AD		 79extern unsigned amdgpu_ip_block_mask;
80extern int amdgpu_bapm;
81extern int amdgpu_deep_color;
82extern int amdgpu_vm_size;
83extern int amdgpu_vm_block_size;
d9c13156 84extern int amdgpu_vm_fault_stop;
b495bd3a 85extern int amdgpu_vm_debug;
1333f723 86extern int amdgpu_sched_jobs;
4afcb303 87extern int amdgpu_sched_hw_submission;
1f7371b2 88extern int amdgpu_powerplay;
6bb6b297 89extern int amdgpu_powercontainment;
cd474ba0
AD		 90extern unsigned amdgpu_pcie_gen_cap;
91extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 92extern unsigned amdgpu_cg_mask;
93extern unsigned amdgpu_pg_mask;
6f8941a2 94extern char *amdgpu_disable_cu;
66bc3f7f 95extern int amdgpu_sclk_deep_sleep_en;
9accf2fd 96extern char *amdgpu_virtual_display;
97b2e202 97
4b559c90 98#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 99#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
101/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
102#define AMDGPU_IB_POOL_SIZE 16
103#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
104#define AMDGPUFB_CONN_LIMIT 4
105#define AMDGPU_BIOS_NUM_SCRATCH 8
106
97b2e202
AD		 107/* max number of rings */
108#define AMDGPU_MAX_RINGS 16
109#define AMDGPU_MAX_GFX_RINGS 1
110#define AMDGPU_MAX_COMPUTE_RINGS 8
111#define AMDGPU_MAX_VCE_RINGS 2
112
36f523a7
JZ		 113/* max number of IP instances */
114#define AMDGPU_MAX_SDMA_INSTANCES 2
115
97b2e202
AD		 116/* hardcode that limit for now */
117#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
118
119/* hard reset data */
120#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
121
122/* reset flags */
123#define AMDGPU_RESET_GFX (1 << 0)
124#define AMDGPU_RESET_COMPUTE (1 << 1)
125#define AMDGPU_RESET_DMA (1 << 2)
126#define AMDGPU_RESET_CP (1 << 3)
127#define AMDGPU_RESET_GRBM (1 << 4)
128#define AMDGPU_RESET_DMA1 (1 << 5)
129#define AMDGPU_RESET_RLC (1 << 6)
130#define AMDGPU_RESET_SEM (1 << 7)
131#define AMDGPU_RESET_IH (1 << 8)
132#define AMDGPU_RESET_VMC (1 << 9)
133#define AMDGPU_RESET_MC (1 << 10)
134#define AMDGPU_RESET_DISPLAY (1 << 11)
135#define AMDGPU_RESET_UVD (1 << 12)
136#define AMDGPU_RESET_VCE (1 << 13)
137#define AMDGPU_RESET_VCE1 (1 << 14)
138
97b2e202
AD		 139/* GFX current status */
140#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
141#define AMDGPU_GFX_SAFE_MODE 0x00000001L
142#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
143#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
144#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
145
146/* max cursor sizes (in pixels) */
147#define CIK_CURSOR_WIDTH 128
148#define CIK_CURSOR_HEIGHT 128
149
150struct amdgpu_device;
97b2e202
AD		 151struct amdgpu_ib;
152struct amdgpu_vm;
153struct amdgpu_ring;
97b2e202 154struct amdgpu_cs_parser;
bb977d37 155struct amdgpu_job;
97b2e202 156struct amdgpu_irq_src;
0b492a4c 157struct amdgpu_fpriv;
97b2e202
AD		 158
159enum amdgpu_cp_irq {
160 AMDGPU_CP_IRQ_GFX_EOP = 0,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
169
170 AMDGPU_CP_IRQ_LAST
171};
172
173enum amdgpu_sdma_irq {
174 AMDGPU_SDMA_IRQ_TRAP0 = 0,
175 AMDGPU_SDMA_IRQ_TRAP1,
176
177 AMDGPU_SDMA_IRQ_LAST
178};
179
180enum amdgpu_thermal_irq {
181 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
182 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
183
184 AMDGPU_THERMAL_IRQ_LAST
185};
186
97b2e202 187int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 188 enum amd_ip_block_type block_type,
189 enum amd_clockgating_state state);
97b2e202 190int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 191 enum amd_ip_block_type block_type,
192 enum amd_powergating_state state);
5dbbb60b
AD		 193int amdgpu_wait_for_idle(struct amdgpu_device *adev,
194 enum amd_ip_block_type block_type);
195bool amdgpu_is_idle(struct amdgpu_device *adev,
196 enum amd_ip_block_type block_type);
97b2e202
AD		 197
198struct amdgpu_ip_block_version {
5fc3aeeb 199 enum amd_ip_block_type type;
97b2e202
AD		 200 u32 major;
201 u32 minor;
202 u32 rev;
5fc3aeeb 203 const struct amd_ip_funcs *funcs;
97b2e202
AD		 204};
205
206int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 207 enum amd_ip_block_type type,
97b2e202
AD		 208 u32 major, u32 minor);
209
210const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
211 struct amdgpu_device *adev,
5fc3aeeb 212 enum amd_ip_block_type type);
97b2e202
AD		 213
214/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
215struct amdgpu_buffer_funcs {
216 /* maximum bytes in a single operation */
217 uint32_t copy_max_bytes;
218
219 /* number of dw to reserve per operation */
220 unsigned copy_num_dw;
221
222 /* used for buffer migration */
c7ae72c0 223 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 224 /* src addr in bytes */
225 uint64_t src_offset,
226 /* dst addr in bytes */
227 uint64_t dst_offset,
228 /* number of byte to transfer */
229 uint32_t byte_count);
230
231 /* maximum bytes in a single operation */
232 uint32_t fill_max_bytes;
233
234 /* number of dw to reserve per operation */
235 unsigned fill_num_dw;
236
237 /* used for buffer clearing */
6e7a3840 238 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 239 /* value to write to memory */
240 uint32_t src_data,
241 /* dst addr in bytes */
242 uint64_t dst_offset,
243 /* number of byte to fill */
244 uint32_t byte_count);
245};
246
247/* provided by hw blocks that can write ptes, e.g., sdma */
248struct amdgpu_vm_pte_funcs {
249 /* copy pte entries from GART */
250 void (*copy_pte)(struct amdgpu_ib *ib,
251 uint64_t pe, uint64_t src,
252 unsigned count);
253 /* write pte one entry at a time with addr mapping */
de9ea7bd
CK		 254 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
255 uint64_t value, unsigned count,
256 uint32_t incr);
97b2e202
AD		 257 /* for linear pte/pde updates without addr mapping */
258 void (*set_pte_pde)(struct amdgpu_ib *ib,
259 uint64_t pe,
260 uint64_t addr, unsigned count,
261 uint32_t incr, uint32_t flags);
97b2e202
AD		 262};
263
264/* provided by the gmc block */
265struct amdgpu_gart_funcs {
266 /* flush the vm tlb via mmio */
267 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
268 uint32_t vmid);
269 /* write pte/pde updates using the cpu */
270 int (*set_pte_pde)(struct amdgpu_device *adev,
271 void *cpu_pt_addr, /* cpu addr of page table */
272 uint32_t gpu_page_idx, /* pte/pde to update */
273 uint64_t addr, /* addr to write into pte/pde */
274 uint32_t flags); /* access flags */
275};
276
277/* provided by the ih block */
278struct amdgpu_ih_funcs {
279 /* ring read/write ptr handling, called from interrupt context */
280 u32 (*get_wptr)(struct amdgpu_device *adev);
281 void (*decode_iv)(struct amdgpu_device *adev,
282 struct amdgpu_iv_entry *entry);
283 void (*set_rptr)(struct amdgpu_device *adev);
284};
285
286/* provided by hw blocks that expose a ring buffer for commands */
287struct amdgpu_ring_funcs {
288 /* ring read/write ptr handling */
289 u32 (*get_rptr)(struct amdgpu_ring *ring);
290 u32 (*get_wptr)(struct amdgpu_ring *ring);
291 void (*set_wptr)(struct amdgpu_ring *ring);
292 /* validating and patching of IBs */
293 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
294 /* command emit functions */
295 void (*emit_ib)(struct amdgpu_ring *ring,
d88bf583
CK		 296 struct amdgpu_ib *ib,
297 unsigned vm_id, bool ctx_switch);
97b2e202 298 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 299 uint64_t seq, unsigned flags);
b8c7b39e 300 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 301 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
302 uint64_t pd_addr);
d2edb07b 303 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 304 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 305 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
306 uint32_t gds_base, uint32_t gds_size,
307 uint32_t gws_base, uint32_t gws_size,
308 uint32_t oa_base, uint32_t oa_size);
309 /* testing functions */
310 int (*test_ring)(struct amdgpu_ring *ring);
bbec97aa 311 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
edff0e28
JZ		 312 /* insert NOP packets */
313 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 314 /* pad the indirect buffer to the necessary number of dw */
315 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
03ccf481
ML		 316 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
317 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
f06505b8
CK		 318 /* note usage for clock and power gating */
319 void (*begin_use)(struct amdgpu_ring *ring);
320 void (*end_use)(struct amdgpu_ring *ring);
97b2e202
AD		 321};
322
323/*
324 * BIOS.
325 */
326bool amdgpu_get_bios(struct amdgpu_device *adev);
327bool amdgpu_read_bios(struct amdgpu_device *adev);
328
329/*
330 * Dummy page
331 */
332struct amdgpu_dummy_page {
333 struct page *page;
334 dma_addr_t addr;
335};
336int amdgpu_dummy_page_init(struct amdgpu_device *adev);
337void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
338
339
340/*
341 * Clocks
342 */
343
344#define AMDGPU_MAX_PPLL 3
345
346struct amdgpu_clock {
347 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
348 struct amdgpu_pll spll;
349 struct amdgpu_pll mpll;
350 /* 10 Khz units */
351 uint32_t default_mclk;
352 uint32_t default_sclk;
353 uint32_t default_dispclk;
354 uint32_t current_dispclk;
355 uint32_t dp_extclk;
356 uint32_t max_pixel_clock;
357};
358
359/*
360 * Fences.
361 */
362struct amdgpu_fence_driver {
97b2e202
AD		 363 uint64_t gpu_addr;
364 volatile uint32_t *cpu_addr;
365 /* sync_seq is protected by ring emission lock */
742c085f
CK		 366 uint32_t sync_seq;
367 atomic_t last_seq;
97b2e202 368 bool initialized;
97b2e202
AD		 369 struct amdgpu_irq_src *irq_src;
370 unsigned irq_type;
c2776afe 371 struct timer_list fallback_timer;
c89377d1 372 unsigned num_fences_mask;
4a7d74f1 373 spinlock_t lock;
c89377d1 374 struct fence **fences;
97b2e202
AD		 375};
376
377/* some special values for the owner field */
378#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
379#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 380
890ee23f
CZ		 381#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
382#define AMDGPU_FENCE_FLAG_INT (1 << 1)
383
97b2e202
AD		 384int amdgpu_fence_driver_init(struct amdgpu_device *adev);
385void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
386void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
387
e6151a08
CK		 388int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
389 unsigned num_hw_submission);
97b2e202
AD		 390int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
391 struct amdgpu_irq_src *irq_src,
392 unsigned irq_type);
5ceb54c6
AD		 393void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
394void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 395int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202 396void amdgpu_fence_process(struct amdgpu_ring *ring);
97b2e202
AD		 397int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
398unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
399
97b2e202 400/*
c632d799 401 * BO.
97b2e202 402 */
29b3259a 403
97b2e202
AD		 404struct amdgpu_bo_list_entry {
405 struct amdgpu_bo *robj;
406 struct ttm_validate_buffer tv;
407 struct amdgpu_bo_va *bo_va;
97b2e202 408 uint32_t priority;
2f568dbd
CK		 409 struct page **user_pages;
410 int user_invalidated;
97b2e202
AD		 411};
412
413struct amdgpu_bo_va_mapping {
414 struct list_head list;
415 struct interval_tree_node it;
416 uint64_t offset;
417 uint32_t flags;
418};
419
420/* bo virtual addresses in a specific vm */
421struct amdgpu_bo_va {
422 /* protected by bo being reserved */
423 struct list_head bo_list;
bb1e38a4 424 struct fence *last_pt_update;
97b2e202
AD		 425 unsigned ref_count;
426
7fc11959 427 /* protected by vm mutex and spinlock */
97b2e202
AD		 428 struct list_head vm_status;
429
7fc11959
CK		 430 /* mappings for this bo_va */
431 struct list_head invalids;
432 struct list_head valids;
433
97b2e202
AD		 434 /* constant after initialization */
435 struct amdgpu_vm *vm;
436 struct amdgpu_bo *bo;
437};
438
7e5a547f
CZ		 439#define AMDGPU_GEM_DOMAIN_MAX 0x3
440
97b2e202
AD		 441struct amdgpu_bo {
442 /* Protected by gem.mutex */
443 struct list_head list;
444 /* Protected by tbo.reserved */
1ea863fd
CK		 445 u32 prefered_domains;
446 u32 allowed_domains;
7e5a547f 447 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 448 struct ttm_placement placement;
449 struct ttm_buffer_object tbo;
450 struct ttm_bo_kmap_obj kmap;
451 u64 flags;
452 unsigned pin_count;
453 void *kptr;
454 u64 tiling_flags;
455 u64 metadata_flags;
456 void *metadata;
457 u32 metadata_size;
458 /* list of all virtual address to which this bo
459 * is associated to
460 */
461 struct list_head va;
462 /* Constant after initialization */
463 struct amdgpu_device *adev;
464 struct drm_gem_object gem_base;
82b9c55b 465 struct amdgpu_bo *parent;
e7893c4b 466 struct amdgpu_bo *shadow;
97b2e202
AD		 467
468 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 469 struct amdgpu_mn *mn;
470 struct list_head mn_list;
0c4e7fa5 471 struct list_head shadow_list;
97b2e202
AD		 472};
473#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
474
475void amdgpu_gem_object_free(struct drm_gem_object *obj);
476int amdgpu_gem_object_open(struct drm_gem_object *obj,
477 struct drm_file *file_priv);
478void amdgpu_gem_object_close(struct drm_gem_object *obj,
479 struct drm_file *file_priv);
480unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
481struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 482struct drm_gem_object *
483amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
484 struct dma_buf_attachment *attach,
485 struct sg_table *sg);
97b2e202
AD		 486struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
487 struct drm_gem_object *gobj,
488 int flags);
489int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
490void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
491struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
492void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
493void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
494int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
495
496/* sub-allocation manager, it has to be protected by another lock.
497 * By conception this is an helper for other part of the driver
498 * like the indirect buffer or semaphore, which both have their
499 * locking.
500 *
501 * Principe is simple, we keep a list of sub allocation in offset
502 * order (first entry has offset == 0, last entry has the highest
503 * offset).
504 *
505 * When allocating new object we first check if there is room at
506 * the end total_size - (last_object_offset + last_object_size) >=
507 * alloc_size. If so we allocate new object there.
508 *
509 * When there is not enough room at the end, we start waiting for
510 * each sub object until we reach object_offset+object_size >=
511 * alloc_size, this object then become the sub object we return.
512 *
513 * Alignment can't be bigger than page size.
514 *
515 * Hole are not considered for allocation to keep things simple.
516 * Assumption is that there won't be hole (all object on same
517 * alignment).
518 */
6ba60b89
CK		 519
520#define AMDGPU_SA_NUM_FENCE_LISTS 32
521
97b2e202
AD		 522struct amdgpu_sa_manager {
523 wait_queue_head_t wq;
524 struct amdgpu_bo *bo;
525 struct list_head *hole;
6ba60b89 526 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 527 struct list_head olist;
528 unsigned size;
529 uint64_t gpu_addr;
530 void *cpu_ptr;
531 uint32_t domain;
532 uint32_t align;
533};
534
97b2e202
AD		 535/* sub-allocation buffer */
536struct amdgpu_sa_bo {
537 struct list_head olist;
538 struct list_head flist;
539 struct amdgpu_sa_manager *manager;
540 unsigned soffset;
541 unsigned eoffset;
4ce9891e 542 struct fence *fence;
97b2e202
AD		 543};
544
545/*
546 * GEM objects.
547 */
418aa0c2 548void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 549int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
550 int alignment, u32 initial_domain,
551 u64 flags, bool kernel,
552 struct drm_gem_object **obj);
553
554int amdgpu_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557int amdgpu_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 560/*
561 * Synchronization
562 */
563struct amdgpu_sync {
f91b3a69 564 DECLARE_HASHTABLE(fences, 4);
3c62338c 565 struct fence *last_vm_update;
97b2e202
AD		 566};
567
568void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 569int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
570 struct fence *f);
97b2e202
AD		 571int amdgpu_sync_resv(struct amdgpu_device *adev,
572 struct amdgpu_sync *sync,
573 struct reservation_object *resv,
574 void *owner);
1fbb2e92
CK		 575struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
576 struct amdgpu_ring *ring);
e61235db 577struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
8a8f0b48 578void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 579int amdgpu_sync_init(void);
580void amdgpu_sync_fini(void);
d573de2d
RZ		 581int amdgpu_fence_slab_init(void);
582void amdgpu_fence_slab_fini(void);
97b2e202
AD		 583
584/*
585 * GART structures, functions & helpers
586 */
587struct amdgpu_mc;
588
589#define AMDGPU_GPU_PAGE_SIZE 4096
590#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
591#define AMDGPU_GPU_PAGE_SHIFT 12
592#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
593
594struct amdgpu_gart {
595 dma_addr_t table_addr;
596 struct amdgpu_bo *robj;
597 void *ptr;
598 unsigned num_gpu_pages;
599 unsigned num_cpu_pages;
600 unsigned table_size;
a1d29476 601#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 602 struct page **pages;
a1d29476 603#endif
97b2e202
AD		 604 bool ready;
605 const struct amdgpu_gart_funcs *gart_funcs;
606};
607
608int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
609void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
610int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
611void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
612int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
613void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
614int amdgpu_gart_init(struct amdgpu_device *adev);
615void amdgpu_gart_fini(struct amdgpu_device *adev);
cab0b8d5 616void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
97b2e202 617 int pages);
cab0b8d5 618int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
97b2e202
AD		 619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr, uint32_t flags);
621
622/*
623 * GPU MC structures, functions & helpers
624 */
625struct amdgpu_mc {
626 resource_size_t aper_size;
627 resource_size_t aper_base;
628 resource_size_t agp_base;
629 /* for some chips with <= 32MB we need to lie
630 * about vram size near mc fb location */
631 u64 mc_vram_size;
632 u64 visible_vram_size;
633 u64 gtt_size;
634 u64 gtt_start;
635 u64 gtt_end;
636 u64 vram_start;
637 u64 vram_end;
638 unsigned vram_width;
639 u64 real_vram_size;
640 int vram_mtrr;
641 u64 gtt_base_align;
642 u64 mc_mask;
643 const struct firmware *fw; /* MC firmware */
644 uint32_t fw_version;
645 struct amdgpu_irq_src vm_fault;
81c59f54 646 uint32_t vram_type;
50b0197a
CZ		 647 uint32_t srbm_soft_reset;
648 struct amdgpu_mode_mc_save save;
97b2e202
AD		 649};
650
651/*
652 * GPU doorbell structures, functions & helpers
653 */
654typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
655{
656 AMDGPU_DOORBELL_KIQ = 0x000,
657 AMDGPU_DOORBELL_HIQ = 0x001,
658 AMDGPU_DOORBELL_DIQ = 0x002,
659 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
660 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
661 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
662 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
663 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
664 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
665 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
666 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
667 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
668 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
669 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
670 AMDGPU_DOORBELL_IH = 0x1E8,
671 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
672 AMDGPU_DOORBELL_INVALID = 0xFFFF
673} AMDGPU_DOORBELL_ASSIGNMENT;
674
675struct amdgpu_doorbell {
676 /* doorbell mmio */
677 resource_size_t base;
678 resource_size_t size;
679 u32 __iomem *ptr;
680 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
681};
682
683void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
684 phys_addr_t *aperture_base,
685 size_t *aperture_size,
686 size_t *start_offset);
687
688/*
689 * IRQS.
690 */
691
692struct amdgpu_flip_work {
325cbba1 693 struct delayed_work flip_work;
97b2e202
AD		 694 struct work_struct unpin_work;
695 struct amdgpu_device *adev;
696 int crtc_id;
325cbba1 697 u32 target_vblank;
97b2e202
AD		 698 uint64_t base;
699 struct drm_pending_vblank_event *event;
700 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 701 struct fence *excl;
702 unsigned shared_count;
703 struct fence **shared;
c3874b75 704 struct fence_cb cb;
cb9e59d7 705 bool async;
97b2e202
AD		 706};
707
708
709/*
710 * CP & rings.
711 */
712
713struct amdgpu_ib {
714 struct amdgpu_sa_bo *sa_bo;
715 uint32_t length_dw;
716 uint64_t gpu_addr;
717 uint32_t *ptr;
de807f81 718 uint32_t flags;
97b2e202
AD		 719};
720
721enum amdgpu_ring_type {
722 AMDGPU_RING_TYPE_GFX,
723 AMDGPU_RING_TYPE_COMPUTE,
724 AMDGPU_RING_TYPE_SDMA,
725 AMDGPU_RING_TYPE_UVD,
726 AMDGPU_RING_TYPE_VCE
727};
728
62250a91 729extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 730
50838c8c 731int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 732 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 733int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
734 struct amdgpu_job **job);
b6723c8d 735
a5fb4ec2 736void amdgpu_job_free_resources(struct amdgpu_job *job);
50838c8c 737void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 738int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 739 struct amd_sched_entity *entity, void *owner,
740 struct fence **f);
3c704e93 741
97b2e202
AD		 742struct amdgpu_ring {
743 struct amdgpu_device *adev;
744 const struct amdgpu_ring_funcs *funcs;
745 struct amdgpu_fence_driver fence_drv;
edf600da 746 struct amd_gpu_scheduler sched;
97b2e202 747
97b2e202
AD		 748 struct amdgpu_bo *ring_obj;
749 volatile uint32_t *ring;
750 unsigned rptr_offs;
97b2e202
AD		 751 unsigned wptr;
752 unsigned wptr_old;
753 unsigned ring_size;
c7e6be23 754 unsigned max_dw;
97b2e202 755 int count_dw;
97b2e202
AD		 756 uint64_t gpu_addr;
757 uint32_t align_mask;
758 uint32_t ptr_mask;
759 bool ready;
760 u32 nop;
761 u32 idx;
97b2e202
AD		 762 u32 me;
763 u32 pipe;
764 u32 queue;
765 struct amdgpu_bo *mqd_obj;
766 u32 doorbell_index;
767 bool use_doorbell;
768 unsigned wptr_offs;
97b2e202 769 unsigned fence_offs;
aa3b73f6 770 uint64_t current_ctx;
97b2e202
AD		 771 enum amdgpu_ring_type type;
772 char name[16];
128cff1a 773 unsigned cond_exe_offs;
92c023c4
CK		 774 u64 cond_exe_gpu_addr;
775 volatile u32 *cond_exe_cpu_addr;
a909c6bd
ML		 776#if defined(CONFIG_DEBUG_FS)
777 struct dentry *ent;
778#endif
97b2e202
AD		 779};
780
781/*
782 * VM
783 */
784
785/* maximum number of VMIDs */
786#define AMDGPU_NUM_VM 16
787
96105e53
CK		 788/* Maximum number of PTEs the hardware can write with one command */
789#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
790
97b2e202
AD		 791/* number of entries in page table */
792#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
793
794/* PTBs (Page Table Blocks) need to be aligned to 32K */
795#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
97b2e202 796
1303c73c
CK		 797/* LOG2 number of continuous pages for the fragment field */
798#define AMDGPU_LOG2_PAGES_PER_FRAG 4
97b2e202
AD		 799
800#define AMDGPU_PTE_VALID (1 << 0)
801#define AMDGPU_PTE_SYSTEM (1 << 1)
802#define AMDGPU_PTE_SNOOPED (1 << 2)
803
804/* VI only */
805#define AMDGPU_PTE_EXECUTABLE (1 << 4)
806
807#define AMDGPU_PTE_READABLE (1 << 5)
808#define AMDGPU_PTE_WRITEABLE (1 << 6)
809
1303c73c 810#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
97b2e202 811
d9c13156
CK		 812/* How to programm VM fault handling */
813#define AMDGPU_VM_FAULT_STOP_NEVER 0
814#define AMDGPU_VM_FAULT_STOP_FIRST 1
815#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
816
97b2e202 817struct amdgpu_vm_pt {
ee1782c3
CK		 818 struct amdgpu_bo_list_entry entry;
819 uint64_t addr;
6557e3d2 820 uint64_t shadow_addr;
97b2e202
AD		 821};
822
97b2e202 823struct amdgpu_vm {
25cfc3c2 824 /* tree of virtual addresses mapped */
97b2e202
AD		 825 struct rb_root va;
826
7fc11959 827 /* protecting invalidated */
97b2e202
AD		 828 spinlock_t status_lock;
829
830 /* BOs moved, but not yet updated in the PT */
831 struct list_head invalidated;
832
7fc11959
CK		 833 /* BOs cleared in the PT because of a move */
834 struct list_head cleared;
835
836 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 837 struct list_head freed;
838
839 /* contains the page directory */
840 struct amdgpu_bo *page_directory;
841 unsigned max_pde_used;
05906dec 842 struct fence *page_directory_fence;
5a712a87 843 uint64_t last_eviction_counter;
97b2e202
AD		 844
845 /* array of page tables, one for each page directory entry */
846 struct amdgpu_vm_pt *page_tables;
847
848 /* for id and flush management per ring */
bcb1ba35 849 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
25cfc3c2 850
81d75a30 851 /* protecting freed */
852 spinlock_t freed_lock;
2bd9ccfa
CK		 853
854 /* Scheduler entity for page table updates */
855 struct amd_sched_entity entity;
031e2983
CZ		 856
857 /* client id */
858 u64 client_id;
97b2e202
AD		 859};
860
bcb1ba35 861struct amdgpu_vm_id {
a9a78b32 862 struct list_head list;
832a902f
CK		 863 struct fence *first;
864 struct amdgpu_sync active;
41d9eb2c 865 struct fence *last_flush;
0ea54b9b 866 atomic64_t owner;
971fe9a9 867
bcb1ba35
CK		 868 uint64_t pd_gpu_addr;
869 /* last flushed PD/PT update */
870 struct fence *flushed_updates;
871
6adb0513
CZ		 872 uint32_t current_gpu_reset_count;
873
971fe9a9
CK		 874 uint32_t gds_base;
875 uint32_t gds_size;
876 uint32_t gws_base;
877 uint32_t gws_size;
878 uint32_t oa_base;
879 uint32_t oa_size;
a9a78b32
CK		 880};
881
97b2e202 882struct amdgpu_vm_manager {
a9a78b32 883 /* Handling of VMIDs */
8d0a7cea 884 struct mutex lock;
a9a78b32
CK		 885 unsigned num_ids;
886 struct list_head ids_lru;
bcb1ba35 887 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
1c16c0a7 888
1fbb2e92
CK		 889 /* Handling of VM fences */
890 u64 fence_context;
891 unsigned seqno[AMDGPU_MAX_RINGS];
892
8b4fb00b 893 uint32_t max_pfn;
97b2e202 894 /* vram base address for page table entry */
8b4fb00b 895 u64 vram_base_offset;
97b2e202 896 /* is vm enabled? */
8b4fb00b 897 bool enabled;
97b2e202
AD		 898 /* vm pte handling */
899 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 900 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
901 unsigned vm_pte_num_rings;
902 atomic_t vm_pte_next_ring;
031e2983
CZ		 903 /* client id counter */
904 atomic64_t client_counter;
97b2e202
AD		 905};
906
a9a78b32 907void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 908void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 909int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
910void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 911void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
912 struct list_head *validated,
913 struct amdgpu_bo_list_entry *entry);
5a712a87
CK		 914void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
915 struct list_head *duplicates);
eceb8a15
CK		 916void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
917 struct amdgpu_vm *vm);
8b4fb00b 918int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83 919 struct amdgpu_sync *sync, struct fence *fence,
fd53be30
CZ		 920 struct amdgpu_job *job);
921int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
971fe9a9 922void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
8b4fb00b
CK		 923int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
924 struct amdgpu_vm *vm);
925int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
926 struct amdgpu_vm *vm);
927int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
928 struct amdgpu_sync *sync);
929int amdgpu_vm_bo_update(struct amdgpu_device *adev,
930 struct amdgpu_bo_va *bo_va,
99e124f4 931 bool clear);
8b4fb00b
CK		 932void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
933 struct amdgpu_bo *bo);
934struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
935 struct amdgpu_bo *bo);
936struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
937 struct amdgpu_vm *vm,
938 struct amdgpu_bo *bo);
939int amdgpu_vm_bo_map(struct amdgpu_device *adev,
940 struct amdgpu_bo_va *bo_va,
941 uint64_t addr, uint64_t offset,
942 uint64_t size, uint32_t flags);
943int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
944 struct amdgpu_bo_va *bo_va,
945 uint64_t addr);
946void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
947 struct amdgpu_bo_va *bo_va);
8b4fb00b 948
97b2e202
AD		 949/*
950 * context related structures
951 */
952
21c16bf6 953struct amdgpu_ctx_ring {
91404fb2 954 uint64_t sequence;
37cd0ca2 955 struct fence **fences;
91404fb2 956 struct amd_sched_entity entity;
21c16bf6
CK		 957};
958
97b2e202 959struct amdgpu_ctx {
0b492a4c 960 struct kref refcount;
9cb7e5a9 961 struct amdgpu_device *adev;
0b492a4c 962 unsigned reset_counter;
21c16bf6 963 spinlock_t ring_lock;
37cd0ca2 964 struct fence **fences;
21c16bf6 965 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 966};
967
968struct amdgpu_ctx_mgr {
0b492a4c
AD		 969 struct amdgpu_device *adev;
970 struct mutex lock;
971 /* protected by lock */
972 struct idr ctx_handles;
97b2e202
AD		 973};
974
0b492a4c
AD		 975struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
976int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
977
21c16bf6 978uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 979 struct fence *fence);
21c16bf6
CK		 980struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
981 struct amdgpu_ring *ring, uint64_t seq);
982
0b492a4c
AD		 983int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *filp);
985
efd4ccb5
CK		 986void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
987void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 988
97b2e202
AD		 989/*
990 * file private structure
991 */
992
993struct amdgpu_fpriv {
994 struct amdgpu_vm vm;
995 struct mutex bo_list_lock;
996 struct idr bo_list_handles;
0b492a4c 997 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 998};
999
1000/*
1001 * residency list
1002 */
1003
1004struct amdgpu_bo_list {
1005 struct mutex lock;
1006 struct amdgpu_bo *gds_obj;
1007 struct amdgpu_bo *gws_obj;
1008 struct amdgpu_bo *oa_obj;
211dff55 1009 unsigned first_userptr;
97b2e202
AD		 1010 unsigned num_entries;
1011 struct amdgpu_bo_list_entry *array;
1012};
1013
1014struct amdgpu_bo_list *
1015amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1016void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1017 struct list_head *validated);
97b2e202
AD		 1018void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1019void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1020
1021/*
1022 * GFX stuff
1023 */
1024#include "clearstate_defs.h"
1025
79e5412c
AD		 1026struct amdgpu_rlc_funcs {
1027 void (*enter_safe_mode)(struct amdgpu_device *adev);
1028 void (*exit_safe_mode)(struct amdgpu_device *adev);
1029};
1030
97b2e202
AD		 1031struct amdgpu_rlc {
1032 /* for power gating */
1033 struct amdgpu_bo *save_restore_obj;
1034 uint64_t save_restore_gpu_addr;
1035 volatile uint32_t *sr_ptr;
1036 const u32 *reg_list;
1037 u32 reg_list_size;
1038 /* for clear state */
1039 struct amdgpu_bo *clear_state_obj;
1040 uint64_t clear_state_gpu_addr;
1041 volatile uint32_t *cs_ptr;
1042 const struct cs_section_def *cs_data;
1043 u32 clear_state_size;
1044 /* for cp tables */
1045 struct amdgpu_bo *cp_table_obj;
1046 uint64_t cp_table_gpu_addr;
1047 volatile uint32_t *cp_table_ptr;
1048 u32 cp_table_size;
79e5412c
AD		 1049
1050 /* safe mode for updating CG/PG state */
1051 bool in_safe_mode;
1052 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 1053
1054 /* for firmware data */
1055 u32 save_and_restore_offset;
1056 u32 clear_state_descriptor_offset;
1057 u32 avail_scratch_ram_locations;
1058 u32 reg_restore_list_size;
1059 u32 reg_list_format_start;
1060 u32 reg_list_format_separate_start;
1061 u32 starting_offsets_start;
1062 u32 reg_list_format_size_bytes;
1063 u32 reg_list_size_bytes;
1064
1065 u32 *register_list_format;
1066 u32 *register_restore;
97b2e202
AD		 1067};
1068
1069struct amdgpu_mec {
1070 struct amdgpu_bo *hpd_eop_obj;
1071 u64 hpd_eop_gpu_addr;
1072 u32 num_pipe;
1073 u32 num_mec;
1074 u32 num_queue;
1075};
1076
1077/*
1078 * GPU scratch registers structures, functions & helpers
1079 */
1080struct amdgpu_scratch {
1081 unsigned num_reg;
1082 uint32_t reg_base;
1083 bool free[32];
1084 uint32_t reg[32];
1085};
1086
1087/*
1088 * GFX configurations
1089 */
1090struct amdgpu_gca_config {
1091 unsigned max_shader_engines;
1092 unsigned max_tile_pipes;
1093 unsigned max_cu_per_sh;
1094 unsigned max_sh_per_se;
1095 unsigned max_backends_per_se;
1096 unsigned max_texture_channel_caches;
1097 unsigned max_gprs;
1098 unsigned max_gs_threads;
1099 unsigned max_hw_contexts;
1100 unsigned sc_prim_fifo_size_frontend;
1101 unsigned sc_prim_fifo_size_backend;
1102 unsigned sc_hiz_tile_fifo_size;
1103 unsigned sc_earlyz_tile_fifo_size;
1104
1105 unsigned num_tile_pipes;
1106 unsigned backend_enable_mask;
1107 unsigned mem_max_burst_length_bytes;
1108 unsigned mem_row_size_in_kb;
1109 unsigned shader_engine_tile_size;
1110 unsigned num_gpus;
1111 unsigned multi_gpu_tile_size;
1112 unsigned mc_arb_ramcfg;
1113 unsigned gb_addr_config;
8f8e00c1 1114 unsigned num_rbs;
97b2e202
AD		 1115
1116 uint32_t tile_mode_array[32];
1117 uint32_t macrotile_mode_array[16];
1118};
1119
7dae69a2
AD		 1120struct amdgpu_cu_info {
1121 uint32_t number; /* total active CU number */
1122 uint32_t ao_cu_mask;
1123 uint32_t bitmap[4][4];
1124};
1125
b95e31fd
AD		 1126struct amdgpu_gfx_funcs {
1127 /* get the gpu clock counter */
1128 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9559ef5b 1129 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
b95e31fd
AD		 1130};
1131
97b2e202
AD		 1132struct amdgpu_gfx {
1133 struct mutex gpu_clock_mutex;
1134 struct amdgpu_gca_config config;
1135 struct amdgpu_rlc rlc;
1136 struct amdgpu_mec mec;
1137 struct amdgpu_scratch scratch;
1138 const struct firmware *me_fw; /* ME firmware */
1139 uint32_t me_fw_version;
1140 const struct firmware *pfp_fw; /* PFP firmware */
1141 uint32_t pfp_fw_version;
1142 const struct firmware *ce_fw; /* CE firmware */
1143 uint32_t ce_fw_version;
1144 const struct firmware *rlc_fw; /* RLC firmware */
1145 uint32_t rlc_fw_version;
1146 const struct firmware *mec_fw; /* MEC firmware */
1147 uint32_t mec_fw_version;
1148 const struct firmware *mec2_fw; /* MEC2 firmware */
1149 uint32_t mec2_fw_version;
02558a00
KW		 1150 uint32_t me_feature_version;
1151 uint32_t ce_feature_version;
1152 uint32_t pfp_feature_version;
351643d7
JZ		 1153 uint32_t rlc_feature_version;
1154 uint32_t mec_feature_version;
1155 uint32_t mec2_feature_version;
97b2e202
AD		 1156 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1157 unsigned num_gfx_rings;
1158 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1159 unsigned num_compute_rings;
1160 struct amdgpu_irq_src eop_irq;
1161 struct amdgpu_irq_src priv_reg_irq;
1162 struct amdgpu_irq_src priv_inst_irq;
1163 /* gfx status */
7dae69a2 1164 uint32_t gfx_current_status;
a101a899 1165 /* ce ram size*/
7dae69a2
AD		 1166 unsigned ce_ram_size;
1167 struct amdgpu_cu_info cu_info;
b95e31fd 1168 const struct amdgpu_gfx_funcs *funcs;
3d7c6384
CZ		 1169
1170 /* reset mask */
1171 uint32_t grbm_soft_reset;
1172 uint32_t srbm_soft_reset;
97b2e202
AD		 1173};
1174
b07c60c0 1175int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1176 unsigned size, struct amdgpu_ib *ib);
4d9c514d
CK		 1177void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1178 struct fence *f);
b07c60c0 1179int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1180 struct amdgpu_ib *ib, struct fence *last_vm_update,
c5637837 1181 struct amdgpu_job *job, struct fence **f);
97b2e202
AD		 1182int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1183void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1184int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1185int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1186void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1187void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1188void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1189void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1190int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1191 unsigned ring_size, u32 nop, u32 align_mask,
1192 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1193 enum amdgpu_ring_type ring_type);
1194void amdgpu_ring_fini(struct amdgpu_ring *ring);
1195
1196/*
1197 * CS.
1198 */
1199struct amdgpu_cs_chunk {
1200 uint32_t chunk_id;
1201 uint32_t length_dw;
758ac17f 1202 void *kdata;
97b2e202
AD		 1203};
1204
1205struct amdgpu_cs_parser {
1206 struct amdgpu_device *adev;
1207 struct drm_file *filp;
3cb485f3 1208 struct amdgpu_ctx *ctx;
c3cca41e 1209
97b2e202
AD		 1210 /* chunks */
1211 unsigned nchunks;
1212 struct amdgpu_cs_chunk *chunks;
97b2e202 1213
50838c8c
CK		 1214 /* scheduler job object */
1215 struct amdgpu_job *job;
97b2e202 1216
c3cca41e
CK		 1217 /* buffer objects */
1218 struct ww_acquire_ctx ticket;
1219 struct amdgpu_bo_list *bo_list;
1220 struct amdgpu_bo_list_entry vm_pd;
1221 struct list_head validated;
1222 struct fence *fence;
1223 uint64_t bytes_moved_threshold;
1224 uint64_t bytes_moved;
97b2e202
AD		 1225
1226 /* user fence */
91acbeb6 1227 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1228};
1229
bb977d37
CZ		 1230struct amdgpu_job {
1231 struct amd_sched_job base;
1232 struct amdgpu_device *adev;
edf600da 1233 struct amdgpu_vm *vm;
b07c60c0 1234 struct amdgpu_ring *ring;
e86f9cee 1235 struct amdgpu_sync sync;
bb977d37 1236 struct amdgpu_ib *ibs;
73cfa5f5 1237 struct fence *fence; /* the hw fence */
bb977d37 1238 uint32_t num_ibs;
e2840221 1239 void *owner;
92f25098 1240 uint64_t ctx;
fd53be30 1241 bool vm_needs_flush;
d88bf583
CK		 1242 unsigned vm_id;
1243 uint64_t vm_pd_addr;
1244 uint32_t gds_base, gds_size;
1245 uint32_t gws_base, gws_size;
1246 uint32_t oa_base, oa_size;
758ac17f
CK		 1247
1248 /* user fence handling */
b5f5acbc 1249 uint64_t uf_addr;
758ac17f
CK		 1250 uint64_t uf_sequence;
1251
bb977d37 1252};
a6db8a33
JZ		 1253#define to_amdgpu_job(sched_job) \
1254 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1255
7270f839
CK		 1256static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1257 uint32_t ib_idx, int idx)
97b2e202 1258{
50838c8c 1259 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1260}
1261
7270f839
CK		 1262static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1263 uint32_t ib_idx, int idx,
1264 uint32_t value)
1265{
50838c8c 1266 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1267}
1268
97b2e202
AD		 1269/*
1270 * Writeback
1271 */
1272#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1273
1274struct amdgpu_wb {
1275 struct amdgpu_bo *wb_obj;
1276 volatile uint32_t *wb;
1277 uint64_t gpu_addr;
1278 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1279 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1280};
1281
1282int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1283void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1284
97b2e202 1285
97b2e202
AD		 1286
1287enum amdgpu_int_thermal_type {
1288 THERMAL_TYPE_NONE,
1289 THERMAL_TYPE_EXTERNAL,
1290 THERMAL_TYPE_EXTERNAL_GPIO,
1291 THERMAL_TYPE_RV6XX,
1292 THERMAL_TYPE_RV770,
1293 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1294 THERMAL_TYPE_EVERGREEN,
1295 THERMAL_TYPE_SUMO,
1296 THERMAL_TYPE_NI,
1297 THERMAL_TYPE_SI,
1298 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1299 THERMAL_TYPE_CI,
1300 THERMAL_TYPE_KV,
1301};
1302
1303enum amdgpu_dpm_auto_throttle_src {
1304 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1305 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1306};
1307
1308enum amdgpu_dpm_event_src {
1309 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1310 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1311 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1312 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1313 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1314};
1315
1316#define AMDGPU_MAX_VCE_LEVELS 6
1317
1318enum amdgpu_vce_level {
1319 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1320 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1321 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1322 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1323 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1324 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1325};
1326
1327struct amdgpu_ps {
1328 u32 caps; /* vbios flags */
1329 u32 class; /* vbios flags */
1330 u32 class2; /* vbios flags */
1331 /* UVD clocks */
1332 u32 vclk;
1333 u32 dclk;
1334 /* VCE clocks */
1335 u32 evclk;
1336 u32 ecclk;
1337 bool vce_active;
1338 enum amdgpu_vce_level vce_level;
1339 /* asic priv */
1340 void *ps_priv;
1341};
1342
1343struct amdgpu_dpm_thermal {
1344 /* thermal interrupt work */
1345 struct work_struct work;
1346 /* low temperature threshold */
1347 int min_temp;
1348 /* high temperature threshold */
1349 int max_temp;
1350 /* was last interrupt low to high or high to low */
1351 bool high_to_low;
1352 /* interrupt source */
1353 struct amdgpu_irq_src irq;
1354};
1355
1356enum amdgpu_clk_action
1357{
1358 AMDGPU_SCLK_UP = 1,
1359 AMDGPU_SCLK_DOWN
1360};
1361
1362struct amdgpu_blacklist_clocks
1363{
1364 u32 sclk;
1365 u32 mclk;
1366 enum amdgpu_clk_action action;
1367};
1368
1369struct amdgpu_clock_and_voltage_limits {
1370 u32 sclk;
1371 u32 mclk;
1372 u16 vddc;
1373 u16 vddci;
1374};
1375
1376struct amdgpu_clock_array {
1377 u32 count;
1378 u32 *values;
1379};
1380
1381struct amdgpu_clock_voltage_dependency_entry {
1382 u32 clk;
1383 u16 v;
1384};
1385
1386struct amdgpu_clock_voltage_dependency_table {
1387 u32 count;
1388 struct amdgpu_clock_voltage_dependency_entry *entries;
1389};
1390
1391union amdgpu_cac_leakage_entry {
1392 struct {
1393 u16 vddc;
1394 u32 leakage;
1395 };
1396 struct {
1397 u16 vddc1;
1398 u16 vddc2;
1399 u16 vddc3;
1400 };
1401};
1402
1403struct amdgpu_cac_leakage_table {
1404 u32 count;
1405 union amdgpu_cac_leakage_entry *entries;
1406};
1407
1408struct amdgpu_phase_shedding_limits_entry {
1409 u16 voltage;
1410 u32 sclk;
1411 u32 mclk;
1412};
1413
1414struct amdgpu_phase_shedding_limits_table {
1415 u32 count;
1416 struct amdgpu_phase_shedding_limits_entry *entries;
1417};
1418
1419struct amdgpu_uvd_clock_voltage_dependency_entry {
1420 u32 vclk;
1421 u32 dclk;
1422 u16 v;
1423};
1424
1425struct amdgpu_uvd_clock_voltage_dependency_table {
1426 u8 count;
1427 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1428};
1429
1430struct amdgpu_vce_clock_voltage_dependency_entry {
1431 u32 ecclk;
1432 u32 evclk;
1433 u16 v;
1434};
1435
1436struct amdgpu_vce_clock_voltage_dependency_table {
1437 u8 count;
1438 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1439};
1440
1441struct amdgpu_ppm_table {
1442 u8 ppm_design;
1443 u16 cpu_core_number;
1444 u32 platform_tdp;
1445 u32 small_ac_platform_tdp;
1446 u32 platform_tdc;
1447 u32 small_ac_platform_tdc;
1448 u32 apu_tdp;
1449 u32 dgpu_tdp;
1450 u32 dgpu_ulv_power;
1451 u32 tj_max;
1452};
1453
1454struct amdgpu_cac_tdp_table {
1455 u16 tdp;
1456 u16 configurable_tdp;
1457 u16 tdc;
1458 u16 battery_power_limit;
1459 u16 small_power_limit;
1460 u16 low_cac_leakage;
1461 u16 high_cac_leakage;
1462 u16 maximum_power_delivery_limit;
1463};
1464
1465struct amdgpu_dpm_dynamic_state {
1466 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1467 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1468 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1469 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1470 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1471 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1472 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1473 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1474 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1475 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1476 struct amdgpu_clock_array valid_sclk_values;
1477 struct amdgpu_clock_array valid_mclk_values;
1478 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1479 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1480 u32 mclk_sclk_ratio;
1481 u32 sclk_mclk_delta;
1482 u16 vddc_vddci_delta;
1483 u16 min_vddc_for_pcie_gen2;
1484 struct amdgpu_cac_leakage_table cac_leakage_table;
1485 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1486 struct amdgpu_ppm_table *ppm_table;
1487 struct amdgpu_cac_tdp_table *cac_tdp_table;
1488};
1489
1490struct amdgpu_dpm_fan {
1491 u16 t_min;
1492 u16 t_med;
1493 u16 t_high;
1494 u16 pwm_min;
1495 u16 pwm_med;
1496 u16 pwm_high;
1497 u8 t_hyst;
1498 u32 cycle_delay;
1499 u16 t_max;
1500 u8 control_mode;
1501 u16 default_max_fan_pwm;
1502 u16 default_fan_output_sensitivity;
1503 u16 fan_output_sensitivity;
1504 bool ucode_fan_control;
1505};
1506
1507enum amdgpu_pcie_gen {
1508 AMDGPU_PCIE_GEN1 = 0,
1509 AMDGPU_PCIE_GEN2 = 1,
1510 AMDGPU_PCIE_GEN3 = 2,
1511 AMDGPU_PCIE_GEN_INVALID = 0xffff
1512};
1513
1514enum amdgpu_dpm_forced_level {
1515 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1516 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1517 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1518 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1519};
1520
1521struct amdgpu_vce_state {
1522 /* vce clocks */
1523 u32 evclk;
1524 u32 ecclk;
1525 /* gpu clocks */
1526 u32 sclk;
1527 u32 mclk;
1528 u8 clk_idx;
1529 u8 pstate;
1530};
1531
1532struct amdgpu_dpm_funcs {
1533 int (*get_temperature)(struct amdgpu_device *adev);
1534 int (*pre_set_power_state)(struct amdgpu_device *adev);
1535 int (*set_power_state)(struct amdgpu_device *adev);
1536 void (*post_set_power_state)(struct amdgpu_device *adev);
1537 void (*display_configuration_changed)(struct amdgpu_device *adev);
1538 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1539 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1540 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1541 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1542 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1543 bool (*vblank_too_short)(struct amdgpu_device *adev);
1544 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1545 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1546 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1547 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1548 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1549 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1550 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
c85e299f
EH		 1551 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1552 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
8b2e574d
EH		 1553 int (*get_sclk_od)(struct amdgpu_device *adev);
1554 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
f2bdc05f
EH		 1555 int (*get_mclk_od)(struct amdgpu_device *adev);
1556 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
97b2e202
AD		 1557};
1558
1559struct amdgpu_dpm {
1560 struct amdgpu_ps *ps;
1561 /* number of valid power states */
1562 int num_ps;
1563 /* current power state that is active */
1564 struct amdgpu_ps *current_ps;
1565 /* requested power state */
1566 struct amdgpu_ps *requested_ps;
1567 /* boot up power state */
1568 struct amdgpu_ps *boot_ps;
1569 /* default uvd power state */
1570 struct amdgpu_ps *uvd_ps;
1571 /* vce requirements */
1572 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1573 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1574 enum amd_pm_state_type state;
1575 enum amd_pm_state_type user_state;
97b2e202
AD		 1576 u32 platform_caps;
1577 u32 voltage_response_time;
1578 u32 backbias_response_time;
1579 void *priv;
1580 u32 new_active_crtcs;
1581 int new_active_crtc_count;
1582 u32 current_active_crtcs;
1583 int current_active_crtc_count;
1584 struct amdgpu_dpm_dynamic_state dyn_state;
1585 struct amdgpu_dpm_fan fan;
1586 u32 tdp_limit;
1587 u32 near_tdp_limit;
1588 u32 near_tdp_limit_adjusted;
1589 u32 sq_ramping_threshold;
1590 u32 cac_leakage;
1591 u16 tdp_od_limit;
1592 u32 tdp_adjustment;
1593 u16 load_line_slope;
1594 bool power_control;
1595 bool ac_power;
1596 /* special states active */
1597 bool thermal_active;
1598 bool uvd_active;
1599 bool vce_active;
1600 /* thermal handling */
1601 struct amdgpu_dpm_thermal thermal;
1602 /* forced levels */
1603 enum amdgpu_dpm_forced_level forced_level;
1604};
1605
1606struct amdgpu_pm {
1607 struct mutex mutex;
97b2e202
AD		 1608 u32 current_sclk;
1609 u32 current_mclk;
1610 u32 default_sclk;
1611 u32 default_mclk;
1612 struct amdgpu_i2c_chan *i2c_bus;
1613 /* internal thermal controller on rv6xx+ */
1614 enum amdgpu_int_thermal_type int_thermal_type;
1615 struct device *int_hwmon_dev;
1616 /* fan control parameters */
1617 bool no_fan;
1618 u8 fan_pulses_per_revolution;
1619 u8 fan_min_rpm;
1620 u8 fan_max_rpm;
1621 /* dpm */
1622 bool dpm_enabled;
c86f5ebf 1623 bool sysfs_initialized;
97b2e202
AD		 1624 struct amdgpu_dpm dpm;
1625 const struct firmware *fw; /* SMC firmware */
1626 uint32_t fw_version;
1627 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1628 uint32_t pcie_gen_mask;
1629 uint32_t pcie_mlw_mask;
7fb72a1f 1630 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1631};
1632
d0dd7f0c
AD		 1633void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1634
97b2e202
AD		 1635/*
1636 * UVD
1637 */
c0365541
AN		 1638#define AMDGPU_DEFAULT_UVD_HANDLES 10
1639#define AMDGPU_MAX_UVD_HANDLES 40
1640#define AMDGPU_UVD_STACK_SIZE (200*1024)
1641#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1642#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1643#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1644
1645struct amdgpu_uvd {
1646 struct amdgpu_bo *vcpu_bo;
1647 void *cpu_addr;
1648 uint64_t gpu_addr;
562e2689 1649 unsigned fw_version;
3f99dd81 1650 void *saved_bo;
c0365541 1651 unsigned max_handles;
97b2e202
AD		 1652 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1653 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1654 struct delayed_work idle_work;
1655 const struct firmware *fw; /* UVD firmware */
1656 struct amdgpu_ring ring;
1657 struct amdgpu_irq_src irq;
1658 bool address_64_bit;
4cb5877c 1659 bool use_ctx_buf;
ead833ec 1660 struct amd_sched_entity entity;
fc0b3b90 1661 uint32_t srbm_soft_reset;
97b2e202
AD		 1662};
1663
1664/*
1665 * VCE
1666 */
1667#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1668#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1669
6a585777
AD		 1670#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1671#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1672
97b2e202
AD		 1673struct amdgpu_vce {
1674 struct amdgpu_bo *vcpu_bo;
1675 uint64_t gpu_addr;
1676 unsigned fw_version;
1677 unsigned fb_version;
1678 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1679 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1680 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202 1681 struct delayed_work idle_work;
ebff485e 1682 struct mutex idle_mutex;
97b2e202
AD		 1683 const struct firmware *fw; /* VCE firmware */
1684 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1685 struct amdgpu_irq_src irq;
6a585777 1686 unsigned harvest_config;
c594989c 1687 struct amd_sched_entity entity;
115933a5 1688 uint32_t srbm_soft_reset;
97b2e202
AD		 1689};
1690
1691/*
1692 * SDMA
1693 */
c113ea1c 1694struct amdgpu_sdma_instance {
97b2e202
AD		 1695 /* SDMA firmware */
1696 const struct firmware *fw;
1697 uint32_t fw_version;
cfa2104f 1698 uint32_t feature_version;
97b2e202
AD		 1699
1700 struct amdgpu_ring ring;
18111de0 1701 bool burst_nop;
97b2e202
AD		 1702};
1703
c113ea1c
AD		 1704struct amdgpu_sdma {
1705 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1706 struct amdgpu_irq_src trap_irq;
1707 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1708 int num_instances;
e702a680 1709 uint32_t srbm_soft_reset;
c113ea1c
AD		 1710};
1711
97b2e202
AD		 1712/*
1713 * Firmware
1714 */
1715struct amdgpu_firmware {
1716 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1717 bool smu_load;
1718 struct amdgpu_bo *fw_buf;
1719 unsigned int fw_size;
1720};
1721
1722/*
1723 * Benchmarking
1724 */
1725void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1726
1727
1728/*
1729 * Testing
1730 */
1731void amdgpu_test_moves(struct amdgpu_device *adev);
1732void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1733 struct amdgpu_ring *cpA,
1734 struct amdgpu_ring *cpB);
1735void amdgpu_test_syncing(struct amdgpu_device *adev);
1736
1737/*
1738 * MMU Notifier
1739 */
1740#if defined(CONFIG_MMU_NOTIFIER)
1741int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1742void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1743#else
1d1106b0 1744static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1745{
1746 return -ENODEV;
1747}
1d1106b0 1748static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1749#endif
1750
1751/*
1752 * Debugfs
1753 */
1754struct amdgpu_debugfs {
06ab6832 1755 const struct drm_info_list *files;
97b2e202
AD		 1756 unsigned num_files;
1757};
1758
1759int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1760 const struct drm_info_list *files,
97b2e202
AD		 1761 unsigned nfiles);
1762int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1763
1764#if defined(CONFIG_DEBUG_FS)
1765int amdgpu_debugfs_init(struct drm_minor *minor);
1766void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1767#endif
1768
50ab2533
HR		 1769int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1770
97b2e202
AD		 1771/*
1772 * amdgpu smumgr functions
1773 */
1774struct amdgpu_smumgr_funcs {
1775 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1776 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1777 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1778};
1779
1780/*
1781 * amdgpu smumgr
1782 */
1783struct amdgpu_smumgr {
1784 struct amdgpu_bo *toc_buf;
1785 struct amdgpu_bo *smu_buf;
1786 /* asic priv smu data */
1787 void *priv;
1788 spinlock_t smu_lock;
1789 /* smumgr functions */
1790 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1791 /* ucode loading complete flag */
1792 uint32_t fw_flags;
1793};
1794
1795/*
1796 * ASIC specific register table accessible by UMD
1797 */
1798struct amdgpu_allowed_register_entry {
1799 uint32_t reg_offset;
1800 bool untouched;
1801 bool grbm_indexed;
1802};
1803
97b2e202
AD		 1804/*
1805 * ASIC specific functions.
1806 */
1807struct amdgpu_asic_funcs {
1808 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1809 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1810 u8 *bios, u32 length_bytes);
97b2e202
AD		 1811 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1812 u32 sh_num, u32 reg_offset, u32 *value);
1813 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1814 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1815 /* get the reference clock */
1816 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1817 /* MM block clocks */
1818 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1819 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
048765ad
AR		 1820 /* query virtual capabilities */
1821 u32 (*get_virtual_caps)(struct amdgpu_device *adev);
97b2e202
AD		 1822};
1823
1824/*
1825 * IOCTL.
1826 */
1827int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1828 struct drm_file *filp);
1829int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831
1832int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1834int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1835 struct drm_file *filp);
1836int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *filp);
1838int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1839 struct drm_file *filp);
1840int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1845int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1846
1847int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849
1850/* VRAM scratch page for HDP bug, default vram page */
1851struct amdgpu_vram_scratch {
1852 struct amdgpu_bo *robj;
1853 volatile uint32_t *ptr;
1854 u64 gpu_addr;
1855};
1856
1857/*
1858 * ACPI
1859 */
1860struct amdgpu_atif_notification_cfg {
1861 bool enabled;
1862 int command_code;
1863};
1864
1865struct amdgpu_atif_notifications {
1866 bool display_switch;
1867 bool expansion_mode_change;
1868 bool thermal_state;
1869 bool forced_power_state;
1870 bool system_power_state;
1871 bool display_conf_change;
1872 bool px_gfx_switch;
1873 bool brightness_change;
1874 bool dgpu_display_event;
1875};
1876
1877struct amdgpu_atif_functions {
1878 bool system_params;
1879 bool sbios_requests;
1880 bool select_active_disp;
1881 bool lid_state;
1882 bool get_tv_standard;
1883 bool set_tv_standard;
1884 bool get_panel_expansion_mode;
1885 bool set_panel_expansion_mode;
1886 bool temperature_change;
1887 bool graphics_device_types;
1888};
1889
1890struct amdgpu_atif {
1891 struct amdgpu_atif_notifications notifications;
1892 struct amdgpu_atif_functions functions;
1893 struct amdgpu_atif_notification_cfg notification_cfg;
1894 struct amdgpu_encoder *encoder_for_bl;
1895};
1896
1897struct amdgpu_atcs_functions {
1898 bool get_ext_state;
1899 bool pcie_perf_req;
1900 bool pcie_dev_rdy;
1901 bool pcie_bus_width;
1902};
1903
1904struct amdgpu_atcs {
1905 struct amdgpu_atcs_functions functions;
1906};
1907
d03846af
CZ		 1908/*
1909 * CGS
1910 */
110e6f26
DA		 1911struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1912void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce
MB		 1913
1914
7e471e6f 1915/* GPU virtualization */
048765ad
AR		 1916#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1917#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
7e471e6f
AD		 1918struct amdgpu_virtualization {
1919 bool supports_sr_iov;
048765ad
AR		 1920 bool is_virtual;
1921 u32 caps;
7e471e6f
AD		 1922};
1923
97b2e202
AD		 1924/*
1925 * Core structure, functions and helpers.
1926 */
1927typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1928typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1929
1930typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1931typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1932
8faf0e08
AD		 1933struct amdgpu_ip_block_status {
1934 bool valid;
1935 bool sw;
1936 bool hw;
63fbf42f 1937 bool hang;
8faf0e08
AD		 1938};
1939
97b2e202
AD		 1940struct amdgpu_device {
1941 struct device *dev;
1942 struct drm_device *ddev;
1943 struct pci_dev *pdev;
97b2e202 1944
a8fe58ce
MB		 1945#ifdef CONFIG_DRM_AMD_ACP
1946 struct amdgpu_acp acp;
1947#endif
1948
97b2e202 1949 /* ASIC */
2f7d10b3 1950 enum amd_asic_type asic_type;
97b2e202
AD		 1951 uint32_t family;
1952 uint32_t rev_id;
1953 uint32_t external_rev_id;
1954 unsigned long flags;
1955 int usec_timeout;
1956 const struct amdgpu_asic_funcs *asic_funcs;
1957 bool shutdown;
97b2e202
AD		 1958 bool need_dma32;
1959 bool accel_working;
edf600da 1960 struct work_struct reset_work;
97b2e202
AD		 1961 struct notifier_block acpi_nb;
1962 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1963 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1964 unsigned debugfs_count;
97b2e202 1965#if defined(CONFIG_DEBUG_FS)
adcec288 1966 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1967#endif
1968 struct amdgpu_atif atif;
1969 struct amdgpu_atcs atcs;
1970 struct mutex srbm_mutex;
1971 /* GRBM index mutex. Protects concurrent access to GRBM index */
1972 struct mutex grbm_idx_mutex;
1973 struct dev_pm_domain vga_pm_domain;
1974 bool have_disp_power_ref;
1975
1976 /* BIOS */
1977 uint8_t *bios;
1978 bool is_atom_bios;
97b2e202
AD		 1979 struct amdgpu_bo *stollen_vga_memory;
1980 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1981
1982 /* Register/doorbell mmio */
1983 resource_size_t rmmio_base;
1984 resource_size_t rmmio_size;
1985 void __iomem *rmmio;
1986 /* protects concurrent MM_INDEX/DATA based register access */
1987 spinlock_t mmio_idx_lock;
1988 /* protects concurrent SMC based register access */
1989 spinlock_t smc_idx_lock;
1990 amdgpu_rreg_t smc_rreg;
1991 amdgpu_wreg_t smc_wreg;
1992 /* protects concurrent PCIE register access */
1993 spinlock_t pcie_idx_lock;
1994 amdgpu_rreg_t pcie_rreg;
1995 amdgpu_wreg_t pcie_wreg;
1996 /* protects concurrent UVD register access */
1997 spinlock_t uvd_ctx_idx_lock;
1998 amdgpu_rreg_t uvd_ctx_rreg;
1999 amdgpu_wreg_t uvd_ctx_wreg;
2000 /* protects concurrent DIDT register access */
2001 spinlock_t didt_idx_lock;
2002 amdgpu_rreg_t didt_rreg;
2003 amdgpu_wreg_t didt_wreg;
ccdbb20a
RZ		 2004 /* protects concurrent gc_cac register access */
2005 spinlock_t gc_cac_idx_lock;
2006 amdgpu_rreg_t gc_cac_rreg;
2007 amdgpu_wreg_t gc_cac_wreg;
97b2e202
AD		 2008 /* protects concurrent ENDPOINT (audio) register access */
2009 spinlock_t audio_endpt_idx_lock;
2010 amdgpu_block_rreg_t audio_endpt_rreg;
2011 amdgpu_block_wreg_t audio_endpt_wreg;
2012 void __iomem *rio_mem;
2013 resource_size_t rio_mem_size;
2014 struct amdgpu_doorbell doorbell;
2015
2016 /* clock/pll info */
2017 struct amdgpu_clock clock;
2018
2019 /* MC */
2020 struct amdgpu_mc mc;
2021 struct amdgpu_gart gart;
2022 struct amdgpu_dummy_page dummy_page;
2023 struct amdgpu_vm_manager vm_manager;
2024
2025 /* memory management */
2026 struct amdgpu_mman mman;
97b2e202
AD		 2027 struct amdgpu_vram_scratch vram_scratch;
2028 struct amdgpu_wb wb;
2029 atomic64_t vram_usage;
2030 atomic64_t vram_vis_usage;
2031 atomic64_t gtt_usage;
2032 atomic64_t num_bytes_moved;
dbd5ed60 2033 atomic64_t num_evictions;
d94aed5a 2034 atomic_t gpu_reset_counter;
97b2e202
AD		 2035
2036 /* display */
9accf2fd 2037 bool enable_virtual_display;
97b2e202
AD		 2038 struct amdgpu_mode_info mode_info;
2039 struct work_struct hotplug_work;
2040 struct amdgpu_irq_src crtc_irq;
2041 struct amdgpu_irq_src pageflip_irq;
2042 struct amdgpu_irq_src hpd_irq;
2043
2044 /* rings */
76bf0db5 2045 u64 fence_context;
97b2e202
AD		 2046 unsigned num_rings;
2047 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2048 bool ib_pool_ready;
2049 struct amdgpu_sa_manager ring_tmp_bo;
2050
2051 /* interrupts */
2052 struct amdgpu_irq irq;
2053
1f7371b2
AD		 2054 /* powerplay */
2055 struct amd_powerplay powerplay;
e61710c5 2056 bool pp_enabled;
f3898ea1 2057 bool pp_force_state_enabled;
1f7371b2 2058
97b2e202
AD		 2059 /* dpm */
2060 struct amdgpu_pm pm;
2061 u32 cg_flags;
2062 u32 pg_flags;
2063
2064 /* amdgpu smumgr */
2065 struct amdgpu_smumgr smu;
2066
2067 /* gfx */
2068 struct amdgpu_gfx gfx;
2069
2070 /* sdma */
c113ea1c 2071 struct amdgpu_sdma sdma;
97b2e202
AD		 2072
2073 /* uvd */
97b2e202
AD		 2074 struct amdgpu_uvd uvd;
2075
2076 /* vce */
2077 struct amdgpu_vce vce;
2078
2079 /* firmwares */
2080 struct amdgpu_firmware firmware;
2081
2082 /* GDS */
2083 struct amdgpu_gds gds;
2084
2085 const struct amdgpu_ip_block_version *ip_blocks;
2086 int num_ip_blocks;
8faf0e08 2087 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2088 struct mutex mn_lock;
2089 DECLARE_HASHTABLE(mn_hash, 7);
2090
2091 /* tracking pinned memory */
2092 u64 vram_pin_size;
e131b914 2093 u64 invisible_pin_size;
97b2e202 2094 u64 gart_pin_size;
130e0371
OG		 2095
2096 /* amdkfd interface */
2097 struct kfd_dev *kfd;
23ca0e4e 2098
7e471e6f 2099 struct amdgpu_virtualization virtualization;
0c4e7fa5
CZ		 2100
2101 /* link all shadow bo */
2102 struct list_head shadow_list;
2103 struct mutex shadow_list_lock;
97b2e202
AD		 2104};
2105
2106bool amdgpu_device_is_px(struct drm_device *dev);
2107int amdgpu_device_init(struct amdgpu_device *adev,
2108 struct drm_device *ddev,
2109 struct pci_dev *pdev,
2110 uint32_t flags);
2111void amdgpu_device_fini(struct amdgpu_device *adev);
2112int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2113
2114uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2115 bool always_indirect);
2116void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2117 bool always_indirect);
2118u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2119void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2120
2121u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2122void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2123
97b2e202
AD		 2124/*
2125 * Registers read & write functions.
2126 */
2127#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2128#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2129#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2130#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2131#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2132#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2133#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2134#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2135#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2136#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2137#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2138#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2139#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2140#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2141#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
ccdbb20a
RZ		 2142#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2143#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
97b2e202
AD		 2144#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2145#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2146#define WREG32_P(reg, val, mask) \
2147 do { \
2148 uint32_t tmp_ = RREG32(reg); \
2149 tmp_ &= (mask); \
2150 tmp_ |= ((val) & ~(mask)); \
2151 WREG32(reg, tmp_); \
2152 } while (0)
2153#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2154#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2155#define WREG32_PLL_P(reg, val, mask) \
2156 do { \
2157 uint32_t tmp_ = RREG32_PLL(reg); \
2158 tmp_ &= (mask); \
2159 tmp_ |= ((val) & ~(mask)); \
2160 WREG32_PLL(reg, tmp_); \
2161 } while (0)
2162#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2163#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2164#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2165
2166#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2167#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2168
2169#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2170#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2171
2172#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2173 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2174 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2175
2176#define REG_GET_FIELD(value, reg, field) \
2177 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2178
61cb8cef
TSD		 2179#define WREG32_FIELD(reg, field, val) \
2180 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
97b2e202
AD		 2181
2182/*
2183 * BIOS helpers.
2184 */
2185#define RBIOS8(i) (adev->bios[i])
2186#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2187#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2188
2189/*
2190 * RING helpers.
2191 */
2192static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2193{
2194 if (ring->count_dw <= 0)
86c2b790 2195 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2196 ring->ring[ring->wptr++] = v;
2197 ring->wptr &= ring->ptr_mask;
2198 ring->count_dw--;
97b2e202
AD		 2199}
2200
c113ea1c
AD		 2201static inline struct amdgpu_sdma_instance *
2202amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2203{
2204 struct amdgpu_device *adev = ring->adev;
2205 int i;
2206
c113ea1c
AD		 2207 for (i = 0; i < adev->sdma.num_instances; i++)
2208 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2209 break;
2210
2211 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2212 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2213 else
2214 return NULL;
2215}
2216
97b2e202
AD		 2217/*
2218 * ASICs macro.
2219 */
2220#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2221#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 2222#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2223#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2224#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
048765ad 2225#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
97b2e202 2226#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2227#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 2228#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
97b2e202
AD		 2229#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2230#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2231#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
de9ea7bd 2232#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
97b2e202 2233#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2234#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2235#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
bbec97aa 2236#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
97b2e202
AD		 2237#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2238#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2239#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 2240#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 2241#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2242#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2243#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2244#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2245#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2246#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2247#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 2248#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2249#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 2250#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2251#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2252#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2253#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2254#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2255#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2256#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2257#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2258#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2259#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2260#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2261#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2262#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 2263#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 2264#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2265#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2266#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2267#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2268#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2269#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2270#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2271#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2272#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2273#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2274#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2275#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2276#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2277#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
b95e31fd 2278#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
9559ef5b 2279#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
3af76f23
RZ		 2280
2281#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2282 ((adev)->pp_enabled ? \
e61710c5 2283 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2284 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2285
2286#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2287 ((adev)->pp_enabled ? \
e61710c5 2288 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2289 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2290
2291#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2292 ((adev)->pp_enabled ? \
e61710c5 2293 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2294 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2295
2296#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2297 ((adev)->pp_enabled ? \
e61710c5 2298 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2299 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2300
2301#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2302 ((adev)->pp_enabled ? \
e61710c5 2303 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2304 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2305
1b5708ff 2306#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2307 ((adev)->pp_enabled ? \
e61710c5 2308 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2309 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2310
2311#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2312 ((adev)->pp_enabled ? \
e61710c5 2313 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2314 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2315
2316
2317#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2318 ((adev)->pp_enabled ? \
e61710c5 2319 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2320 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2321
2322#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2323 ((adev)->pp_enabled ? \
e61710c5 2324 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2325 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2326
2327#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2328 ((adev)->pp_enabled ? \
e61710c5 2329 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2330 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2331
2332#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2333 ((adev)->pp_enabled ? \
e61710c5 2334 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2335 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2336
2337#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2338 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2339
2340#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2341 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2342
f3898ea1
EH		 2343#define amdgpu_dpm_get_pp_num_states(adev, data) \
2344 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2345
2346#define amdgpu_dpm_get_pp_table(adev, table) \
2347 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2348
2349#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2350 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2351
2352#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2353 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2354
2355#define amdgpu_dpm_force_clock_level(adev, type, level) \
2356 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2357
428bafa8
EH		 2358#define amdgpu_dpm_get_sclk_od(adev) \
2359 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2360
2361#define amdgpu_dpm_set_sclk_od(adev, value) \
2362 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2363
f2bdc05f
EH		 2364#define amdgpu_dpm_get_mclk_od(adev) \
2365 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2366
2367#define amdgpu_dpm_set_mclk_od(adev, value) \
2368 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2369
e61710c5 2370#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2371 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2372
2373#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2374
2375/* Common functions */
2376int amdgpu_gpu_reset(struct amdgpu_device *adev);
3ad81f16 2377bool amdgpu_need_backup(struct amdgpu_device *adev);
97b2e202
AD		 2378void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2379bool amdgpu_card_posted(struct amdgpu_device *adev);
2380void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2381
97b2e202
AD		 2382int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2383int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2384 u32 ip_instance, u32 ring,
2385 struct amdgpu_ring **out_ring);
2386void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2387bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2388int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2389int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2390 uint32_t flags);
2391bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 2392struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2393bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2394 unsigned long end);
2f568dbd
CK		 2395bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2396 int *last_invalidated);
97b2e202
AD		 2397bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2398uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2399 struct ttm_mem_reg *mem);
2400void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2401void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2402void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
a693e050
KW		 2403u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
2404int amdgpu_ttm_global_init(struct amdgpu_device *adev);
97b2e202
AD		 2405void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2406 const u32 *registers,
2407 const u32 array_size);
2408
2409bool amdgpu_device_is_px(struct drm_device *dev);
2410/* atpx handler */
2411#if defined(CONFIG_VGA_SWITCHEROO)
2412void amdgpu_register_atpx_handler(void);
2413void amdgpu_unregister_atpx_handler(void);
a78fe133 2414bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 2415bool amdgpu_is_atpx_hybrid(void);
97b2e202
AD		 2416#else
2417static inline void amdgpu_register_atpx_handler(void) {}
2418static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 2419static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 2420static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
97b2e202
AD		 2421#endif
2422
2423/*
2424 * KMS
2425 */
2426extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 2427extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 2428
2429int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2430int amdgpu_driver_unload_kms(struct drm_device *dev);
2431void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2432int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2433void amdgpu_driver_postclose_kms(struct drm_device *dev,
2434 struct drm_file *file_priv);
2435void amdgpu_driver_preclose_kms(struct drm_device *dev,
2436 struct drm_file *file_priv);
2437int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2438int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2439u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2440int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2441void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2442int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2443 int *max_error,
2444 struct timeval *vblank_time,
2445 unsigned flags);
2446long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2447 unsigned long arg);
2448
97b2e202
AD		 2449/*
2450 * functions used by amdgpu_encoder.c
2451 */
2452struct amdgpu_afmt_acr {
2453 u32 clock;
2454
2455 int n_32khz;
2456 int cts_32khz;
2457
2458 int n_44_1khz;
2459 int cts_44_1khz;
2460
2461 int n_48khz;
2462 int cts_48khz;
2463
2464};
2465
2466struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2467
2468/* amdgpu_acpi.c */
2469#if defined(CONFIG_ACPI)
2470int amdgpu_acpi_init(struct amdgpu_device *adev);
2471void amdgpu_acpi_fini(struct amdgpu_device *adev);
2472bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2473int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2474 u8 perf_req, bool advertise);
2475int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2476#else
2477static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2478static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2479#endif
2480
2481struct amdgpu_bo_va_mapping *
2482amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2483 uint64_t addr, struct amdgpu_bo **bo);
2484
2485#include "amdgpu_object.h"
97b2e202 2486#endif
Linux kernel - Deliverables
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