projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: add a new set of rlc function pointers
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
cd474ba0
AD		 88extern unsigned amdgpu_pcie_gen_cap;
89extern unsigned amdgpu_pcie_lane_cap;
97b2e202 90
4b559c90 91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95#define AMDGPU_IB_POOL_SIZE 16
96#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97#define AMDGPUFB_CONN_LIMIT 4
98#define AMDGPU_BIOS_NUM_SCRATCH 8
99
97b2e202
AD		 100/* max number of rings */
101#define AMDGPU_MAX_RINGS 16
102#define AMDGPU_MAX_GFX_RINGS 1
103#define AMDGPU_MAX_COMPUTE_RINGS 8
104#define AMDGPU_MAX_VCE_RINGS 2
105
36f523a7
JZ		 106/* max number of IP instances */
107#define AMDGPU_MAX_SDMA_INSTANCES 2
108
97b2e202
AD		 109/* hardcode that limit for now */
110#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112/* hard reset data */
113#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115/* reset flags */
116#define AMDGPU_RESET_GFX (1 << 0)
117#define AMDGPU_RESET_COMPUTE (1 << 1)
118#define AMDGPU_RESET_DMA (1 << 2)
119#define AMDGPU_RESET_CP (1 << 3)
120#define AMDGPU_RESET_GRBM (1 << 4)
121#define AMDGPU_RESET_DMA1 (1 << 5)
122#define AMDGPU_RESET_RLC (1 << 6)
123#define AMDGPU_RESET_SEM (1 << 7)
124#define AMDGPU_RESET_IH (1 << 8)
125#define AMDGPU_RESET_VMC (1 << 9)
126#define AMDGPU_RESET_MC (1 << 10)
127#define AMDGPU_RESET_DISPLAY (1 << 11)
128#define AMDGPU_RESET_UVD (1 << 12)
129#define AMDGPU_RESET_VCE (1 << 13)
130#define AMDGPU_RESET_VCE1 (1 << 14)
131
97b2e202
AD		 132/* GFX current status */
133#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
134#define AMDGPU_GFX_SAFE_MODE 0x00000001L
135#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
136#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
137#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
138
139/* max cursor sizes (in pixels) */
140#define CIK_CURSOR_WIDTH 128
141#define CIK_CURSOR_HEIGHT 128
142
143struct amdgpu_device;
97b2e202
AD		 144struct amdgpu_ib;
145struct amdgpu_vm;
146struct amdgpu_ring;
97b2e202 147struct amdgpu_cs_parser;
bb977d37 148struct amdgpu_job;
97b2e202 149struct amdgpu_irq_src;
0b492a4c 150struct amdgpu_fpriv;
97b2e202
AD		 151
152enum amdgpu_cp_irq {
153 AMDGPU_CP_IRQ_GFX_EOP = 0,
154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
162
163 AMDGPU_CP_IRQ_LAST
164};
165
166enum amdgpu_sdma_irq {
167 AMDGPU_SDMA_IRQ_TRAP0 = 0,
168 AMDGPU_SDMA_IRQ_TRAP1,
169
170 AMDGPU_SDMA_IRQ_LAST
171};
172
173enum amdgpu_thermal_irq {
174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
176
177 AMDGPU_THERMAL_IRQ_LAST
178};
179
97b2e202 180int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 181 enum amd_ip_block_type block_type,
182 enum amd_clockgating_state state);
97b2e202 183int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 184 enum amd_ip_block_type block_type,
185 enum amd_powergating_state state);
97b2e202
AD		 186
187struct amdgpu_ip_block_version {
5fc3aeeb 188 enum amd_ip_block_type type;
97b2e202
AD		 189 u32 major;
190 u32 minor;
191 u32 rev;
5fc3aeeb 192 const struct amd_ip_funcs *funcs;
97b2e202
AD		 193};
194
195int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 196 enum amd_ip_block_type type,
97b2e202
AD		 197 u32 major, u32 minor);
198
199const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
200 struct amdgpu_device *adev,
5fc3aeeb 201 enum amd_ip_block_type type);
97b2e202
AD		 202
203/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
204struct amdgpu_buffer_funcs {
205 /* maximum bytes in a single operation */
206 uint32_t copy_max_bytes;
207
208 /* number of dw to reserve per operation */
209 unsigned copy_num_dw;
210
211 /* used for buffer migration */
c7ae72c0 212 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 213 /* src addr in bytes */
214 uint64_t src_offset,
215 /* dst addr in bytes */
216 uint64_t dst_offset,
217 /* number of byte to transfer */
218 uint32_t byte_count);
219
220 /* maximum bytes in a single operation */
221 uint32_t fill_max_bytes;
222
223 /* number of dw to reserve per operation */
224 unsigned fill_num_dw;
225
226 /* used for buffer clearing */
6e7a3840 227 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 228 /* value to write to memory */
229 uint32_t src_data,
230 /* dst addr in bytes */
231 uint64_t dst_offset,
232 /* number of byte to fill */
233 uint32_t byte_count);
234};
235
236/* provided by hw blocks that can write ptes, e.g., sdma */
237struct amdgpu_vm_pte_funcs {
238 /* copy pte entries from GART */
239 void (*copy_pte)(struct amdgpu_ib *ib,
240 uint64_t pe, uint64_t src,
241 unsigned count);
242 /* write pte one entry at a time with addr mapping */
243 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 244 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 245 uint64_t addr, unsigned count,
246 uint32_t incr, uint32_t flags);
247 /* for linear pte/pde updates without addr mapping */
248 void (*set_pte_pde)(struct amdgpu_ib *ib,
249 uint64_t pe,
250 uint64_t addr, unsigned count,
251 uint32_t incr, uint32_t flags);
97b2e202
AD		 252};
253
254/* provided by the gmc block */
255struct amdgpu_gart_funcs {
256 /* flush the vm tlb via mmio */
257 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
258 uint32_t vmid);
259 /* write pte/pde updates using the cpu */
260 int (*set_pte_pde)(struct amdgpu_device *adev,
261 void *cpu_pt_addr, /* cpu addr of page table */
262 uint32_t gpu_page_idx, /* pte/pde to update */
263 uint64_t addr, /* addr to write into pte/pde */
264 uint32_t flags); /* access flags */
265};
266
267/* provided by the ih block */
268struct amdgpu_ih_funcs {
269 /* ring read/write ptr handling, called from interrupt context */
270 u32 (*get_wptr)(struct amdgpu_device *adev);
271 void (*decode_iv)(struct amdgpu_device *adev,
272 struct amdgpu_iv_entry *entry);
273 void (*set_rptr)(struct amdgpu_device *adev);
274};
275
276/* provided by hw blocks that expose a ring buffer for commands */
277struct amdgpu_ring_funcs {
278 /* ring read/write ptr handling */
279 u32 (*get_rptr)(struct amdgpu_ring *ring);
280 u32 (*get_wptr)(struct amdgpu_ring *ring);
281 void (*set_wptr)(struct amdgpu_ring *ring);
282 /* validating and patching of IBs */
283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
284 /* command emit functions */
285 void (*emit_ib)(struct amdgpu_ring *ring,
286 struct amdgpu_ib *ib);
287 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 288 uint64_t seq, unsigned flags);
b8c7b39e 289 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
291 uint64_t pd_addr);
d2edb07b 292 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 293 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 294 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
295 uint32_t gds_base, uint32_t gds_size,
296 uint32_t gws_base, uint32_t gws_size,
297 uint32_t oa_base, uint32_t oa_size);
298 /* testing functions */
299 int (*test_ring)(struct amdgpu_ring *ring);
300 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 301 /* insert NOP packets */
302 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 303 /* pad the indirect buffer to the necessary number of dw */
304 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
03ccf481
ML		 305 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
306 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
97b2e202
AD		 307};
308
309/*
310 * BIOS.
311 */
312bool amdgpu_get_bios(struct amdgpu_device *adev);
313bool amdgpu_read_bios(struct amdgpu_device *adev);
314
315/*
316 * Dummy page
317 */
318struct amdgpu_dummy_page {
319 struct page *page;
320 dma_addr_t addr;
321};
322int amdgpu_dummy_page_init(struct amdgpu_device *adev);
323void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
324
325
326/*
327 * Clocks
328 */
329
330#define AMDGPU_MAX_PPLL 3
331
332struct amdgpu_clock {
333 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
334 struct amdgpu_pll spll;
335 struct amdgpu_pll mpll;
336 /* 10 Khz units */
337 uint32_t default_mclk;
338 uint32_t default_sclk;
339 uint32_t default_dispclk;
340 uint32_t current_dispclk;
341 uint32_t dp_extclk;
342 uint32_t max_pixel_clock;
343};
344
345/*
346 * Fences.
347 */
348struct amdgpu_fence_driver {
97b2e202
AD		 349 uint64_t gpu_addr;
350 volatile uint32_t *cpu_addr;
351 /* sync_seq is protected by ring emission lock */
742c085f
CK		 352 uint32_t sync_seq;
353 atomic_t last_seq;
97b2e202 354 bool initialized;
97b2e202
AD		 355 struct amdgpu_irq_src *irq_src;
356 unsigned irq_type;
c2776afe 357 struct timer_list fallback_timer;
c89377d1 358 unsigned num_fences_mask;
4a7d74f1 359 spinlock_t lock;
c89377d1 360 struct fence **fences;
97b2e202
AD		 361};
362
363/* some special values for the owner field */
364#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
365#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 366
890ee23f
CZ		 367#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
368#define AMDGPU_FENCE_FLAG_INT (1 << 1)
369
97b2e202
AD		 370struct amdgpu_user_fence {
371 /* write-back bo */
372 struct amdgpu_bo *bo;
373 /* write-back address offset to bo start */
374 uint32_t offset;
375};
376
377int amdgpu_fence_driver_init(struct amdgpu_device *adev);
378void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
379void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
380
e6151a08
CK		 381int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
382 unsigned num_hw_submission);
97b2e202
AD		 383int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
384 struct amdgpu_irq_src *irq_src,
385 unsigned irq_type);
5ceb54c6
AD		 386void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
387void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 388int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202 389void amdgpu_fence_process(struct amdgpu_ring *ring);
97b2e202
AD		 390int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
391unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
392
97b2e202
AD		 393/*
394 * TTM.
395 */
396struct amdgpu_mman {
397 struct ttm_bo_global_ref bo_global_ref;
398 struct drm_global_reference mem_global_ref;
399 struct ttm_bo_device bdev;
400 bool mem_global_referenced;
401 bool initialized;
402
403#if defined(CONFIG_DEBUG_FS)
404 struct dentry *vram;
405 struct dentry *gtt;
406#endif
407
408 /* buffer handling */
409 const struct amdgpu_buffer_funcs *buffer_funcs;
410 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 411 /* Scheduler entity for buffer moves */
412 struct amd_sched_entity entity;
97b2e202
AD		 413};
414
415int amdgpu_copy_buffer(struct amdgpu_ring *ring,
416 uint64_t src_offset,
417 uint64_t dst_offset,
418 uint32_t byte_count,
419 struct reservation_object *resv,
c7ae72c0 420 struct fence **fence);
97b2e202
AD		 421int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
422
423struct amdgpu_bo_list_entry {
424 struct amdgpu_bo *robj;
425 struct ttm_validate_buffer tv;
426 struct amdgpu_bo_va *bo_va;
97b2e202 427 uint32_t priority;
2f568dbd
CK		 428 struct page **user_pages;
429 int user_invalidated;
97b2e202
AD		 430};
431
432struct amdgpu_bo_va_mapping {
433 struct list_head list;
434 struct interval_tree_node it;
435 uint64_t offset;
436 uint32_t flags;
437};
438
439/* bo virtual addresses in a specific vm */
440struct amdgpu_bo_va {
441 /* protected by bo being reserved */
442 struct list_head bo_list;
bb1e38a4 443 struct fence *last_pt_update;
97b2e202
AD		 444 unsigned ref_count;
445
7fc11959 446 /* protected by vm mutex and spinlock */
97b2e202
AD		 447 struct list_head vm_status;
448
7fc11959
CK		 449 /* mappings for this bo_va */
450 struct list_head invalids;
451 struct list_head valids;
452
97b2e202
AD		 453 /* constant after initialization */
454 struct amdgpu_vm *vm;
455 struct amdgpu_bo *bo;
456};
457
7e5a547f
CZ		 458#define AMDGPU_GEM_DOMAIN_MAX 0x3
459
97b2e202
AD		 460struct amdgpu_bo {
461 /* Protected by gem.mutex */
462 struct list_head list;
463 /* Protected by tbo.reserved */
1ea863fd
CK		 464 u32 prefered_domains;
465 u32 allowed_domains;
7e5a547f 466 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 467 struct ttm_placement placement;
468 struct ttm_buffer_object tbo;
469 struct ttm_bo_kmap_obj kmap;
470 u64 flags;
471 unsigned pin_count;
472 void *kptr;
473 u64 tiling_flags;
474 u64 metadata_flags;
475 void *metadata;
476 u32 metadata_size;
477 /* list of all virtual address to which this bo
478 * is associated to
479 */
480 struct list_head va;
481 /* Constant after initialization */
482 struct amdgpu_device *adev;
483 struct drm_gem_object gem_base;
82b9c55b 484 struct amdgpu_bo *parent;
97b2e202
AD		 485
486 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 487 struct amdgpu_mn *mn;
488 struct list_head mn_list;
489};
490#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
491
492void amdgpu_gem_object_free(struct drm_gem_object *obj);
493int amdgpu_gem_object_open(struct drm_gem_object *obj,
494 struct drm_file *file_priv);
495void amdgpu_gem_object_close(struct drm_gem_object *obj,
496 struct drm_file *file_priv);
497unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
498struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
499struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
500 struct dma_buf_attachment *attach,
501 struct sg_table *sg);
502struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
503 struct drm_gem_object *gobj,
504 int flags);
505int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
506void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
507struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
508void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
509void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
510int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
511
512/* sub-allocation manager, it has to be protected by another lock.
513 * By conception this is an helper for other part of the driver
514 * like the indirect buffer or semaphore, which both have their
515 * locking.
516 *
517 * Principe is simple, we keep a list of sub allocation in offset
518 * order (first entry has offset == 0, last entry has the highest
519 * offset).
520 *
521 * When allocating new object we first check if there is room at
522 * the end total_size - (last_object_offset + last_object_size) >=
523 * alloc_size. If so we allocate new object there.
524 *
525 * When there is not enough room at the end, we start waiting for
526 * each sub object until we reach object_offset+object_size >=
527 * alloc_size, this object then become the sub object we return.
528 *
529 * Alignment can't be bigger than page size.
530 *
531 * Hole are not considered for allocation to keep things simple.
532 * Assumption is that there won't be hole (all object on same
533 * alignment).
534 */
6ba60b89
CK		 535
536#define AMDGPU_SA_NUM_FENCE_LISTS 32
537
97b2e202
AD		 538struct amdgpu_sa_manager {
539 wait_queue_head_t wq;
540 struct amdgpu_bo *bo;
541 struct list_head *hole;
6ba60b89 542 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 543 struct list_head olist;
544 unsigned size;
545 uint64_t gpu_addr;
546 void *cpu_ptr;
547 uint32_t domain;
548 uint32_t align;
549};
550
97b2e202
AD		 551/* sub-allocation buffer */
552struct amdgpu_sa_bo {
553 struct list_head olist;
554 struct list_head flist;
555 struct amdgpu_sa_manager *manager;
556 unsigned soffset;
557 unsigned eoffset;
4ce9891e 558 struct fence *fence;
97b2e202
AD		 559};
560
561/*
562 * GEM objects.
563 */
418aa0c2 564void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 565int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
566 int alignment, u32 initial_domain,
567 u64 flags, bool kernel,
568 struct drm_gem_object **obj);
569
570int amdgpu_mode_dumb_create(struct drm_file *file_priv,
571 struct drm_device *dev,
572 struct drm_mode_create_dumb *args);
573int amdgpu_mode_dumb_mmap(struct drm_file *filp,
574 struct drm_device *dev,
575 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 576/*
577 * Synchronization
578 */
579struct amdgpu_sync {
f91b3a69 580 DECLARE_HASHTABLE(fences, 4);
3c62338c 581 struct fence *last_vm_update;
97b2e202
AD		 582};
583
584void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 585int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
586 struct fence *f);
97b2e202
AD		 587int amdgpu_sync_resv(struct amdgpu_device *adev,
588 struct amdgpu_sync *sync,
589 struct reservation_object *resv,
590 void *owner);
832a902f
CK		 591bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);
592int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
593 struct fence *fence);
e61235db 594struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 595int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 596void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 597int amdgpu_sync_init(void);
598void amdgpu_sync_fini(void);
97b2e202
AD		 599
600/*
601 * GART structures, functions & helpers
602 */
603struct amdgpu_mc;
604
605#define AMDGPU_GPU_PAGE_SIZE 4096
606#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
607#define AMDGPU_GPU_PAGE_SHIFT 12
608#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
609
610struct amdgpu_gart {
611 dma_addr_t table_addr;
612 struct amdgpu_bo *robj;
613 void *ptr;
614 unsigned num_gpu_pages;
615 unsigned num_cpu_pages;
616 unsigned table_size;
a1d29476 617#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 618 struct page **pages;
a1d29476 619#endif
97b2e202
AD		 620 bool ready;
621 const struct amdgpu_gart_funcs *gart_funcs;
622};
623
624int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
625void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
626int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
627void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
628int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
629void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
630int amdgpu_gart_init(struct amdgpu_device *adev);
631void amdgpu_gart_fini(struct amdgpu_device *adev);
632void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
633 int pages);
634int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
635 int pages, struct page **pagelist,
636 dma_addr_t *dma_addr, uint32_t flags);
637
638/*
639 * GPU MC structures, functions & helpers
640 */
641struct amdgpu_mc {
642 resource_size_t aper_size;
643 resource_size_t aper_base;
644 resource_size_t agp_base;
645 /* for some chips with <= 32MB we need to lie
646 * about vram size near mc fb location */
647 u64 mc_vram_size;
648 u64 visible_vram_size;
649 u64 gtt_size;
650 u64 gtt_start;
651 u64 gtt_end;
652 u64 vram_start;
653 u64 vram_end;
654 unsigned vram_width;
655 u64 real_vram_size;
656 int vram_mtrr;
657 u64 gtt_base_align;
658 u64 mc_mask;
659 const struct firmware *fw; /* MC firmware */
660 uint32_t fw_version;
661 struct amdgpu_irq_src vm_fault;
81c59f54 662 uint32_t vram_type;
97b2e202
AD		 663};
664
665/*
666 * GPU doorbell structures, functions & helpers
667 */
668typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
669{
670 AMDGPU_DOORBELL_KIQ = 0x000,
671 AMDGPU_DOORBELL_HIQ = 0x001,
672 AMDGPU_DOORBELL_DIQ = 0x002,
673 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
674 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
675 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
676 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
677 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
678 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
679 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
680 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
681 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
682 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
683 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
684 AMDGPU_DOORBELL_IH = 0x1E8,
685 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
686 AMDGPU_DOORBELL_INVALID = 0xFFFF
687} AMDGPU_DOORBELL_ASSIGNMENT;
688
689struct amdgpu_doorbell {
690 /* doorbell mmio */
691 resource_size_t base;
692 resource_size_t size;
693 u32 __iomem *ptr;
694 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
695};
696
697void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
698 phys_addr_t *aperture_base,
699 size_t *aperture_size,
700 size_t *start_offset);
701
702/*
703 * IRQS.
704 */
705
706struct amdgpu_flip_work {
707 struct work_struct flip_work;
708 struct work_struct unpin_work;
709 struct amdgpu_device *adev;
710 int crtc_id;
711 uint64_t base;
712 struct drm_pending_vblank_event *event;
713 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 714 struct fence *excl;
715 unsigned shared_count;
716 struct fence **shared;
c3874b75 717 struct fence_cb cb;
97b2e202
AD		 718};
719
720
721/*
722 * CP & rings.
723 */
724
725struct amdgpu_ib {
726 struct amdgpu_sa_bo *sa_bo;
727 uint32_t length_dw;
728 uint64_t gpu_addr;
729 uint32_t *ptr;
97b2e202
AD		 730 struct amdgpu_user_fence *user;
731 struct amdgpu_vm *vm;
4ff37a83
CK		 732 unsigned vm_id;
733 uint64_t vm_pd_addr;
3cb485f3 734 struct amdgpu_ctx *ctx;
97b2e202
AD		 735 uint32_t gds_base, gds_size;
736 uint32_t gws_base, gws_size;
737 uint32_t oa_base, oa_size;
de807f81 738 uint32_t flags;
5430a3ff
CK		 739 /* resulting sequence number */
740 uint64_t sequence;
97b2e202
AD		 741};
742
743enum amdgpu_ring_type {
744 AMDGPU_RING_TYPE_GFX,
745 AMDGPU_RING_TYPE_COMPUTE,
746 AMDGPU_RING_TYPE_SDMA,
747 AMDGPU_RING_TYPE_UVD,
748 AMDGPU_RING_TYPE_VCE
749};
750
62250a91 751extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 752
50838c8c
CK		 753int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
754 struct amdgpu_job **job);
d71518b5
CK		 755int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
756 struct amdgpu_job **job);
b6723c8d 757
50838c8c 758void amdgpu_job_free(struct amdgpu_job *job);
b6723c8d 759void amdgpu_job_free_func(struct kref *refcount);
d71518b5 760int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 761 struct amd_sched_entity *entity, void *owner,
762 struct fence **f);
0de2479c 763void amdgpu_job_timeout_func(struct work_struct *work);
3c704e93 764
97b2e202
AD		 765struct amdgpu_ring {
766 struct amdgpu_device *adev;
767 const struct amdgpu_ring_funcs *funcs;
768 struct amdgpu_fence_driver fence_drv;
4f839a24 769 struct amd_gpu_scheduler sched;
97b2e202 770
176e1ab1 771 spinlock_t fence_lock;
97b2e202
AD		 772 struct amdgpu_bo *ring_obj;
773 volatile uint32_t *ring;
774 unsigned rptr_offs;
775 u64 next_rptr_gpu_addr;
776 volatile u32 *next_rptr_cpu_addr;
777 unsigned wptr;
778 unsigned wptr_old;
779 unsigned ring_size;
c7e6be23 780 unsigned max_dw;
97b2e202 781 int count_dw;
97b2e202
AD		 782 uint64_t gpu_addr;
783 uint32_t align_mask;
784 uint32_t ptr_mask;
785 bool ready;
786 u32 nop;
787 u32 idx;
97b2e202
AD		 788 u32 me;
789 u32 pipe;
790 u32 queue;
791 struct amdgpu_bo *mqd_obj;
792 u32 doorbell_index;
793 bool use_doorbell;
794 unsigned wptr_offs;
795 unsigned next_rptr_offs;
796 unsigned fence_offs;
3cb485f3 797 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 798 enum amdgpu_ring_type type;
799 char name[16];
128cff1a
ML		 800 unsigned cond_exe_offs;
801 u64 cond_exe_gpu_addr;
802 volatile u32 *cond_exe_cpu_addr;
97b2e202
AD		 803};
804
805/*
806 * VM
807 */
808
809/* maximum number of VMIDs */
810#define AMDGPU_NUM_VM 16
811
812/* number of entries in page table */
813#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
814
815/* PTBs (Page Table Blocks) need to be aligned to 32K */
816#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
817#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
818#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
819
820#define AMDGPU_PTE_VALID (1 << 0)
821#define AMDGPU_PTE_SYSTEM (1 << 1)
822#define AMDGPU_PTE_SNOOPED (1 << 2)
823
824/* VI only */
825#define AMDGPU_PTE_EXECUTABLE (1 << 4)
826
827#define AMDGPU_PTE_READABLE (1 << 5)
828#define AMDGPU_PTE_WRITEABLE (1 << 6)
829
830/* PTE (Page Table Entry) fragment field for different page sizes */
831#define AMDGPU_PTE_FRAG_4KB (0 << 7)
832#define AMDGPU_PTE_FRAG_64KB (4 << 7)
833#define AMDGPU_LOG2_PAGES_PER_FRAG 4
834
d9c13156
CK		 835/* How to programm VM fault handling */
836#define AMDGPU_VM_FAULT_STOP_NEVER 0
837#define AMDGPU_VM_FAULT_STOP_FIRST 1
838#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
839
97b2e202 840struct amdgpu_vm_pt {
ee1782c3
CK		 841 struct amdgpu_bo_list_entry entry;
842 uint64_t addr;
97b2e202
AD		 843};
844
97b2e202 845struct amdgpu_vm {
25cfc3c2 846 /* tree of virtual addresses mapped */
97b2e202
AD		 847 struct rb_root va;
848
7fc11959 849 /* protecting invalidated */
97b2e202
AD		 850 spinlock_t status_lock;
851
852 /* BOs moved, but not yet updated in the PT */
853 struct list_head invalidated;
854
7fc11959
CK		 855 /* BOs cleared in the PT because of a move */
856 struct list_head cleared;
857
858 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 859 struct list_head freed;
860
861 /* contains the page directory */
862 struct amdgpu_bo *page_directory;
863 unsigned max_pde_used;
05906dec 864 struct fence *page_directory_fence;
97b2e202
AD		 865
866 /* array of page tables, one for each page directory entry */
867 struct amdgpu_vm_pt *page_tables;
868
869 /* for id and flush management per ring */
bcb1ba35 870 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
25cfc3c2 871
81d75a30 872 /* protecting freed */
873 spinlock_t freed_lock;
2bd9ccfa
CK		 874
875 /* Scheduler entity for page table updates */
876 struct amd_sched_entity entity;
97b2e202
AD		 877};
878
bcb1ba35 879struct amdgpu_vm_id {
a9a78b32 880 struct list_head list;
832a902f
CK		 881 struct fence *first;
882 struct amdgpu_sync active;
41d9eb2c 883 struct fence *last_flush;
a9a78b32 884 atomic_long_t owner;
971fe9a9 885
bcb1ba35
CK		 886 uint64_t pd_gpu_addr;
887 /* last flushed PD/PT update */
888 struct fence *flushed_updates;
889
971fe9a9
CK		 890 uint32_t gds_base;
891 uint32_t gds_size;
892 uint32_t gws_base;
893 uint32_t gws_size;
894 uint32_t oa_base;
895 uint32_t oa_size;
a9a78b32
CK		 896};
897
97b2e202 898struct amdgpu_vm_manager {
a9a78b32 899 /* Handling of VMIDs */
8d0a7cea 900 struct mutex lock;
a9a78b32
CK		 901 unsigned num_ids;
902 struct list_head ids_lru;
bcb1ba35 903 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
1c16c0a7 904
8b4fb00b 905 uint32_t max_pfn;
97b2e202 906 /* vram base address for page table entry */
8b4fb00b 907 u64 vram_base_offset;
97b2e202 908 /* is vm enabled? */
8b4fb00b 909 bool enabled;
97b2e202
AD		 910 /* vm pte handling */
911 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 912 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
913 unsigned vm_pte_num_rings;
914 atomic_t vm_pte_next_ring;
97b2e202
AD		 915};
916
a9a78b32 917void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 918void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 919int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
920void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 921void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
922 struct list_head *validated,
923 struct amdgpu_bo_list_entry *entry);
ee1782c3 924void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 925void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
926 struct amdgpu_vm *vm);
8b4fb00b 927int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83
CK		 928 struct amdgpu_sync *sync, struct fence *fence,
929 unsigned *vm_id, uint64_t *vm_pd_addr);
41d9eb2c
CK		 930int amdgpu_vm_flush(struct amdgpu_ring *ring,
931 unsigned vm_id, uint64_t pd_addr,
932 uint32_t gds_base, uint32_t gds_size,
933 uint32_t gws_base, uint32_t gws_size,
934 uint32_t oa_base, uint32_t oa_size);
971fe9a9 935void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
b07c9d2a 936uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 937int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
938 struct amdgpu_vm *vm);
939int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
940 struct amdgpu_vm *vm);
941int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
942 struct amdgpu_sync *sync);
943int amdgpu_vm_bo_update(struct amdgpu_device *adev,
944 struct amdgpu_bo_va *bo_va,
945 struct ttm_mem_reg *mem);
946void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
947 struct amdgpu_bo *bo);
948struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
949 struct amdgpu_bo *bo);
950struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
951 struct amdgpu_vm *vm,
952 struct amdgpu_bo *bo);
953int amdgpu_vm_bo_map(struct amdgpu_device *adev,
954 struct amdgpu_bo_va *bo_va,
955 uint64_t addr, uint64_t offset,
956 uint64_t size, uint32_t flags);
957int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
958 struct amdgpu_bo_va *bo_va,
959 uint64_t addr);
960void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
961 struct amdgpu_bo_va *bo_va);
8b4fb00b 962
97b2e202
AD		 963/*
964 * context related structures
965 */
966
21c16bf6 967struct amdgpu_ctx_ring {
91404fb2 968 uint64_t sequence;
37cd0ca2 969 struct fence **fences;
91404fb2 970 struct amd_sched_entity entity;
21c16bf6
CK		 971};
972
97b2e202 973struct amdgpu_ctx {
0b492a4c 974 struct kref refcount;
9cb7e5a9 975 struct amdgpu_device *adev;
0b492a4c 976 unsigned reset_counter;
21c16bf6 977 spinlock_t ring_lock;
37cd0ca2 978 struct fence **fences;
21c16bf6 979 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 980};
981
982struct amdgpu_ctx_mgr {
0b492a4c
AD		 983 struct amdgpu_device *adev;
984 struct mutex lock;
985 /* protected by lock */
986 struct idr ctx_handles;
97b2e202
AD		 987};
988
0b492a4c
AD		 989struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
990int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
991
21c16bf6 992uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 993 struct fence *fence);
21c16bf6
CK		 994struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
995 struct amdgpu_ring *ring, uint64_t seq);
996
0b492a4c
AD		 997int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *filp);
999
efd4ccb5
CK		 1000void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1001void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1002
97b2e202
AD		 1003/*
1004 * file private structure
1005 */
1006
1007struct amdgpu_fpriv {
1008 struct amdgpu_vm vm;
1009 struct mutex bo_list_lock;
1010 struct idr bo_list_handles;
0b492a4c 1011 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1012};
1013
1014/*
1015 * residency list
1016 */
1017
1018struct amdgpu_bo_list {
1019 struct mutex lock;
1020 struct amdgpu_bo *gds_obj;
1021 struct amdgpu_bo *gws_obj;
1022 struct amdgpu_bo *oa_obj;
211dff55 1023 unsigned first_userptr;
97b2e202
AD		 1024 unsigned num_entries;
1025 struct amdgpu_bo_list_entry *array;
1026};
1027
1028struct amdgpu_bo_list *
1029amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1030void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1031 struct list_head *validated);
97b2e202
AD		 1032void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1033void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1034
1035/*
1036 * GFX stuff
1037 */
1038#include "clearstate_defs.h"
1039
79e5412c
AD		 1040struct amdgpu_rlc_funcs {
1041 void (*enter_safe_mode)(struct amdgpu_device *adev);
1042 void (*exit_safe_mode)(struct amdgpu_device *adev);
1043};
1044
97b2e202
AD		 1045struct amdgpu_rlc {
1046 /* for power gating */
1047 struct amdgpu_bo *save_restore_obj;
1048 uint64_t save_restore_gpu_addr;
1049 volatile uint32_t *sr_ptr;
1050 const u32 *reg_list;
1051 u32 reg_list_size;
1052 /* for clear state */
1053 struct amdgpu_bo *clear_state_obj;
1054 uint64_t clear_state_gpu_addr;
1055 volatile uint32_t *cs_ptr;
1056 const struct cs_section_def *cs_data;
1057 u32 clear_state_size;
1058 /* for cp tables */
1059 struct amdgpu_bo *cp_table_obj;
1060 uint64_t cp_table_gpu_addr;
1061 volatile uint32_t *cp_table_ptr;
1062 u32 cp_table_size;
79e5412c
AD		 1063
1064 /* safe mode for updating CG/PG state */
1065 bool in_safe_mode;
1066 const struct amdgpu_rlc_funcs *funcs;
97b2e202
AD		 1067};
1068
1069struct amdgpu_mec {
1070 struct amdgpu_bo *hpd_eop_obj;
1071 u64 hpd_eop_gpu_addr;
1072 u32 num_pipe;
1073 u32 num_mec;
1074 u32 num_queue;
1075};
1076
1077/*
1078 * GPU scratch registers structures, functions & helpers
1079 */
1080struct amdgpu_scratch {
1081 unsigned num_reg;
1082 uint32_t reg_base;
1083 bool free[32];
1084 uint32_t reg[32];
1085};
1086
1087/*
1088 * GFX configurations
1089 */
1090struct amdgpu_gca_config {
1091 unsigned max_shader_engines;
1092 unsigned max_tile_pipes;
1093 unsigned max_cu_per_sh;
1094 unsigned max_sh_per_se;
1095 unsigned max_backends_per_se;
1096 unsigned max_texture_channel_caches;
1097 unsigned max_gprs;
1098 unsigned max_gs_threads;
1099 unsigned max_hw_contexts;
1100 unsigned sc_prim_fifo_size_frontend;
1101 unsigned sc_prim_fifo_size_backend;
1102 unsigned sc_hiz_tile_fifo_size;
1103 unsigned sc_earlyz_tile_fifo_size;
1104
1105 unsigned num_tile_pipes;
1106 unsigned backend_enable_mask;
1107 unsigned mem_max_burst_length_bytes;
1108 unsigned mem_row_size_in_kb;
1109 unsigned shader_engine_tile_size;
1110 unsigned num_gpus;
1111 unsigned multi_gpu_tile_size;
1112 unsigned mc_arb_ramcfg;
1113 unsigned gb_addr_config;
8f8e00c1 1114 unsigned num_rbs;
97b2e202
AD		 1115
1116 uint32_t tile_mode_array[32];
1117 uint32_t macrotile_mode_array[16];
1118};
1119
1120struct amdgpu_gfx {
1121 struct mutex gpu_clock_mutex;
1122 struct amdgpu_gca_config config;
1123 struct amdgpu_rlc rlc;
1124 struct amdgpu_mec mec;
1125 struct amdgpu_scratch scratch;
1126 const struct firmware *me_fw; /* ME firmware */
1127 uint32_t me_fw_version;
1128 const struct firmware *pfp_fw; /* PFP firmware */
1129 uint32_t pfp_fw_version;
1130 const struct firmware *ce_fw; /* CE firmware */
1131 uint32_t ce_fw_version;
1132 const struct firmware *rlc_fw; /* RLC firmware */
1133 uint32_t rlc_fw_version;
1134 const struct firmware *mec_fw; /* MEC firmware */
1135 uint32_t mec_fw_version;
1136 const struct firmware *mec2_fw; /* MEC2 firmware */
1137 uint32_t mec2_fw_version;
02558a00
KW		 1138 uint32_t me_feature_version;
1139 uint32_t ce_feature_version;
1140 uint32_t pfp_feature_version;
351643d7
JZ		 1141 uint32_t rlc_feature_version;
1142 uint32_t mec_feature_version;
1143 uint32_t mec2_feature_version;
97b2e202
AD		 1144 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1145 unsigned num_gfx_rings;
1146 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1147 unsigned num_compute_rings;
1148 struct amdgpu_irq_src eop_irq;
1149 struct amdgpu_irq_src priv_reg_irq;
1150 struct amdgpu_irq_src priv_inst_irq;
1151 /* gfx status */
1152 uint32_t gfx_current_status;
a101a899
KW		 1153 /* ce ram size*/
1154 unsigned ce_ram_size;
97b2e202
AD		 1155};
1156
b07c60c0 1157int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1158 unsigned size, struct amdgpu_ib *ib);
cc55c45d 1159void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
b07c60c0 1160int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1161 struct amdgpu_ib *ib, struct fence *last_vm_update,
ec72b800 1162 struct fence **f);
97b2e202
AD		 1163int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1164void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1165int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1166int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1167void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1168void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1169void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1170void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1171unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1172 uint32_t **data);
1173int amdgpu_ring_restore(struct amdgpu_ring *ring,
1174 unsigned size, uint32_t *data);
1175int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1176 unsigned ring_size, u32 nop, u32 align_mask,
1177 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1178 enum amdgpu_ring_type ring_type);
1179void amdgpu_ring_fini(struct amdgpu_ring *ring);
1180
1181/*
1182 * CS.
1183 */
1184struct amdgpu_cs_chunk {
1185 uint32_t chunk_id;
1186 uint32_t length_dw;
1187 uint32_t *kdata;
97b2e202
AD		 1188};
1189
1190struct amdgpu_cs_parser {
1191 struct amdgpu_device *adev;
1192 struct drm_file *filp;
3cb485f3 1193 struct amdgpu_ctx *ctx;
c3cca41e 1194
97b2e202
AD		 1195 /* chunks */
1196 unsigned nchunks;
1197 struct amdgpu_cs_chunk *chunks;
97b2e202 1198
50838c8c
CK		 1199 /* scheduler job object */
1200 struct amdgpu_job *job;
97b2e202 1201
c3cca41e
CK		 1202 /* buffer objects */
1203 struct ww_acquire_ctx ticket;
1204 struct amdgpu_bo_list *bo_list;
1205 struct amdgpu_bo_list_entry vm_pd;
1206 struct list_head validated;
1207 struct fence *fence;
1208 uint64_t bytes_moved_threshold;
1209 uint64_t bytes_moved;
97b2e202
AD		 1210
1211 /* user fence */
91acbeb6 1212 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1213};
1214
bb977d37
CZ		 1215struct amdgpu_job {
1216 struct amd_sched_job base;
1217 struct amdgpu_device *adev;
b07c60c0 1218 struct amdgpu_ring *ring;
e86f9cee 1219 struct amdgpu_sync sync;
bb977d37 1220 struct amdgpu_ib *ibs;
73cfa5f5 1221 struct fence *fence; /* the hw fence */
bb977d37 1222 uint32_t num_ibs;
e2840221 1223 void *owner;
bb977d37 1224 struct amdgpu_user_fence uf;
bb977d37 1225};
a6db8a33
JZ		 1226#define to_amdgpu_job(sched_job) \
1227 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1228
7270f839
CK		 1229static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1230 uint32_t ib_idx, int idx)
97b2e202 1231{
50838c8c 1232 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1233}
1234
7270f839
CK		 1235static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1236 uint32_t ib_idx, int idx,
1237 uint32_t value)
1238{
50838c8c 1239 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1240}
1241
97b2e202
AD		 1242/*
1243 * Writeback
1244 */
1245#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1246
1247struct amdgpu_wb {
1248 struct amdgpu_bo *wb_obj;
1249 volatile uint32_t *wb;
1250 uint64_t gpu_addr;
1251 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1252 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1253};
1254
1255int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1256void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1257
97b2e202 1258
97b2e202
AD		 1259
1260enum amdgpu_int_thermal_type {
1261 THERMAL_TYPE_NONE,
1262 THERMAL_TYPE_EXTERNAL,
1263 THERMAL_TYPE_EXTERNAL_GPIO,
1264 THERMAL_TYPE_RV6XX,
1265 THERMAL_TYPE_RV770,
1266 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1267 THERMAL_TYPE_EVERGREEN,
1268 THERMAL_TYPE_SUMO,
1269 THERMAL_TYPE_NI,
1270 THERMAL_TYPE_SI,
1271 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1272 THERMAL_TYPE_CI,
1273 THERMAL_TYPE_KV,
1274};
1275
1276enum amdgpu_dpm_auto_throttle_src {
1277 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1278 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1279};
1280
1281enum amdgpu_dpm_event_src {
1282 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1283 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1284 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1285 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1286 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1287};
1288
1289#define AMDGPU_MAX_VCE_LEVELS 6
1290
1291enum amdgpu_vce_level {
1292 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1293 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1294 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1295 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1296 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1297 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1298};
1299
1300struct amdgpu_ps {
1301 u32 caps; /* vbios flags */
1302 u32 class; /* vbios flags */
1303 u32 class2; /* vbios flags */
1304 /* UVD clocks */
1305 u32 vclk;
1306 u32 dclk;
1307 /* VCE clocks */
1308 u32 evclk;
1309 u32 ecclk;
1310 bool vce_active;
1311 enum amdgpu_vce_level vce_level;
1312 /* asic priv */
1313 void *ps_priv;
1314};
1315
1316struct amdgpu_dpm_thermal {
1317 /* thermal interrupt work */
1318 struct work_struct work;
1319 /* low temperature threshold */
1320 int min_temp;
1321 /* high temperature threshold */
1322 int max_temp;
1323 /* was last interrupt low to high or high to low */
1324 bool high_to_low;
1325 /* interrupt source */
1326 struct amdgpu_irq_src irq;
1327};
1328
1329enum amdgpu_clk_action
1330{
1331 AMDGPU_SCLK_UP = 1,
1332 AMDGPU_SCLK_DOWN
1333};
1334
1335struct amdgpu_blacklist_clocks
1336{
1337 u32 sclk;
1338 u32 mclk;
1339 enum amdgpu_clk_action action;
1340};
1341
1342struct amdgpu_clock_and_voltage_limits {
1343 u32 sclk;
1344 u32 mclk;
1345 u16 vddc;
1346 u16 vddci;
1347};
1348
1349struct amdgpu_clock_array {
1350 u32 count;
1351 u32 *values;
1352};
1353
1354struct amdgpu_clock_voltage_dependency_entry {
1355 u32 clk;
1356 u16 v;
1357};
1358
1359struct amdgpu_clock_voltage_dependency_table {
1360 u32 count;
1361 struct amdgpu_clock_voltage_dependency_entry *entries;
1362};
1363
1364union amdgpu_cac_leakage_entry {
1365 struct {
1366 u16 vddc;
1367 u32 leakage;
1368 };
1369 struct {
1370 u16 vddc1;
1371 u16 vddc2;
1372 u16 vddc3;
1373 };
1374};
1375
1376struct amdgpu_cac_leakage_table {
1377 u32 count;
1378 union amdgpu_cac_leakage_entry *entries;
1379};
1380
1381struct amdgpu_phase_shedding_limits_entry {
1382 u16 voltage;
1383 u32 sclk;
1384 u32 mclk;
1385};
1386
1387struct amdgpu_phase_shedding_limits_table {
1388 u32 count;
1389 struct amdgpu_phase_shedding_limits_entry *entries;
1390};
1391
1392struct amdgpu_uvd_clock_voltage_dependency_entry {
1393 u32 vclk;
1394 u32 dclk;
1395 u16 v;
1396};
1397
1398struct amdgpu_uvd_clock_voltage_dependency_table {
1399 u8 count;
1400 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1401};
1402
1403struct amdgpu_vce_clock_voltage_dependency_entry {
1404 u32 ecclk;
1405 u32 evclk;
1406 u16 v;
1407};
1408
1409struct amdgpu_vce_clock_voltage_dependency_table {
1410 u8 count;
1411 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1412};
1413
1414struct amdgpu_ppm_table {
1415 u8 ppm_design;
1416 u16 cpu_core_number;
1417 u32 platform_tdp;
1418 u32 small_ac_platform_tdp;
1419 u32 platform_tdc;
1420 u32 small_ac_platform_tdc;
1421 u32 apu_tdp;
1422 u32 dgpu_tdp;
1423 u32 dgpu_ulv_power;
1424 u32 tj_max;
1425};
1426
1427struct amdgpu_cac_tdp_table {
1428 u16 tdp;
1429 u16 configurable_tdp;
1430 u16 tdc;
1431 u16 battery_power_limit;
1432 u16 small_power_limit;
1433 u16 low_cac_leakage;
1434 u16 high_cac_leakage;
1435 u16 maximum_power_delivery_limit;
1436};
1437
1438struct amdgpu_dpm_dynamic_state {
1439 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1440 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1441 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1442 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1443 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1444 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1445 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1446 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1447 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1448 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1449 struct amdgpu_clock_array valid_sclk_values;
1450 struct amdgpu_clock_array valid_mclk_values;
1451 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1452 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1453 u32 mclk_sclk_ratio;
1454 u32 sclk_mclk_delta;
1455 u16 vddc_vddci_delta;
1456 u16 min_vddc_for_pcie_gen2;
1457 struct amdgpu_cac_leakage_table cac_leakage_table;
1458 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1459 struct amdgpu_ppm_table *ppm_table;
1460 struct amdgpu_cac_tdp_table *cac_tdp_table;
1461};
1462
1463struct amdgpu_dpm_fan {
1464 u16 t_min;
1465 u16 t_med;
1466 u16 t_high;
1467 u16 pwm_min;
1468 u16 pwm_med;
1469 u16 pwm_high;
1470 u8 t_hyst;
1471 u32 cycle_delay;
1472 u16 t_max;
1473 u8 control_mode;
1474 u16 default_max_fan_pwm;
1475 u16 default_fan_output_sensitivity;
1476 u16 fan_output_sensitivity;
1477 bool ucode_fan_control;
1478};
1479
1480enum amdgpu_pcie_gen {
1481 AMDGPU_PCIE_GEN1 = 0,
1482 AMDGPU_PCIE_GEN2 = 1,
1483 AMDGPU_PCIE_GEN3 = 2,
1484 AMDGPU_PCIE_GEN_INVALID = 0xffff
1485};
1486
1487enum amdgpu_dpm_forced_level {
1488 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1489 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1490 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1491 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1492};
1493
1494struct amdgpu_vce_state {
1495 /* vce clocks */
1496 u32 evclk;
1497 u32 ecclk;
1498 /* gpu clocks */
1499 u32 sclk;
1500 u32 mclk;
1501 u8 clk_idx;
1502 u8 pstate;
1503};
1504
1505struct amdgpu_dpm_funcs {
1506 int (*get_temperature)(struct amdgpu_device *adev);
1507 int (*pre_set_power_state)(struct amdgpu_device *adev);
1508 int (*set_power_state)(struct amdgpu_device *adev);
1509 void (*post_set_power_state)(struct amdgpu_device *adev);
1510 void (*display_configuration_changed)(struct amdgpu_device *adev);
1511 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1512 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1513 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1514 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1515 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1516 bool (*vblank_too_short)(struct amdgpu_device *adev);
1517 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1518 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1519 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1520 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1521 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1522 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1523 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1524};
1525
1526struct amdgpu_dpm {
1527 struct amdgpu_ps *ps;
1528 /* number of valid power states */
1529 int num_ps;
1530 /* current power state that is active */
1531 struct amdgpu_ps *current_ps;
1532 /* requested power state */
1533 struct amdgpu_ps *requested_ps;
1534 /* boot up power state */
1535 struct amdgpu_ps *boot_ps;
1536 /* default uvd power state */
1537 struct amdgpu_ps *uvd_ps;
1538 /* vce requirements */
1539 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1540 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1541 enum amd_pm_state_type state;
1542 enum amd_pm_state_type user_state;
97b2e202
AD		 1543 u32 platform_caps;
1544 u32 voltage_response_time;
1545 u32 backbias_response_time;
1546 void *priv;
1547 u32 new_active_crtcs;
1548 int new_active_crtc_count;
1549 u32 current_active_crtcs;
1550 int current_active_crtc_count;
1551 struct amdgpu_dpm_dynamic_state dyn_state;
1552 struct amdgpu_dpm_fan fan;
1553 u32 tdp_limit;
1554 u32 near_tdp_limit;
1555 u32 near_tdp_limit_adjusted;
1556 u32 sq_ramping_threshold;
1557 u32 cac_leakage;
1558 u16 tdp_od_limit;
1559 u32 tdp_adjustment;
1560 u16 load_line_slope;
1561 bool power_control;
1562 bool ac_power;
1563 /* special states active */
1564 bool thermal_active;
1565 bool uvd_active;
1566 bool vce_active;
1567 /* thermal handling */
1568 struct amdgpu_dpm_thermal thermal;
1569 /* forced levels */
1570 enum amdgpu_dpm_forced_level forced_level;
1571};
1572
1573struct amdgpu_pm {
1574 struct mutex mutex;
97b2e202
AD		 1575 u32 current_sclk;
1576 u32 current_mclk;
1577 u32 default_sclk;
1578 u32 default_mclk;
1579 struct amdgpu_i2c_chan *i2c_bus;
1580 /* internal thermal controller on rv6xx+ */
1581 enum amdgpu_int_thermal_type int_thermal_type;
1582 struct device *int_hwmon_dev;
1583 /* fan control parameters */
1584 bool no_fan;
1585 u8 fan_pulses_per_revolution;
1586 u8 fan_min_rpm;
1587 u8 fan_max_rpm;
1588 /* dpm */
1589 bool dpm_enabled;
c86f5ebf 1590 bool sysfs_initialized;
97b2e202
AD		 1591 struct amdgpu_dpm dpm;
1592 const struct firmware *fw; /* SMC firmware */
1593 uint32_t fw_version;
1594 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1595 uint32_t pcie_gen_mask;
1596 uint32_t pcie_mlw_mask;
7fb72a1f 1597 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1598};
1599
d0dd7f0c
AD		 1600void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1601
97b2e202
AD		 1602/*
1603 * UVD
1604 */
c0365541
AN		 1605#define AMDGPU_DEFAULT_UVD_HANDLES 10
1606#define AMDGPU_MAX_UVD_HANDLES 40
1607#define AMDGPU_UVD_STACK_SIZE (200*1024)
1608#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1609#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1610#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1611
1612struct amdgpu_uvd {
1613 struct amdgpu_bo *vcpu_bo;
1614 void *cpu_addr;
1615 uint64_t gpu_addr;
3f99dd81 1616 void *saved_bo;
c0365541 1617 unsigned max_handles;
97b2e202
AD		 1618 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1619 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1620 struct delayed_work idle_work;
1621 const struct firmware *fw; /* UVD firmware */
1622 struct amdgpu_ring ring;
1623 struct amdgpu_irq_src irq;
1624 bool address_64_bit;
ead833ec 1625 struct amd_sched_entity entity;
97b2e202
AD		 1626};
1627
1628/*
1629 * VCE
1630 */
1631#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1632#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1633
6a585777
AD		 1634#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1635#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1636
97b2e202
AD		 1637struct amdgpu_vce {
1638 struct amdgpu_bo *vcpu_bo;
1639 uint64_t gpu_addr;
1640 unsigned fw_version;
1641 unsigned fb_version;
1642 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1643 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1644 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1645 struct delayed_work idle_work;
1646 const struct firmware *fw; /* VCE firmware */
1647 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1648 struct amdgpu_irq_src irq;
6a585777 1649 unsigned harvest_config;
c594989c 1650 struct amd_sched_entity entity;
97b2e202
AD		 1651};
1652
1653/*
1654 * SDMA
1655 */
c113ea1c 1656struct amdgpu_sdma_instance {
97b2e202
AD		 1657 /* SDMA firmware */
1658 const struct firmware *fw;
1659 uint32_t fw_version;
cfa2104f 1660 uint32_t feature_version;
97b2e202
AD		 1661
1662 struct amdgpu_ring ring;
18111de0 1663 bool burst_nop;
97b2e202
AD		 1664};
1665
c113ea1c
AD		 1666struct amdgpu_sdma {
1667 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1668 struct amdgpu_irq_src trap_irq;
1669 struct amdgpu_irq_src illegal_inst_irq;
1670 int num_instances;
1671};
1672
97b2e202
AD		 1673/*
1674 * Firmware
1675 */
1676struct amdgpu_firmware {
1677 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1678 bool smu_load;
1679 struct amdgpu_bo *fw_buf;
1680 unsigned int fw_size;
1681};
1682
1683/*
1684 * Benchmarking
1685 */
1686void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1687
1688
1689/*
1690 * Testing
1691 */
1692void amdgpu_test_moves(struct amdgpu_device *adev);
1693void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1694 struct amdgpu_ring *cpA,
1695 struct amdgpu_ring *cpB);
1696void amdgpu_test_syncing(struct amdgpu_device *adev);
1697
1698/*
1699 * MMU Notifier
1700 */
1701#if defined(CONFIG_MMU_NOTIFIER)
1702int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1703void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1704#else
1d1106b0 1705static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1706{
1707 return -ENODEV;
1708}
1d1106b0 1709static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1710#endif
1711
1712/*
1713 * Debugfs
1714 */
1715struct amdgpu_debugfs {
06ab6832 1716 const struct drm_info_list *files;
97b2e202
AD		 1717 unsigned num_files;
1718};
1719
1720int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1721 const struct drm_info_list *files,
97b2e202
AD		 1722 unsigned nfiles);
1723int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1724
1725#if defined(CONFIG_DEBUG_FS)
1726int amdgpu_debugfs_init(struct drm_minor *minor);
1727void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1728#endif
1729
1730/*
1731 * amdgpu smumgr functions
1732 */
1733struct amdgpu_smumgr_funcs {
1734 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1735 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1736 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1737};
1738
1739/*
1740 * amdgpu smumgr
1741 */
1742struct amdgpu_smumgr {
1743 struct amdgpu_bo *toc_buf;
1744 struct amdgpu_bo *smu_buf;
1745 /* asic priv smu data */
1746 void *priv;
1747 spinlock_t smu_lock;
1748 /* smumgr functions */
1749 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1750 /* ucode loading complete flag */
1751 uint32_t fw_flags;
1752};
1753
1754/*
1755 * ASIC specific register table accessible by UMD
1756 */
1757struct amdgpu_allowed_register_entry {
1758 uint32_t reg_offset;
1759 bool untouched;
1760 bool grbm_indexed;
1761};
1762
1763struct amdgpu_cu_info {
1764 uint32_t number; /* total active CU number */
1765 uint32_t ao_cu_mask;
1766 uint32_t bitmap[4][4];
1767};
1768
1769
1770/*
1771 * ASIC specific functions.
1772 */
1773struct amdgpu_asic_funcs {
1774 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1775 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1776 u8 *bios, u32 length_bytes);
97b2e202
AD		 1777 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1778 u32 sh_num, u32 reg_offset, u32 *value);
1779 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1780 int (*reset)(struct amdgpu_device *adev);
1781 /* wait for mc_idle */
1782 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1783 /* get the reference clock */
1784 u32 (*get_xclk)(struct amdgpu_device *adev);
1785 /* get the gpu clock counter */
1786 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1787 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1788 /* MM block clocks */
1789 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1790 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1791};
1792
1793/*
1794 * IOCTL.
1795 */
1796int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1797 struct drm_file *filp);
1798int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1799 struct drm_file *filp);
1800
1801int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1802 struct drm_file *filp);
1803int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1804 struct drm_file *filp);
1805int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1806 struct drm_file *filp);
1807int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1808 struct drm_file *filp);
1809int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1810 struct drm_file *filp);
1811int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1814int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1815
1816int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1817 struct drm_file *filp);
1818
1819/* VRAM scratch page for HDP bug, default vram page */
1820struct amdgpu_vram_scratch {
1821 struct amdgpu_bo *robj;
1822 volatile uint32_t *ptr;
1823 u64 gpu_addr;
1824};
1825
1826/*
1827 * ACPI
1828 */
1829struct amdgpu_atif_notification_cfg {
1830 bool enabled;
1831 int command_code;
1832};
1833
1834struct amdgpu_atif_notifications {
1835 bool display_switch;
1836 bool expansion_mode_change;
1837 bool thermal_state;
1838 bool forced_power_state;
1839 bool system_power_state;
1840 bool display_conf_change;
1841 bool px_gfx_switch;
1842 bool brightness_change;
1843 bool dgpu_display_event;
1844};
1845
1846struct amdgpu_atif_functions {
1847 bool system_params;
1848 bool sbios_requests;
1849 bool select_active_disp;
1850 bool lid_state;
1851 bool get_tv_standard;
1852 bool set_tv_standard;
1853 bool get_panel_expansion_mode;
1854 bool set_panel_expansion_mode;
1855 bool temperature_change;
1856 bool graphics_device_types;
1857};
1858
1859struct amdgpu_atif {
1860 struct amdgpu_atif_notifications notifications;
1861 struct amdgpu_atif_functions functions;
1862 struct amdgpu_atif_notification_cfg notification_cfg;
1863 struct amdgpu_encoder *encoder_for_bl;
1864};
1865
1866struct amdgpu_atcs_functions {
1867 bool get_ext_state;
1868 bool pcie_perf_req;
1869 bool pcie_dev_rdy;
1870 bool pcie_bus_width;
1871};
1872
1873struct amdgpu_atcs {
1874 struct amdgpu_atcs_functions functions;
1875};
1876
d03846af
CZ		 1877/*
1878 * CGS
1879 */
110e6f26
DA		 1880struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1881void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce
MB		 1882
1883
7e471e6f
AD		 1884/* GPU virtualization */
1885struct amdgpu_virtualization {
1886 bool supports_sr_iov;
1887};
1888
97b2e202
AD		 1889/*
1890 * Core structure, functions and helpers.
1891 */
1892typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1893typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1894
1895typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1896typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1897
8faf0e08
AD		 1898struct amdgpu_ip_block_status {
1899 bool valid;
1900 bool sw;
1901 bool hw;
1902};
1903
97b2e202
AD		 1904struct amdgpu_device {
1905 struct device *dev;
1906 struct drm_device *ddev;
1907 struct pci_dev *pdev;
97b2e202 1908
a8fe58ce
MB		 1909#ifdef CONFIG_DRM_AMD_ACP
1910 struct amdgpu_acp acp;
1911#endif
1912
97b2e202 1913 /* ASIC */
2f7d10b3 1914 enum amd_asic_type asic_type;
97b2e202
AD		 1915 uint32_t family;
1916 uint32_t rev_id;
1917 uint32_t external_rev_id;
1918 unsigned long flags;
1919 int usec_timeout;
1920 const struct amdgpu_asic_funcs *asic_funcs;
1921 bool shutdown;
97b2e202
AD		 1922 bool need_dma32;
1923 bool accel_working;
97b2e202
AD		 1924 struct work_struct reset_work;
1925 struct notifier_block acpi_nb;
1926 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1927 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1928 unsigned debugfs_count;
1929#if defined(CONFIG_DEBUG_FS)
1930 struct dentry *debugfs_regs;
1931#endif
1932 struct amdgpu_atif atif;
1933 struct amdgpu_atcs atcs;
1934 struct mutex srbm_mutex;
1935 /* GRBM index mutex. Protects concurrent access to GRBM index */
1936 struct mutex grbm_idx_mutex;
1937 struct dev_pm_domain vga_pm_domain;
1938 bool have_disp_power_ref;
1939
1940 /* BIOS */
1941 uint8_t *bios;
1942 bool is_atom_bios;
97b2e202
AD		 1943 struct amdgpu_bo *stollen_vga_memory;
1944 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1945
1946 /* Register/doorbell mmio */
1947 resource_size_t rmmio_base;
1948 resource_size_t rmmio_size;
1949 void __iomem *rmmio;
1950 /* protects concurrent MM_INDEX/DATA based register access */
1951 spinlock_t mmio_idx_lock;
1952 /* protects concurrent SMC based register access */
1953 spinlock_t smc_idx_lock;
1954 amdgpu_rreg_t smc_rreg;
1955 amdgpu_wreg_t smc_wreg;
1956 /* protects concurrent PCIE register access */
1957 spinlock_t pcie_idx_lock;
1958 amdgpu_rreg_t pcie_rreg;
1959 amdgpu_wreg_t pcie_wreg;
1960 /* protects concurrent UVD register access */
1961 spinlock_t uvd_ctx_idx_lock;
1962 amdgpu_rreg_t uvd_ctx_rreg;
1963 amdgpu_wreg_t uvd_ctx_wreg;
1964 /* protects concurrent DIDT register access */
1965 spinlock_t didt_idx_lock;
1966 amdgpu_rreg_t didt_rreg;
1967 amdgpu_wreg_t didt_wreg;
1968 /* protects concurrent ENDPOINT (audio) register access */
1969 spinlock_t audio_endpt_idx_lock;
1970 amdgpu_block_rreg_t audio_endpt_rreg;
1971 amdgpu_block_wreg_t audio_endpt_wreg;
1972 void __iomem *rio_mem;
1973 resource_size_t rio_mem_size;
1974 struct amdgpu_doorbell doorbell;
1975
1976 /* clock/pll info */
1977 struct amdgpu_clock clock;
1978
1979 /* MC */
1980 struct amdgpu_mc mc;
1981 struct amdgpu_gart gart;
1982 struct amdgpu_dummy_page dummy_page;
1983 struct amdgpu_vm_manager vm_manager;
1984
1985 /* memory management */
1986 struct amdgpu_mman mman;
97b2e202
AD		 1987 struct amdgpu_vram_scratch vram_scratch;
1988 struct amdgpu_wb wb;
1989 atomic64_t vram_usage;
1990 atomic64_t vram_vis_usage;
1991 atomic64_t gtt_usage;
1992 atomic64_t num_bytes_moved;
d94aed5a 1993 atomic_t gpu_reset_counter;
97b2e202
AD		 1994
1995 /* display */
1996 struct amdgpu_mode_info mode_info;
1997 struct work_struct hotplug_work;
1998 struct amdgpu_irq_src crtc_irq;
1999 struct amdgpu_irq_src pageflip_irq;
2000 struct amdgpu_irq_src hpd_irq;
2001
2002 /* rings */
97b2e202 2003 unsigned fence_context;
97b2e202
AD		 2004 unsigned num_rings;
2005 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2006 bool ib_pool_ready;
2007 struct amdgpu_sa_manager ring_tmp_bo;
2008
2009 /* interrupts */
2010 struct amdgpu_irq irq;
2011
1f7371b2
AD		 2012 /* powerplay */
2013 struct amd_powerplay powerplay;
e61710c5 2014 bool pp_enabled;
f3898ea1 2015 bool pp_force_state_enabled;
1f7371b2 2016
97b2e202
AD		 2017 /* dpm */
2018 struct amdgpu_pm pm;
2019 u32 cg_flags;
2020 u32 pg_flags;
2021
2022 /* amdgpu smumgr */
2023 struct amdgpu_smumgr smu;
2024
2025 /* gfx */
2026 struct amdgpu_gfx gfx;
2027
2028 /* sdma */
c113ea1c 2029 struct amdgpu_sdma sdma;
97b2e202
AD		 2030
2031 /* uvd */
97b2e202
AD		 2032 struct amdgpu_uvd uvd;
2033
2034 /* vce */
2035 struct amdgpu_vce vce;
2036
2037 /* firmwares */
2038 struct amdgpu_firmware firmware;
2039
2040 /* GDS */
2041 struct amdgpu_gds gds;
2042
2043 const struct amdgpu_ip_block_version *ip_blocks;
2044 int num_ip_blocks;
8faf0e08 2045 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2046 struct mutex mn_lock;
2047 DECLARE_HASHTABLE(mn_hash, 7);
2048
2049 /* tracking pinned memory */
2050 u64 vram_pin_size;
2051 u64 gart_pin_size;
130e0371
OG		 2052
2053 /* amdkfd interface */
2054 struct kfd_dev *kfd;
23ca0e4e 2055
7e471e6f 2056 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2057};
2058
2059bool amdgpu_device_is_px(struct drm_device *dev);
2060int amdgpu_device_init(struct amdgpu_device *adev,
2061 struct drm_device *ddev,
2062 struct pci_dev *pdev,
2063 uint32_t flags);
2064void amdgpu_device_fini(struct amdgpu_device *adev);
2065int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2066
2067uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2068 bool always_indirect);
2069void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2070 bool always_indirect);
2071u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2072void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2073
2074u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2075void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2076
97b2e202
AD		 2077/*
2078 * Registers read & write functions.
2079 */
2080#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2081#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2082#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2083#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2084#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2085#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2086#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2087#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2088#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2089#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2090#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2091#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2092#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2093#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2094#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2095#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2096#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2097#define WREG32_P(reg, val, mask) \
2098 do { \
2099 uint32_t tmp_ = RREG32(reg); \
2100 tmp_ &= (mask); \
2101 tmp_ |= ((val) & ~(mask)); \
2102 WREG32(reg, tmp_); \
2103 } while (0)
2104#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2105#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2106#define WREG32_PLL_P(reg, val, mask) \
2107 do { \
2108 uint32_t tmp_ = RREG32_PLL(reg); \
2109 tmp_ &= (mask); \
2110 tmp_ |= ((val) & ~(mask)); \
2111 WREG32_PLL(reg, tmp_); \
2112 } while (0)
2113#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2114#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2115#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2116
2117#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2118#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2119
2120#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2121#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2122
2123#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2124 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2125 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2126
2127#define REG_GET_FIELD(value, reg, field) \
2128 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2129
2130/*
2131 * BIOS helpers.
2132 */
2133#define RBIOS8(i) (adev->bios[i])
2134#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2135#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2136
2137/*
2138 * RING helpers.
2139 */
2140static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2141{
2142 if (ring->count_dw <= 0)
86c2b790 2143 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2144 ring->ring[ring->wptr++] = v;
2145 ring->wptr &= ring->ptr_mask;
2146 ring->count_dw--;
97b2e202
AD		 2147}
2148
c113ea1c
AD		 2149static inline struct amdgpu_sdma_instance *
2150amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2151{
2152 struct amdgpu_device *adev = ring->adev;
2153 int i;
2154
c113ea1c
AD		 2155 for (i = 0; i < adev->sdma.num_instances; i++)
2156 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2157 break;
2158
2159 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2160 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2161 else
2162 return NULL;
2163}
2164
97b2e202
AD		 2165/*
2166 * ASICs macro.
2167 */
2168#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2169#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2170#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2171#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2172#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2173#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2174#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2175#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2176#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2177#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2178#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2179#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2180#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2181#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2182#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2183#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2184#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2185#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2186#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2187#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2188#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2189#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2190#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
b8c7b39e 2191#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2192#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2193#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2194#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2195#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2196#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2197#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 2198#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2199#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 2200#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2201#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2202#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2203#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2204#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2205#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2206#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2207#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2208#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2209#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2210#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2211#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2212#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2213#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2214#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2215#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2216#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2217#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2218#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2219#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2220#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2221#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2222#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2223#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2224#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2225#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2226#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2227#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2228
2229#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2230 ((adev)->pp_enabled ? \
e61710c5 2231 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2232 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2233
2234#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2235 ((adev)->pp_enabled ? \
e61710c5 2236 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2237 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2238
2239#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2240 ((adev)->pp_enabled ? \
e61710c5 2241 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2242 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2243
2244#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2245 ((adev)->pp_enabled ? \
e61710c5 2246 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2247 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2248
2249#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2250 ((adev)->pp_enabled ? \
e61710c5 2251 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2252 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2253
1b5708ff 2254#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2255 ((adev)->pp_enabled ? \
e61710c5 2256 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2257 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2258
2259#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2260 ((adev)->pp_enabled ? \
e61710c5 2261 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2262 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2263
2264
2265#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2266 ((adev)->pp_enabled ? \
e61710c5 2267 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2268 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2269
2270#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2271 ((adev)->pp_enabled ? \
e61710c5 2272 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2273 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2274
2275#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2276 ((adev)->pp_enabled ? \
e61710c5 2277 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2278 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2279
2280#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2281 ((adev)->pp_enabled ? \
e61710c5 2282 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2283 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2284
2285#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2286 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2287
2288#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2289 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2290
f3898ea1
EH		 2291#define amdgpu_dpm_get_pp_num_states(adev, data) \
2292 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2293
2294#define amdgpu_dpm_get_pp_table(adev, table) \
2295 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2296
2297#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2298 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2299
2300#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2301 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2302
2303#define amdgpu_dpm_force_clock_level(adev, type, level) \
2304 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2305
e61710c5 2306#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2307 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2308
2309#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2310
2311/* Common functions */
2312int amdgpu_gpu_reset(struct amdgpu_device *adev);
2313void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2314bool amdgpu_card_posted(struct amdgpu_device *adev);
2315void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2316
97b2e202
AD		 2317int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2318int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2319 u32 ip_instance, u32 ring,
2320 struct amdgpu_ring **out_ring);
2321void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2322bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2323int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2324int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2325 uint32_t flags);
2326bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 2327struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2328bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2329 unsigned long end);
2f568dbd
CK		 2330bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2331 int *last_invalidated);
97b2e202
AD		 2332bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2333uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2334 struct ttm_mem_reg *mem);
2335void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2336void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2337void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2338void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2339 const u32 *registers,
2340 const u32 array_size);
2341
2342bool amdgpu_device_is_px(struct drm_device *dev);
2343/* atpx handler */
2344#if defined(CONFIG_VGA_SWITCHEROO)
2345void amdgpu_register_atpx_handler(void);
2346void amdgpu_unregister_atpx_handler(void);
2347#else
2348static inline void amdgpu_register_atpx_handler(void) {}
2349static inline void amdgpu_unregister_atpx_handler(void) {}
2350#endif
2351
2352/*
2353 * KMS
2354 */
2355extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 2356extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 2357
2358int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2359int amdgpu_driver_unload_kms(struct drm_device *dev);
2360void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2361int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2362void amdgpu_driver_postclose_kms(struct drm_device *dev,
2363 struct drm_file *file_priv);
2364void amdgpu_driver_preclose_kms(struct drm_device *dev,
2365 struct drm_file *file_priv);
2366int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2367int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2368u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2369int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2370void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2371int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2372 int *max_error,
2373 struct timeval *vblank_time,
2374 unsigned flags);
2375long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2376 unsigned long arg);
2377
97b2e202
AD		 2378/*
2379 * functions used by amdgpu_encoder.c
2380 */
2381struct amdgpu_afmt_acr {
2382 u32 clock;
2383
2384 int n_32khz;
2385 int cts_32khz;
2386
2387 int n_44_1khz;
2388 int cts_44_1khz;
2389
2390 int n_48khz;
2391 int cts_48khz;
2392
2393};
2394
2395struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2396
2397/* amdgpu_acpi.c */
2398#if defined(CONFIG_ACPI)
2399int amdgpu_acpi_init(struct amdgpu_device *adev);
2400void amdgpu_acpi_fini(struct amdgpu_device *adev);
2401bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2402int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2403 u8 perf_req, bool advertise);
2404int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2405#else
2406static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2407static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2408#endif
2409
2410struct amdgpu_bo_va_mapping *
2411amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2412 uint64_t addr, struct amdgpu_bo **bo);
2413
2414#include "amdgpu_object.h"
97b2e202 2415#endif
Linux kernel - Deliverables
This page took 0.235051 seconds and 5 git commands to generate.