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drm/amdgpu: Poll for both connect/disconnect on analog connectors
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
6bb6b297 88extern int amdgpu_powercontainment;
cd474ba0
AD		 89extern unsigned amdgpu_pcie_gen_cap;
90extern unsigned amdgpu_pcie_lane_cap;
395d1fb9
NH		 91extern unsigned amdgpu_cg_mask;
92extern unsigned amdgpu_pg_mask;
6f8941a2 93extern char *amdgpu_disable_cu;
97b2e202 94
4b559c90 95#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 96#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
97#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
98/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
99#define AMDGPU_IB_POOL_SIZE 16
100#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
101#define AMDGPUFB_CONN_LIMIT 4
102#define AMDGPU_BIOS_NUM_SCRATCH 8
103
97b2e202
AD		 104/* max number of rings */
105#define AMDGPU_MAX_RINGS 16
106#define AMDGPU_MAX_GFX_RINGS 1
107#define AMDGPU_MAX_COMPUTE_RINGS 8
108#define AMDGPU_MAX_VCE_RINGS 2
109
36f523a7
JZ		 110/* max number of IP instances */
111#define AMDGPU_MAX_SDMA_INSTANCES 2
112
97b2e202
AD		 113/* hardcode that limit for now */
114#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
115
116/* hard reset data */
117#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
118
119/* reset flags */
120#define AMDGPU_RESET_GFX (1 << 0)
121#define AMDGPU_RESET_COMPUTE (1 << 1)
122#define AMDGPU_RESET_DMA (1 << 2)
123#define AMDGPU_RESET_CP (1 << 3)
124#define AMDGPU_RESET_GRBM (1 << 4)
125#define AMDGPU_RESET_DMA1 (1 << 5)
126#define AMDGPU_RESET_RLC (1 << 6)
127#define AMDGPU_RESET_SEM (1 << 7)
128#define AMDGPU_RESET_IH (1 << 8)
129#define AMDGPU_RESET_VMC (1 << 9)
130#define AMDGPU_RESET_MC (1 << 10)
131#define AMDGPU_RESET_DISPLAY (1 << 11)
132#define AMDGPU_RESET_UVD (1 << 12)
133#define AMDGPU_RESET_VCE (1 << 13)
134#define AMDGPU_RESET_VCE1 (1 << 14)
135
97b2e202
AD		 136/* GFX current status */
137#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
138#define AMDGPU_GFX_SAFE_MODE 0x00000001L
139#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
140#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
141#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
142
143/* max cursor sizes (in pixels) */
144#define CIK_CURSOR_WIDTH 128
145#define CIK_CURSOR_HEIGHT 128
146
147struct amdgpu_device;
97b2e202
AD		 148struct amdgpu_ib;
149struct amdgpu_vm;
150struct amdgpu_ring;
97b2e202 151struct amdgpu_cs_parser;
bb977d37 152struct amdgpu_job;
97b2e202 153struct amdgpu_irq_src;
0b492a4c 154struct amdgpu_fpriv;
97b2e202
AD		 155
156enum amdgpu_cp_irq {
157 AMDGPU_CP_IRQ_GFX_EOP = 0,
158 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
166
167 AMDGPU_CP_IRQ_LAST
168};
169
170enum amdgpu_sdma_irq {
171 AMDGPU_SDMA_IRQ_TRAP0 = 0,
172 AMDGPU_SDMA_IRQ_TRAP1,
173
174 AMDGPU_SDMA_IRQ_LAST
175};
176
177enum amdgpu_thermal_irq {
178 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
179 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
180
181 AMDGPU_THERMAL_IRQ_LAST
182};
183
97b2e202 184int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 185 enum amd_ip_block_type block_type,
186 enum amd_clockgating_state state);
97b2e202 187int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 188 enum amd_ip_block_type block_type,
189 enum amd_powergating_state state);
5dbbb60b
AD		 190int amdgpu_wait_for_idle(struct amdgpu_device *adev,
191 enum amd_ip_block_type block_type);
192bool amdgpu_is_idle(struct amdgpu_device *adev,
193 enum amd_ip_block_type block_type);
97b2e202
AD		 194
195struct amdgpu_ip_block_version {
5fc3aeeb 196 enum amd_ip_block_type type;
97b2e202
AD		 197 u32 major;
198 u32 minor;
199 u32 rev;
5fc3aeeb 200 const struct amd_ip_funcs *funcs;
97b2e202
AD		 201};
202
203int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 204 enum amd_ip_block_type type,
97b2e202
AD		 205 u32 major, u32 minor);
206
207const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
208 struct amdgpu_device *adev,
5fc3aeeb 209 enum amd_ip_block_type type);
97b2e202
AD		 210
211/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
212struct amdgpu_buffer_funcs {
213 /* maximum bytes in a single operation */
214 uint32_t copy_max_bytes;
215
216 /* number of dw to reserve per operation */
217 unsigned copy_num_dw;
218
219 /* used for buffer migration */
c7ae72c0 220 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 221 /* src addr in bytes */
222 uint64_t src_offset,
223 /* dst addr in bytes */
224 uint64_t dst_offset,
225 /* number of byte to transfer */
226 uint32_t byte_count);
227
228 /* maximum bytes in a single operation */
229 uint32_t fill_max_bytes;
230
231 /* number of dw to reserve per operation */
232 unsigned fill_num_dw;
233
234 /* used for buffer clearing */
6e7a3840 235 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 236 /* value to write to memory */
237 uint32_t src_data,
238 /* dst addr in bytes */
239 uint64_t dst_offset,
240 /* number of byte to fill */
241 uint32_t byte_count);
242};
243
244/* provided by hw blocks that can write ptes, e.g., sdma */
245struct amdgpu_vm_pte_funcs {
246 /* copy pte entries from GART */
247 void (*copy_pte)(struct amdgpu_ib *ib,
248 uint64_t pe, uint64_t src,
249 unsigned count);
250 /* write pte one entry at a time with addr mapping */
251 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 252 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 253 uint64_t addr, unsigned count,
254 uint32_t incr, uint32_t flags);
255 /* for linear pte/pde updates without addr mapping */
256 void (*set_pte_pde)(struct amdgpu_ib *ib,
257 uint64_t pe,
258 uint64_t addr, unsigned count,
259 uint32_t incr, uint32_t flags);
97b2e202
AD		 260};
261
262/* provided by the gmc block */
263struct amdgpu_gart_funcs {
264 /* flush the vm tlb via mmio */
265 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
266 uint32_t vmid);
267 /* write pte/pde updates using the cpu */
268 int (*set_pte_pde)(struct amdgpu_device *adev,
269 void *cpu_pt_addr, /* cpu addr of page table */
270 uint32_t gpu_page_idx, /* pte/pde to update */
271 uint64_t addr, /* addr to write into pte/pde */
272 uint32_t flags); /* access flags */
273};
274
275/* provided by the ih block */
276struct amdgpu_ih_funcs {
277 /* ring read/write ptr handling, called from interrupt context */
278 u32 (*get_wptr)(struct amdgpu_device *adev);
279 void (*decode_iv)(struct amdgpu_device *adev,
280 struct amdgpu_iv_entry *entry);
281 void (*set_rptr)(struct amdgpu_device *adev);
282};
283
284/* provided by hw blocks that expose a ring buffer for commands */
285struct amdgpu_ring_funcs {
286 /* ring read/write ptr handling */
287 u32 (*get_rptr)(struct amdgpu_ring *ring);
288 u32 (*get_wptr)(struct amdgpu_ring *ring);
289 void (*set_wptr)(struct amdgpu_ring *ring);
290 /* validating and patching of IBs */
291 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
292 /* command emit functions */
293 void (*emit_ib)(struct amdgpu_ring *ring,
d88bf583
CK		 294 struct amdgpu_ib *ib,
295 unsigned vm_id, bool ctx_switch);
97b2e202 296 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 297 uint64_t seq, unsigned flags);
b8c7b39e 298 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
97b2e202
AD		 299 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
300 uint64_t pd_addr);
d2edb07b 301 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
11afbde8 302 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
97b2e202
AD		 303 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
304 uint32_t gds_base, uint32_t gds_size,
305 uint32_t gws_base, uint32_t gws_size,
306 uint32_t oa_base, uint32_t oa_size);
307 /* testing functions */
308 int (*test_ring)(struct amdgpu_ring *ring);
309 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 310 /* insert NOP packets */
311 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 312 /* pad the indirect buffer to the necessary number of dw */
313 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
03ccf481
ML		 314 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
315 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
97b2e202
AD		 316};
317
318/*
319 * BIOS.
320 */
321bool amdgpu_get_bios(struct amdgpu_device *adev);
322bool amdgpu_read_bios(struct amdgpu_device *adev);
323
324/*
325 * Dummy page
326 */
327struct amdgpu_dummy_page {
328 struct page *page;
329 dma_addr_t addr;
330};
331int amdgpu_dummy_page_init(struct amdgpu_device *adev);
332void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
333
334
335/*
336 * Clocks
337 */
338
339#define AMDGPU_MAX_PPLL 3
340
341struct amdgpu_clock {
342 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
343 struct amdgpu_pll spll;
344 struct amdgpu_pll mpll;
345 /* 10 Khz units */
346 uint32_t default_mclk;
347 uint32_t default_sclk;
348 uint32_t default_dispclk;
349 uint32_t current_dispclk;
350 uint32_t dp_extclk;
351 uint32_t max_pixel_clock;
352};
353
354/*
355 * Fences.
356 */
357struct amdgpu_fence_driver {
97b2e202
AD		 358 uint64_t gpu_addr;
359 volatile uint32_t *cpu_addr;
360 /* sync_seq is protected by ring emission lock */
742c085f
CK		 361 uint32_t sync_seq;
362 atomic_t last_seq;
97b2e202 363 bool initialized;
97b2e202
AD		 364 struct amdgpu_irq_src *irq_src;
365 unsigned irq_type;
c2776afe 366 struct timer_list fallback_timer;
c89377d1 367 unsigned num_fences_mask;
4a7d74f1 368 spinlock_t lock;
c89377d1 369 struct fence **fences;
97b2e202
AD		 370};
371
372/* some special values for the owner field */
373#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
374#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 375
890ee23f
CZ		 376#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
377#define AMDGPU_FENCE_FLAG_INT (1 << 1)
378
97b2e202
AD		 379int amdgpu_fence_driver_init(struct amdgpu_device *adev);
380void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
381void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
382
e6151a08
CK		 383int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
384 unsigned num_hw_submission);
97b2e202
AD		 385int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
386 struct amdgpu_irq_src *irq_src,
387 unsigned irq_type);
5ceb54c6
AD		 388void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
389void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
364beb2c 390int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
97b2e202 391void amdgpu_fence_process(struct amdgpu_ring *ring);
97b2e202
AD		 392int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
393unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
394
97b2e202
AD		 395/*
396 * TTM.
397 */
29b3259a
CK		 398
399#define AMDGPU_TTM_LRU_SIZE 20
400
401struct amdgpu_mman_lru {
402 struct list_head *lru[TTM_NUM_MEM_TYPES];
403 struct list_head *swap_lru;
404};
405
97b2e202
AD		 406struct amdgpu_mman {
407 struct ttm_bo_global_ref bo_global_ref;
408 struct drm_global_reference mem_global_ref;
409 struct ttm_bo_device bdev;
410 bool mem_global_referenced;
411 bool initialized;
412
413#if defined(CONFIG_DEBUG_FS)
414 struct dentry *vram;
415 struct dentry *gtt;
416#endif
417
418 /* buffer handling */
419 const struct amdgpu_buffer_funcs *buffer_funcs;
420 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 421 /* Scheduler entity for buffer moves */
422 struct amd_sched_entity entity;
29b3259a
CK		 423
424 /* custom LRU management */
425 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
97b2e202
AD		 426};
427
428int amdgpu_copy_buffer(struct amdgpu_ring *ring,
429 uint64_t src_offset,
430 uint64_t dst_offset,
431 uint32_t byte_count,
432 struct reservation_object *resv,
c7ae72c0 433 struct fence **fence);
97b2e202
AD		 434int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
435
436struct amdgpu_bo_list_entry {
437 struct amdgpu_bo *robj;
438 struct ttm_validate_buffer tv;
439 struct amdgpu_bo_va *bo_va;
97b2e202 440 uint32_t priority;
2f568dbd
CK		 441 struct page **user_pages;
442 int user_invalidated;
97b2e202
AD		 443};
444
445struct amdgpu_bo_va_mapping {
446 struct list_head list;
447 struct interval_tree_node it;
448 uint64_t offset;
449 uint32_t flags;
450};
451
452/* bo virtual addresses in a specific vm */
453struct amdgpu_bo_va {
454 /* protected by bo being reserved */
455 struct list_head bo_list;
bb1e38a4 456 struct fence *last_pt_update;
97b2e202
AD		 457 unsigned ref_count;
458
7fc11959 459 /* protected by vm mutex and spinlock */
97b2e202
AD		 460 struct list_head vm_status;
461
7fc11959
CK		 462 /* mappings for this bo_va */
463 struct list_head invalids;
464 struct list_head valids;
465
97b2e202
AD		 466 /* constant after initialization */
467 struct amdgpu_vm *vm;
468 struct amdgpu_bo *bo;
469};
470
7e5a547f
CZ		 471#define AMDGPU_GEM_DOMAIN_MAX 0x3
472
97b2e202
AD		 473struct amdgpu_bo {
474 /* Protected by gem.mutex */
475 struct list_head list;
476 /* Protected by tbo.reserved */
1ea863fd
CK		 477 u32 prefered_domains;
478 u32 allowed_domains;
7e5a547f 479 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 480 struct ttm_placement placement;
481 struct ttm_buffer_object tbo;
482 struct ttm_bo_kmap_obj kmap;
483 u64 flags;
484 unsigned pin_count;
485 void *kptr;
486 u64 tiling_flags;
487 u64 metadata_flags;
488 void *metadata;
489 u32 metadata_size;
490 /* list of all virtual address to which this bo
491 * is associated to
492 */
493 struct list_head va;
494 /* Constant after initialization */
495 struct amdgpu_device *adev;
496 struct drm_gem_object gem_base;
82b9c55b 497 struct amdgpu_bo *parent;
97b2e202
AD		 498
499 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 500 struct amdgpu_mn *mn;
501 struct list_head mn_list;
502};
503#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
504
505void amdgpu_gem_object_free(struct drm_gem_object *obj);
506int amdgpu_gem_object_open(struct drm_gem_object *obj,
507 struct drm_file *file_priv);
508void amdgpu_gem_object_close(struct drm_gem_object *obj,
509 struct drm_file *file_priv);
510unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
511struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4d9c514d
CK		 512struct drm_gem_object *
513amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
514 struct dma_buf_attachment *attach,
515 struct sg_table *sg);
97b2e202
AD		 516struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
517 struct drm_gem_object *gobj,
518 int flags);
519int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
520void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
521struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
522void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
523void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
524int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
525
526/* sub-allocation manager, it has to be protected by another lock.
527 * By conception this is an helper for other part of the driver
528 * like the indirect buffer or semaphore, which both have their
529 * locking.
530 *
531 * Principe is simple, we keep a list of sub allocation in offset
532 * order (first entry has offset == 0, last entry has the highest
533 * offset).
534 *
535 * When allocating new object we first check if there is room at
536 * the end total_size - (last_object_offset + last_object_size) >=
537 * alloc_size. If so we allocate new object there.
538 *
539 * When there is not enough room at the end, we start waiting for
540 * each sub object until we reach object_offset+object_size >=
541 * alloc_size, this object then become the sub object we return.
542 *
543 * Alignment can't be bigger than page size.
544 *
545 * Hole are not considered for allocation to keep things simple.
546 * Assumption is that there won't be hole (all object on same
547 * alignment).
548 */
6ba60b89
CK		 549
550#define AMDGPU_SA_NUM_FENCE_LISTS 32
551
97b2e202
AD		 552struct amdgpu_sa_manager {
553 wait_queue_head_t wq;
554 struct amdgpu_bo *bo;
555 struct list_head *hole;
6ba60b89 556 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
97b2e202
AD		 557 struct list_head olist;
558 unsigned size;
559 uint64_t gpu_addr;
560 void *cpu_ptr;
561 uint32_t domain;
562 uint32_t align;
563};
564
97b2e202
AD		 565/* sub-allocation buffer */
566struct amdgpu_sa_bo {
567 struct list_head olist;
568 struct list_head flist;
569 struct amdgpu_sa_manager *manager;
570 unsigned soffset;
571 unsigned eoffset;
4ce9891e 572 struct fence *fence;
97b2e202
AD		 573};
574
575/*
576 * GEM objects.
577 */
418aa0c2 578void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 579int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
580 int alignment, u32 initial_domain,
581 u64 flags, bool kernel,
582 struct drm_gem_object **obj);
583
584int amdgpu_mode_dumb_create(struct drm_file *file_priv,
585 struct drm_device *dev,
586 struct drm_mode_create_dumb *args);
587int amdgpu_mode_dumb_mmap(struct drm_file *filp,
588 struct drm_device *dev,
589 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 590/*
591 * Synchronization
592 */
593struct amdgpu_sync {
f91b3a69 594 DECLARE_HASHTABLE(fences, 4);
3c62338c 595 struct fence *last_vm_update;
97b2e202
AD		 596};
597
598void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 599int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
600 struct fence *f);
97b2e202
AD		 601int amdgpu_sync_resv(struct amdgpu_device *adev,
602 struct amdgpu_sync *sync,
603 struct reservation_object *resv,
604 void *owner);
1fbb2e92
CK		 605struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
606 struct amdgpu_ring *ring);
e61235db 607struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
8a8f0b48 608void amdgpu_sync_free(struct amdgpu_sync *sync);
257bf15a
CK		 609int amdgpu_sync_init(void);
610void amdgpu_sync_fini(void);
d573de2d
RZ		 611int amdgpu_fence_slab_init(void);
612void amdgpu_fence_slab_fini(void);
97b2e202
AD		 613
614/*
615 * GART structures, functions & helpers
616 */
617struct amdgpu_mc;
618
619#define AMDGPU_GPU_PAGE_SIZE 4096
620#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
621#define AMDGPU_GPU_PAGE_SHIFT 12
622#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
623
624struct amdgpu_gart {
625 dma_addr_t table_addr;
626 struct amdgpu_bo *robj;
627 void *ptr;
628 unsigned num_gpu_pages;
629 unsigned num_cpu_pages;
630 unsigned table_size;
a1d29476 631#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
97b2e202 632 struct page **pages;
a1d29476 633#endif
97b2e202
AD		 634 bool ready;
635 const struct amdgpu_gart_funcs *gart_funcs;
636};
637
638int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
639void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
640int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
641void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
642int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
643void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
644int amdgpu_gart_init(struct amdgpu_device *adev);
645void amdgpu_gart_fini(struct amdgpu_device *adev);
646void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
647 int pages);
648int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
649 int pages, struct page **pagelist,
650 dma_addr_t *dma_addr, uint32_t flags);
651
652/*
653 * GPU MC structures, functions & helpers
654 */
655struct amdgpu_mc {
656 resource_size_t aper_size;
657 resource_size_t aper_base;
658 resource_size_t agp_base;
659 /* for some chips with <= 32MB we need to lie
660 * about vram size near mc fb location */
661 u64 mc_vram_size;
662 u64 visible_vram_size;
663 u64 gtt_size;
664 u64 gtt_start;
665 u64 gtt_end;
666 u64 vram_start;
667 u64 vram_end;
668 unsigned vram_width;
669 u64 real_vram_size;
670 int vram_mtrr;
671 u64 gtt_base_align;
672 u64 mc_mask;
673 const struct firmware *fw; /* MC firmware */
674 uint32_t fw_version;
675 struct amdgpu_irq_src vm_fault;
81c59f54 676 uint32_t vram_type;
97b2e202
AD		 677};
678
679/*
680 * GPU doorbell structures, functions & helpers
681 */
682typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
683{
684 AMDGPU_DOORBELL_KIQ = 0x000,
685 AMDGPU_DOORBELL_HIQ = 0x001,
686 AMDGPU_DOORBELL_DIQ = 0x002,
687 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
688 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
689 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
690 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
691 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
692 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
693 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
694 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
695 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
696 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
697 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
698 AMDGPU_DOORBELL_IH = 0x1E8,
699 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
700 AMDGPU_DOORBELL_INVALID = 0xFFFF
701} AMDGPU_DOORBELL_ASSIGNMENT;
702
703struct amdgpu_doorbell {
704 /* doorbell mmio */
705 resource_size_t base;
706 resource_size_t size;
707 u32 __iomem *ptr;
708 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
709};
710
711void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
712 phys_addr_t *aperture_base,
713 size_t *aperture_size,
714 size_t *start_offset);
715
716/*
717 * IRQS.
718 */
719
720struct amdgpu_flip_work {
721 struct work_struct flip_work;
722 struct work_struct unpin_work;
723 struct amdgpu_device *adev;
724 int crtc_id;
725 uint64_t base;
726 struct drm_pending_vblank_event *event;
727 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 728 struct fence *excl;
729 unsigned shared_count;
730 struct fence **shared;
c3874b75 731 struct fence_cb cb;
cb9e59d7 732 bool async;
97b2e202
AD		 733};
734
735
736/*
737 * CP & rings.
738 */
739
740struct amdgpu_ib {
741 struct amdgpu_sa_bo *sa_bo;
742 uint32_t length_dw;
743 uint64_t gpu_addr;
744 uint32_t *ptr;
de807f81 745 uint32_t flags;
97b2e202
AD		 746};
747
748enum amdgpu_ring_type {
749 AMDGPU_RING_TYPE_GFX,
750 AMDGPU_RING_TYPE_COMPUTE,
751 AMDGPU_RING_TYPE_SDMA,
752 AMDGPU_RING_TYPE_UVD,
753 AMDGPU_RING_TYPE_VCE
754};
755
62250a91 756extern const struct amd_sched_backend_ops amdgpu_sched_ops;
c1b69ed0 757
50838c8c 758int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
c5637837 759 struct amdgpu_job **job, struct amdgpu_vm *vm);
d71518b5
CK		 760int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
761 struct amdgpu_job **job);
b6723c8d 762
50838c8c 763void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 764int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 765 struct amd_sched_entity *entity, void *owner,
766 struct fence **f);
3c704e93 767
97b2e202
AD		 768struct amdgpu_ring {
769 struct amdgpu_device *adev;
770 const struct amdgpu_ring_funcs *funcs;
771 struct amdgpu_fence_driver fence_drv;
edf600da 772 struct amd_gpu_scheduler sched;
97b2e202 773
176e1ab1 774 spinlock_t fence_lock;
97b2e202
AD		 775 struct amdgpu_bo *ring_obj;
776 volatile uint32_t *ring;
777 unsigned rptr_offs;
778 u64 next_rptr_gpu_addr;
779 volatile u32 *next_rptr_cpu_addr;
780 unsigned wptr;
781 unsigned wptr_old;
782 unsigned ring_size;
c7e6be23 783 unsigned max_dw;
97b2e202 784 int count_dw;
97b2e202
AD		 785 uint64_t gpu_addr;
786 uint32_t align_mask;
787 uint32_t ptr_mask;
788 bool ready;
789 u32 nop;
790 u32 idx;
97b2e202
AD		 791 u32 me;
792 u32 pipe;
793 u32 queue;
794 struct amdgpu_bo *mqd_obj;
795 u32 doorbell_index;
796 bool use_doorbell;
797 unsigned wptr_offs;
798 unsigned next_rptr_offs;
799 unsigned fence_offs;
aa3b73f6 800 uint64_t current_ctx;
97b2e202
AD		 801 enum amdgpu_ring_type type;
802 char name[16];
128cff1a
ML		 803 unsigned cond_exe_offs;
804 u64 cond_exe_gpu_addr;
805 volatile u32 *cond_exe_cpu_addr;
a909c6bd
ML		 806#if defined(CONFIG_DEBUG_FS)
807 struct dentry *ent;
808#endif
97b2e202
AD		 809};
810
811/*
812 * VM
813 */
814
815/* maximum number of VMIDs */
816#define AMDGPU_NUM_VM 16
817
818/* number of entries in page table */
819#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
820
821/* PTBs (Page Table Blocks) need to be aligned to 32K */
822#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
823#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
824#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
825
826#define AMDGPU_PTE_VALID (1 << 0)
827#define AMDGPU_PTE_SYSTEM (1 << 1)
828#define AMDGPU_PTE_SNOOPED (1 << 2)
829
830/* VI only */
831#define AMDGPU_PTE_EXECUTABLE (1 << 4)
832
833#define AMDGPU_PTE_READABLE (1 << 5)
834#define AMDGPU_PTE_WRITEABLE (1 << 6)
835
836/* PTE (Page Table Entry) fragment field for different page sizes */
837#define AMDGPU_PTE_FRAG_4KB (0 << 7)
838#define AMDGPU_PTE_FRAG_64KB (4 << 7)
839#define AMDGPU_LOG2_PAGES_PER_FRAG 4
840
d9c13156
CK		 841/* How to programm VM fault handling */
842#define AMDGPU_VM_FAULT_STOP_NEVER 0
843#define AMDGPU_VM_FAULT_STOP_FIRST 1
844#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
845
97b2e202 846struct amdgpu_vm_pt {
ee1782c3
CK		 847 struct amdgpu_bo_list_entry entry;
848 uint64_t addr;
97b2e202
AD		 849};
850
97b2e202 851struct amdgpu_vm {
25cfc3c2 852 /* tree of virtual addresses mapped */
97b2e202
AD		 853 struct rb_root va;
854
7fc11959 855 /* protecting invalidated */
97b2e202
AD		 856 spinlock_t status_lock;
857
858 /* BOs moved, but not yet updated in the PT */
859 struct list_head invalidated;
860
7fc11959
CK		 861 /* BOs cleared in the PT because of a move */
862 struct list_head cleared;
863
864 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 865 struct list_head freed;
866
867 /* contains the page directory */
868 struct amdgpu_bo *page_directory;
869 unsigned max_pde_used;
05906dec 870 struct fence *page_directory_fence;
5a712a87 871 uint64_t last_eviction_counter;
97b2e202
AD		 872
873 /* array of page tables, one for each page directory entry */
874 struct amdgpu_vm_pt *page_tables;
875
876 /* for id and flush management per ring */
bcb1ba35 877 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
25cfc3c2 878
81d75a30 879 /* protecting freed */
880 spinlock_t freed_lock;
2bd9ccfa
CK		 881
882 /* Scheduler entity for page table updates */
883 struct amd_sched_entity entity;
031e2983
CZ		 884
885 /* client id */
886 u64 client_id;
97b2e202
AD		 887};
888
bcb1ba35 889struct amdgpu_vm_id {
a9a78b32 890 struct list_head list;
832a902f
CK		 891 struct fence *first;
892 struct amdgpu_sync active;
41d9eb2c 893 struct fence *last_flush;
0ea54b9b 894 atomic64_t owner;
971fe9a9 895
bcb1ba35
CK		 896 uint64_t pd_gpu_addr;
897 /* last flushed PD/PT update */
898 struct fence *flushed_updates;
899
6adb0513
CZ		 900 uint32_t current_gpu_reset_count;
901
971fe9a9
CK		 902 uint32_t gds_base;
903 uint32_t gds_size;
904 uint32_t gws_base;
905 uint32_t gws_size;
906 uint32_t oa_base;
907 uint32_t oa_size;
a9a78b32
CK		 908};
909
97b2e202 910struct amdgpu_vm_manager {
a9a78b32 911 /* Handling of VMIDs */
8d0a7cea 912 struct mutex lock;
a9a78b32
CK		 913 unsigned num_ids;
914 struct list_head ids_lru;
bcb1ba35 915 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
1c16c0a7 916
1fbb2e92
CK		 917 /* Handling of VM fences */
918 u64 fence_context;
919 unsigned seqno[AMDGPU_MAX_RINGS];
920
8b4fb00b 921 uint32_t max_pfn;
97b2e202 922 /* vram base address for page table entry */
8b4fb00b 923 u64 vram_base_offset;
97b2e202 924 /* is vm enabled? */
8b4fb00b 925 bool enabled;
97b2e202
AD		 926 /* vm pte handling */
927 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 928 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
929 unsigned vm_pte_num_rings;
930 atomic_t vm_pte_next_ring;
031e2983
CZ		 931 /* client id counter */
932 atomic64_t client_counter;
97b2e202
AD		 933};
934
a9a78b32 935void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 936void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 937int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
938void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 939void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
940 struct list_head *validated,
941 struct amdgpu_bo_list_entry *entry);
5a712a87
CK		 942void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
943 struct list_head *duplicates);
eceb8a15
CK		 944void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
945 struct amdgpu_vm *vm);
8b4fb00b 946int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
4ff37a83
CK		 947 struct amdgpu_sync *sync, struct fence *fence,
948 unsigned *vm_id, uint64_t *vm_pd_addr);
41d9eb2c
CK		 949int amdgpu_vm_flush(struct amdgpu_ring *ring,
950 unsigned vm_id, uint64_t pd_addr,
951 uint32_t gds_base, uint32_t gds_size,
952 uint32_t gws_base, uint32_t gws_size,
953 uint32_t oa_base, uint32_t oa_size);
971fe9a9 954void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
b07c9d2a 955uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 956int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
957 struct amdgpu_vm *vm);
958int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm);
960int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
961 struct amdgpu_sync *sync);
962int amdgpu_vm_bo_update(struct amdgpu_device *adev,
963 struct amdgpu_bo_va *bo_va,
964 struct ttm_mem_reg *mem);
965void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
966 struct amdgpu_bo *bo);
967struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
968 struct amdgpu_bo *bo);
969struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
970 struct amdgpu_vm *vm,
971 struct amdgpu_bo *bo);
972int amdgpu_vm_bo_map(struct amdgpu_device *adev,
973 struct amdgpu_bo_va *bo_va,
974 uint64_t addr, uint64_t offset,
975 uint64_t size, uint32_t flags);
976int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
977 struct amdgpu_bo_va *bo_va,
978 uint64_t addr);
979void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
980 struct amdgpu_bo_va *bo_va);
8b4fb00b 981
97b2e202
AD		 982/*
983 * context related structures
984 */
985
21c16bf6 986struct amdgpu_ctx_ring {
91404fb2 987 uint64_t sequence;
37cd0ca2 988 struct fence **fences;
91404fb2 989 struct amd_sched_entity entity;
21c16bf6
CK		 990};
991
97b2e202 992struct amdgpu_ctx {
0b492a4c 993 struct kref refcount;
9cb7e5a9 994 struct amdgpu_device *adev;
0b492a4c 995 unsigned reset_counter;
21c16bf6 996 spinlock_t ring_lock;
37cd0ca2 997 struct fence **fences;
21c16bf6 998 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 999};
1000
1001struct amdgpu_ctx_mgr {
0b492a4c
AD		 1002 struct amdgpu_device *adev;
1003 struct mutex lock;
1004 /* protected by lock */
1005 struct idr ctx_handles;
97b2e202
AD		 1006};
1007
0b492a4c
AD		 1008struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1009int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1010
21c16bf6 1011uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1012 struct fence *fence);
21c16bf6
CK		 1013struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1014 struct amdgpu_ring *ring, uint64_t seq);
1015
0b492a4c
AD		 1016int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1017 struct drm_file *filp);
1018
efd4ccb5
CK		 1019void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1020void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1021
97b2e202
AD		 1022/*
1023 * file private structure
1024 */
1025
1026struct amdgpu_fpriv {
1027 struct amdgpu_vm vm;
1028 struct mutex bo_list_lock;
1029 struct idr bo_list_handles;
0b492a4c 1030 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1031};
1032
1033/*
1034 * residency list
1035 */
1036
1037struct amdgpu_bo_list {
1038 struct mutex lock;
1039 struct amdgpu_bo *gds_obj;
1040 struct amdgpu_bo *gws_obj;
1041 struct amdgpu_bo *oa_obj;
211dff55 1042 unsigned first_userptr;
97b2e202
AD		 1043 unsigned num_entries;
1044 struct amdgpu_bo_list_entry *array;
1045};
1046
1047struct amdgpu_bo_list *
1048amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1049void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1050 struct list_head *validated);
97b2e202
AD		 1051void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1052void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1053
1054/*
1055 * GFX stuff
1056 */
1057#include "clearstate_defs.h"
1058
79e5412c
AD		 1059struct amdgpu_rlc_funcs {
1060 void (*enter_safe_mode)(struct amdgpu_device *adev);
1061 void (*exit_safe_mode)(struct amdgpu_device *adev);
1062};
1063
97b2e202
AD		 1064struct amdgpu_rlc {
1065 /* for power gating */
1066 struct amdgpu_bo *save_restore_obj;
1067 uint64_t save_restore_gpu_addr;
1068 volatile uint32_t *sr_ptr;
1069 const u32 *reg_list;
1070 u32 reg_list_size;
1071 /* for clear state */
1072 struct amdgpu_bo *clear_state_obj;
1073 uint64_t clear_state_gpu_addr;
1074 volatile uint32_t *cs_ptr;
1075 const struct cs_section_def *cs_data;
1076 u32 clear_state_size;
1077 /* for cp tables */
1078 struct amdgpu_bo *cp_table_obj;
1079 uint64_t cp_table_gpu_addr;
1080 volatile uint32_t *cp_table_ptr;
1081 u32 cp_table_size;
79e5412c
AD		 1082
1083 /* safe mode for updating CG/PG state */
1084 bool in_safe_mode;
1085 const struct amdgpu_rlc_funcs *funcs;
2b6cd977
EH		 1086
1087 /* for firmware data */
1088 u32 save_and_restore_offset;
1089 u32 clear_state_descriptor_offset;
1090 u32 avail_scratch_ram_locations;
1091 u32 reg_restore_list_size;
1092 u32 reg_list_format_start;
1093 u32 reg_list_format_separate_start;
1094 u32 starting_offsets_start;
1095 u32 reg_list_format_size_bytes;
1096 u32 reg_list_size_bytes;
1097
1098 u32 *register_list_format;
1099 u32 *register_restore;
97b2e202
AD		 1100};
1101
1102struct amdgpu_mec {
1103 struct amdgpu_bo *hpd_eop_obj;
1104 u64 hpd_eop_gpu_addr;
1105 u32 num_pipe;
1106 u32 num_mec;
1107 u32 num_queue;
1108};
1109
1110/*
1111 * GPU scratch registers structures, functions & helpers
1112 */
1113struct amdgpu_scratch {
1114 unsigned num_reg;
1115 uint32_t reg_base;
1116 bool free[32];
1117 uint32_t reg[32];
1118};
1119
1120/*
1121 * GFX configurations
1122 */
1123struct amdgpu_gca_config {
1124 unsigned max_shader_engines;
1125 unsigned max_tile_pipes;
1126 unsigned max_cu_per_sh;
1127 unsigned max_sh_per_se;
1128 unsigned max_backends_per_se;
1129 unsigned max_texture_channel_caches;
1130 unsigned max_gprs;
1131 unsigned max_gs_threads;
1132 unsigned max_hw_contexts;
1133 unsigned sc_prim_fifo_size_frontend;
1134 unsigned sc_prim_fifo_size_backend;
1135 unsigned sc_hiz_tile_fifo_size;
1136 unsigned sc_earlyz_tile_fifo_size;
1137
1138 unsigned num_tile_pipes;
1139 unsigned backend_enable_mask;
1140 unsigned mem_max_burst_length_bytes;
1141 unsigned mem_row_size_in_kb;
1142 unsigned shader_engine_tile_size;
1143 unsigned num_gpus;
1144 unsigned multi_gpu_tile_size;
1145 unsigned mc_arb_ramcfg;
1146 unsigned gb_addr_config;
8f8e00c1 1147 unsigned num_rbs;
97b2e202
AD		 1148
1149 uint32_t tile_mode_array[32];
1150 uint32_t macrotile_mode_array[16];
1151};
1152
7dae69a2
AD		 1153struct amdgpu_cu_info {
1154 uint32_t number; /* total active CU number */
1155 uint32_t ao_cu_mask;
1156 uint32_t bitmap[4][4];
1157};
1158
b95e31fd
AD		 1159struct amdgpu_gfx_funcs {
1160 /* get the gpu clock counter */
1161 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
05fb7291 1162 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num);
b95e31fd
AD		 1163};
1164
97b2e202
AD		 1165struct amdgpu_gfx {
1166 struct mutex gpu_clock_mutex;
1167 struct amdgpu_gca_config config;
1168 struct amdgpu_rlc rlc;
1169 struct amdgpu_mec mec;
1170 struct amdgpu_scratch scratch;
1171 const struct firmware *me_fw; /* ME firmware */
1172 uint32_t me_fw_version;
1173 const struct firmware *pfp_fw; /* PFP firmware */
1174 uint32_t pfp_fw_version;
1175 const struct firmware *ce_fw; /* CE firmware */
1176 uint32_t ce_fw_version;
1177 const struct firmware *rlc_fw; /* RLC firmware */
1178 uint32_t rlc_fw_version;
1179 const struct firmware *mec_fw; /* MEC firmware */
1180 uint32_t mec_fw_version;
1181 const struct firmware *mec2_fw; /* MEC2 firmware */
1182 uint32_t mec2_fw_version;
02558a00
KW		 1183 uint32_t me_feature_version;
1184 uint32_t ce_feature_version;
1185 uint32_t pfp_feature_version;
351643d7
JZ		 1186 uint32_t rlc_feature_version;
1187 uint32_t mec_feature_version;
1188 uint32_t mec2_feature_version;
97b2e202
AD		 1189 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1190 unsigned num_gfx_rings;
1191 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1192 unsigned num_compute_rings;
1193 struct amdgpu_irq_src eop_irq;
1194 struct amdgpu_irq_src priv_reg_irq;
1195 struct amdgpu_irq_src priv_inst_irq;
1196 /* gfx status */
7dae69a2 1197 uint32_t gfx_current_status;
a101a899 1198 /* ce ram size*/
7dae69a2
AD		 1199 unsigned ce_ram_size;
1200 struct amdgpu_cu_info cu_info;
b95e31fd 1201 const struct amdgpu_gfx_funcs *funcs;
97b2e202
AD		 1202};
1203
b07c60c0 1204int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202 1205 unsigned size, struct amdgpu_ib *ib);
4d9c514d
CK		 1206void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1207 struct fence *f);
b07c60c0 1208int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 1209 struct amdgpu_ib *ib, struct fence *last_vm_update,
c5637837 1210 struct amdgpu_job *job, struct fence **f);
97b2e202
AD		 1211int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1212void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1213int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1214int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1215void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1216void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1217void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1218void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1219unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1220 uint32_t **data);
1221int amdgpu_ring_restore(struct amdgpu_ring *ring,
1222 unsigned size, uint32_t *data);
1223int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1224 unsigned ring_size, u32 nop, u32 align_mask,
1225 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1226 enum amdgpu_ring_type ring_type);
1227void amdgpu_ring_fini(struct amdgpu_ring *ring);
1228
1229/*
1230 * CS.
1231 */
1232struct amdgpu_cs_chunk {
1233 uint32_t chunk_id;
1234 uint32_t length_dw;
758ac17f 1235 void *kdata;
97b2e202
AD		 1236};
1237
1238struct amdgpu_cs_parser {
1239 struct amdgpu_device *adev;
1240 struct drm_file *filp;
3cb485f3 1241 struct amdgpu_ctx *ctx;
c3cca41e 1242
97b2e202
AD		 1243 /* chunks */
1244 unsigned nchunks;
1245 struct amdgpu_cs_chunk *chunks;
97b2e202 1246
50838c8c
CK		 1247 /* scheduler job object */
1248 struct amdgpu_job *job;
97b2e202 1249
c3cca41e
CK		 1250 /* buffer objects */
1251 struct ww_acquire_ctx ticket;
1252 struct amdgpu_bo_list *bo_list;
1253 struct amdgpu_bo_list_entry vm_pd;
1254 struct list_head validated;
1255 struct fence *fence;
1256 uint64_t bytes_moved_threshold;
1257 uint64_t bytes_moved;
97b2e202
AD		 1258
1259 /* user fence */
91acbeb6 1260 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1261};
1262
bb977d37
CZ		 1263struct amdgpu_job {
1264 struct amd_sched_job base;
1265 struct amdgpu_device *adev;
edf600da 1266 struct amdgpu_vm *vm;
b07c60c0 1267 struct amdgpu_ring *ring;
e86f9cee 1268 struct amdgpu_sync sync;
bb977d37 1269 struct amdgpu_ib *ibs;
73cfa5f5 1270 struct fence *fence; /* the hw fence */
bb977d37 1271 uint32_t num_ibs;
e2840221 1272 void *owner;
92f25098 1273 uint64_t ctx;
d88bf583
CK		 1274 unsigned vm_id;
1275 uint64_t vm_pd_addr;
1276 uint32_t gds_base, gds_size;
1277 uint32_t gws_base, gws_size;
1278 uint32_t oa_base, oa_size;
758ac17f
CK		 1279
1280 /* user fence handling */
1281 struct amdgpu_bo *uf_bo;
1282 uint32_t uf_offset;
1283 uint64_t uf_sequence;
1284
bb977d37 1285};
a6db8a33
JZ		 1286#define to_amdgpu_job(sched_job) \
1287 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1288
7270f839
CK		 1289static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1290 uint32_t ib_idx, int idx)
97b2e202 1291{
50838c8c 1292 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1293}
1294
7270f839
CK		 1295static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1296 uint32_t ib_idx, int idx,
1297 uint32_t value)
1298{
50838c8c 1299 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1300}
1301
97b2e202
AD		 1302/*
1303 * Writeback
1304 */
1305#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1306
1307struct amdgpu_wb {
1308 struct amdgpu_bo *wb_obj;
1309 volatile uint32_t *wb;
1310 uint64_t gpu_addr;
1311 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1312 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1313};
1314
1315int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1316void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1317
97b2e202 1318
97b2e202
AD		 1319
1320enum amdgpu_int_thermal_type {
1321 THERMAL_TYPE_NONE,
1322 THERMAL_TYPE_EXTERNAL,
1323 THERMAL_TYPE_EXTERNAL_GPIO,
1324 THERMAL_TYPE_RV6XX,
1325 THERMAL_TYPE_RV770,
1326 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1327 THERMAL_TYPE_EVERGREEN,
1328 THERMAL_TYPE_SUMO,
1329 THERMAL_TYPE_NI,
1330 THERMAL_TYPE_SI,
1331 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1332 THERMAL_TYPE_CI,
1333 THERMAL_TYPE_KV,
1334};
1335
1336enum amdgpu_dpm_auto_throttle_src {
1337 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1338 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1339};
1340
1341enum amdgpu_dpm_event_src {
1342 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1343 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1344 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1345 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1346 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1347};
1348
1349#define AMDGPU_MAX_VCE_LEVELS 6
1350
1351enum amdgpu_vce_level {
1352 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1353 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1354 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1355 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1356 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1357 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1358};
1359
1360struct amdgpu_ps {
1361 u32 caps; /* vbios flags */
1362 u32 class; /* vbios flags */
1363 u32 class2; /* vbios flags */
1364 /* UVD clocks */
1365 u32 vclk;
1366 u32 dclk;
1367 /* VCE clocks */
1368 u32 evclk;
1369 u32 ecclk;
1370 bool vce_active;
1371 enum amdgpu_vce_level vce_level;
1372 /* asic priv */
1373 void *ps_priv;
1374};
1375
1376struct amdgpu_dpm_thermal {
1377 /* thermal interrupt work */
1378 struct work_struct work;
1379 /* low temperature threshold */
1380 int min_temp;
1381 /* high temperature threshold */
1382 int max_temp;
1383 /* was last interrupt low to high or high to low */
1384 bool high_to_low;
1385 /* interrupt source */
1386 struct amdgpu_irq_src irq;
1387};
1388
1389enum amdgpu_clk_action
1390{
1391 AMDGPU_SCLK_UP = 1,
1392 AMDGPU_SCLK_DOWN
1393};
1394
1395struct amdgpu_blacklist_clocks
1396{
1397 u32 sclk;
1398 u32 mclk;
1399 enum amdgpu_clk_action action;
1400};
1401
1402struct amdgpu_clock_and_voltage_limits {
1403 u32 sclk;
1404 u32 mclk;
1405 u16 vddc;
1406 u16 vddci;
1407};
1408
1409struct amdgpu_clock_array {
1410 u32 count;
1411 u32 *values;
1412};
1413
1414struct amdgpu_clock_voltage_dependency_entry {
1415 u32 clk;
1416 u16 v;
1417};
1418
1419struct amdgpu_clock_voltage_dependency_table {
1420 u32 count;
1421 struct amdgpu_clock_voltage_dependency_entry *entries;
1422};
1423
1424union amdgpu_cac_leakage_entry {
1425 struct {
1426 u16 vddc;
1427 u32 leakage;
1428 };
1429 struct {
1430 u16 vddc1;
1431 u16 vddc2;
1432 u16 vddc3;
1433 };
1434};
1435
1436struct amdgpu_cac_leakage_table {
1437 u32 count;
1438 union amdgpu_cac_leakage_entry *entries;
1439};
1440
1441struct amdgpu_phase_shedding_limits_entry {
1442 u16 voltage;
1443 u32 sclk;
1444 u32 mclk;
1445};
1446
1447struct amdgpu_phase_shedding_limits_table {
1448 u32 count;
1449 struct amdgpu_phase_shedding_limits_entry *entries;
1450};
1451
1452struct amdgpu_uvd_clock_voltage_dependency_entry {
1453 u32 vclk;
1454 u32 dclk;
1455 u16 v;
1456};
1457
1458struct amdgpu_uvd_clock_voltage_dependency_table {
1459 u8 count;
1460 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1461};
1462
1463struct amdgpu_vce_clock_voltage_dependency_entry {
1464 u32 ecclk;
1465 u32 evclk;
1466 u16 v;
1467};
1468
1469struct amdgpu_vce_clock_voltage_dependency_table {
1470 u8 count;
1471 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1472};
1473
1474struct amdgpu_ppm_table {
1475 u8 ppm_design;
1476 u16 cpu_core_number;
1477 u32 platform_tdp;
1478 u32 small_ac_platform_tdp;
1479 u32 platform_tdc;
1480 u32 small_ac_platform_tdc;
1481 u32 apu_tdp;
1482 u32 dgpu_tdp;
1483 u32 dgpu_ulv_power;
1484 u32 tj_max;
1485};
1486
1487struct amdgpu_cac_tdp_table {
1488 u16 tdp;
1489 u16 configurable_tdp;
1490 u16 tdc;
1491 u16 battery_power_limit;
1492 u16 small_power_limit;
1493 u16 low_cac_leakage;
1494 u16 high_cac_leakage;
1495 u16 maximum_power_delivery_limit;
1496};
1497
1498struct amdgpu_dpm_dynamic_state {
1499 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1500 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1501 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1502 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1503 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1504 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1505 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1506 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1507 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1508 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1509 struct amdgpu_clock_array valid_sclk_values;
1510 struct amdgpu_clock_array valid_mclk_values;
1511 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1512 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1513 u32 mclk_sclk_ratio;
1514 u32 sclk_mclk_delta;
1515 u16 vddc_vddci_delta;
1516 u16 min_vddc_for_pcie_gen2;
1517 struct amdgpu_cac_leakage_table cac_leakage_table;
1518 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1519 struct amdgpu_ppm_table *ppm_table;
1520 struct amdgpu_cac_tdp_table *cac_tdp_table;
1521};
1522
1523struct amdgpu_dpm_fan {
1524 u16 t_min;
1525 u16 t_med;
1526 u16 t_high;
1527 u16 pwm_min;
1528 u16 pwm_med;
1529 u16 pwm_high;
1530 u8 t_hyst;
1531 u32 cycle_delay;
1532 u16 t_max;
1533 u8 control_mode;
1534 u16 default_max_fan_pwm;
1535 u16 default_fan_output_sensitivity;
1536 u16 fan_output_sensitivity;
1537 bool ucode_fan_control;
1538};
1539
1540enum amdgpu_pcie_gen {
1541 AMDGPU_PCIE_GEN1 = 0,
1542 AMDGPU_PCIE_GEN2 = 1,
1543 AMDGPU_PCIE_GEN3 = 2,
1544 AMDGPU_PCIE_GEN_INVALID = 0xffff
1545};
1546
1547enum amdgpu_dpm_forced_level {
1548 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1549 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1550 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1551 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1552};
1553
1554struct amdgpu_vce_state {
1555 /* vce clocks */
1556 u32 evclk;
1557 u32 ecclk;
1558 /* gpu clocks */
1559 u32 sclk;
1560 u32 mclk;
1561 u8 clk_idx;
1562 u8 pstate;
1563};
1564
1565struct amdgpu_dpm_funcs {
1566 int (*get_temperature)(struct amdgpu_device *adev);
1567 int (*pre_set_power_state)(struct amdgpu_device *adev);
1568 int (*set_power_state)(struct amdgpu_device *adev);
1569 void (*post_set_power_state)(struct amdgpu_device *adev);
1570 void (*display_configuration_changed)(struct amdgpu_device *adev);
1571 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1572 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1573 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1574 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1575 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1576 bool (*vblank_too_short)(struct amdgpu_device *adev);
1577 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1578 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1579 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1580 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1581 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1582 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1583 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
c85e299f
EH		 1584 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1585 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
8b2e574d
EH		 1586 int (*get_sclk_od)(struct amdgpu_device *adev);
1587 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
f2bdc05f
EH		 1588 int (*get_mclk_od)(struct amdgpu_device *adev);
1589 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
97b2e202
AD		 1590};
1591
1592struct amdgpu_dpm {
1593 struct amdgpu_ps *ps;
1594 /* number of valid power states */
1595 int num_ps;
1596 /* current power state that is active */
1597 struct amdgpu_ps *current_ps;
1598 /* requested power state */
1599 struct amdgpu_ps *requested_ps;
1600 /* boot up power state */
1601 struct amdgpu_ps *boot_ps;
1602 /* default uvd power state */
1603 struct amdgpu_ps *uvd_ps;
1604 /* vce requirements */
1605 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1606 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1607 enum amd_pm_state_type state;
1608 enum amd_pm_state_type user_state;
97b2e202
AD		 1609 u32 platform_caps;
1610 u32 voltage_response_time;
1611 u32 backbias_response_time;
1612 void *priv;
1613 u32 new_active_crtcs;
1614 int new_active_crtc_count;
1615 u32 current_active_crtcs;
1616 int current_active_crtc_count;
1617 struct amdgpu_dpm_dynamic_state dyn_state;
1618 struct amdgpu_dpm_fan fan;
1619 u32 tdp_limit;
1620 u32 near_tdp_limit;
1621 u32 near_tdp_limit_adjusted;
1622 u32 sq_ramping_threshold;
1623 u32 cac_leakage;
1624 u16 tdp_od_limit;
1625 u32 tdp_adjustment;
1626 u16 load_line_slope;
1627 bool power_control;
1628 bool ac_power;
1629 /* special states active */
1630 bool thermal_active;
1631 bool uvd_active;
1632 bool vce_active;
1633 /* thermal handling */
1634 struct amdgpu_dpm_thermal thermal;
1635 /* forced levels */
1636 enum amdgpu_dpm_forced_level forced_level;
1637};
1638
1639struct amdgpu_pm {
1640 struct mutex mutex;
97b2e202
AD		 1641 u32 current_sclk;
1642 u32 current_mclk;
1643 u32 default_sclk;
1644 u32 default_mclk;
1645 struct amdgpu_i2c_chan *i2c_bus;
1646 /* internal thermal controller on rv6xx+ */
1647 enum amdgpu_int_thermal_type int_thermal_type;
1648 struct device *int_hwmon_dev;
1649 /* fan control parameters */
1650 bool no_fan;
1651 u8 fan_pulses_per_revolution;
1652 u8 fan_min_rpm;
1653 u8 fan_max_rpm;
1654 /* dpm */
1655 bool dpm_enabled;
c86f5ebf 1656 bool sysfs_initialized;
97b2e202
AD		 1657 struct amdgpu_dpm dpm;
1658 const struct firmware *fw; /* SMC firmware */
1659 uint32_t fw_version;
1660 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1661 uint32_t pcie_gen_mask;
1662 uint32_t pcie_mlw_mask;
7fb72a1f 1663 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1664};
1665
d0dd7f0c
AD		 1666void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1667
97b2e202
AD		 1668/*
1669 * UVD
1670 */
c0365541
AN		 1671#define AMDGPU_DEFAULT_UVD_HANDLES 10
1672#define AMDGPU_MAX_UVD_HANDLES 40
1673#define AMDGPU_UVD_STACK_SIZE (200*1024)
1674#define AMDGPU_UVD_HEAP_SIZE (256*1024)
1675#define AMDGPU_UVD_SESSION_SIZE (50*1024)
1676#define AMDGPU_UVD_FIRMWARE_OFFSET 256
97b2e202
AD		 1677
1678struct amdgpu_uvd {
1679 struct amdgpu_bo *vcpu_bo;
1680 void *cpu_addr;
1681 uint64_t gpu_addr;
562e2689 1682 unsigned fw_version;
3f99dd81 1683 void *saved_bo;
c0365541 1684 unsigned max_handles;
97b2e202
AD		 1685 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1686 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1687 struct delayed_work idle_work;
1688 const struct firmware *fw; /* UVD firmware */
1689 struct amdgpu_ring ring;
1690 struct amdgpu_irq_src irq;
1691 bool address_64_bit;
ead833ec 1692 struct amd_sched_entity entity;
97b2e202
AD		 1693};
1694
1695/*
1696 * VCE
1697 */
1698#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1699#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1700
6a585777
AD		 1701#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1702#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1703
97b2e202
AD		 1704struct amdgpu_vce {
1705 struct amdgpu_bo *vcpu_bo;
1706 uint64_t gpu_addr;
1707 unsigned fw_version;
1708 unsigned fb_version;
1709 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1710 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1711 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1712 struct delayed_work idle_work;
1713 const struct firmware *fw; /* VCE firmware */
1714 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1715 struct amdgpu_irq_src irq;
6a585777 1716 unsigned harvest_config;
c594989c 1717 struct amd_sched_entity entity;
97b2e202
AD		 1718};
1719
1720/*
1721 * SDMA
1722 */
c113ea1c 1723struct amdgpu_sdma_instance {
97b2e202
AD		 1724 /* SDMA firmware */
1725 const struct firmware *fw;
1726 uint32_t fw_version;
cfa2104f 1727 uint32_t feature_version;
97b2e202
AD		 1728
1729 struct amdgpu_ring ring;
18111de0 1730 bool burst_nop;
97b2e202
AD		 1731};
1732
c113ea1c
AD		 1733struct amdgpu_sdma {
1734 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1735 struct amdgpu_irq_src trap_irq;
1736 struct amdgpu_irq_src illegal_inst_irq;
edf600da 1737 int num_instances;
c113ea1c
AD		 1738};
1739
97b2e202
AD		 1740/*
1741 * Firmware
1742 */
1743struct amdgpu_firmware {
1744 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1745 bool smu_load;
1746 struct amdgpu_bo *fw_buf;
1747 unsigned int fw_size;
1748};
1749
1750/*
1751 * Benchmarking
1752 */
1753void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1754
1755
1756/*
1757 * Testing
1758 */
1759void amdgpu_test_moves(struct amdgpu_device *adev);
1760void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1761 struct amdgpu_ring *cpA,
1762 struct amdgpu_ring *cpB);
1763void amdgpu_test_syncing(struct amdgpu_device *adev);
1764
1765/*
1766 * MMU Notifier
1767 */
1768#if defined(CONFIG_MMU_NOTIFIER)
1769int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1770void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1771#else
1d1106b0 1772static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1773{
1774 return -ENODEV;
1775}
1d1106b0 1776static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1777#endif
1778
1779/*
1780 * Debugfs
1781 */
1782struct amdgpu_debugfs {
06ab6832 1783 const struct drm_info_list *files;
97b2e202
AD		 1784 unsigned num_files;
1785};
1786
1787int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 1788 const struct drm_info_list *files,
97b2e202
AD		 1789 unsigned nfiles);
1790int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1791
1792#if defined(CONFIG_DEBUG_FS)
1793int amdgpu_debugfs_init(struct drm_minor *minor);
1794void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1795#endif
1796
50ab2533
HR		 1797int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1798
97b2e202
AD		 1799/*
1800 * amdgpu smumgr functions
1801 */
1802struct amdgpu_smumgr_funcs {
1803 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1804 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1805 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1806};
1807
1808/*
1809 * amdgpu smumgr
1810 */
1811struct amdgpu_smumgr {
1812 struct amdgpu_bo *toc_buf;
1813 struct amdgpu_bo *smu_buf;
1814 /* asic priv smu data */
1815 void *priv;
1816 spinlock_t smu_lock;
1817 /* smumgr functions */
1818 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1819 /* ucode loading complete flag */
1820 uint32_t fw_flags;
1821};
1822
1823/*
1824 * ASIC specific register table accessible by UMD
1825 */
1826struct amdgpu_allowed_register_entry {
1827 uint32_t reg_offset;
1828 bool untouched;
1829 bool grbm_indexed;
1830};
1831
97b2e202
AD		 1832/*
1833 * ASIC specific functions.
1834 */
1835struct amdgpu_asic_funcs {
1836 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1837 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1838 u8 *bios, u32 length_bytes);
97b2e202
AD		 1839 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1840 u32 sh_num, u32 reg_offset, u32 *value);
1841 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1842 int (*reset)(struct amdgpu_device *adev);
97b2e202
AD		 1843 /* get the reference clock */
1844 u32 (*get_xclk)(struct amdgpu_device *adev);
97b2e202
AD		 1845 /* MM block clocks */
1846 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1847 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
048765ad
AR		 1848 /* query virtual capabilities */
1849 u32 (*get_virtual_caps)(struct amdgpu_device *adev);
97b2e202
AD		 1850};
1851
1852/*
1853 * IOCTL.
1854 */
1855int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859
1860int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *filp);
1866int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1867 struct drm_file *filp);
1868int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1869 struct drm_file *filp);
1870int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1871 struct drm_file *filp);
1872int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1873int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1874
1875int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1876 struct drm_file *filp);
1877
1878/* VRAM scratch page for HDP bug, default vram page */
1879struct amdgpu_vram_scratch {
1880 struct amdgpu_bo *robj;
1881 volatile uint32_t *ptr;
1882 u64 gpu_addr;
1883};
1884
1885/*
1886 * ACPI
1887 */
1888struct amdgpu_atif_notification_cfg {
1889 bool enabled;
1890 int command_code;
1891};
1892
1893struct amdgpu_atif_notifications {
1894 bool display_switch;
1895 bool expansion_mode_change;
1896 bool thermal_state;
1897 bool forced_power_state;
1898 bool system_power_state;
1899 bool display_conf_change;
1900 bool px_gfx_switch;
1901 bool brightness_change;
1902 bool dgpu_display_event;
1903};
1904
1905struct amdgpu_atif_functions {
1906 bool system_params;
1907 bool sbios_requests;
1908 bool select_active_disp;
1909 bool lid_state;
1910 bool get_tv_standard;
1911 bool set_tv_standard;
1912 bool get_panel_expansion_mode;
1913 bool set_panel_expansion_mode;
1914 bool temperature_change;
1915 bool graphics_device_types;
1916};
1917
1918struct amdgpu_atif {
1919 struct amdgpu_atif_notifications notifications;
1920 struct amdgpu_atif_functions functions;
1921 struct amdgpu_atif_notification_cfg notification_cfg;
1922 struct amdgpu_encoder *encoder_for_bl;
1923};
1924
1925struct amdgpu_atcs_functions {
1926 bool get_ext_state;
1927 bool pcie_perf_req;
1928 bool pcie_dev_rdy;
1929 bool pcie_bus_width;
1930};
1931
1932struct amdgpu_atcs {
1933 struct amdgpu_atcs_functions functions;
1934};
1935
d03846af
CZ		 1936/*
1937 * CGS
1938 */
110e6f26
DA		 1939struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1940void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
a8fe58ce
MB		 1941
1942
7e471e6f 1943/* GPU virtualization */
048765ad
AR		 1944#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1945#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
7e471e6f
AD		 1946struct amdgpu_virtualization {
1947 bool supports_sr_iov;
048765ad
AR		 1948 bool is_virtual;
1949 u32 caps;
7e471e6f
AD		 1950};
1951
97b2e202
AD		 1952/*
1953 * Core structure, functions and helpers.
1954 */
1955typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1956typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1957
1958typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1959typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1960
8faf0e08
AD		 1961struct amdgpu_ip_block_status {
1962 bool valid;
1963 bool sw;
1964 bool hw;
1965};
1966
97b2e202
AD		 1967struct amdgpu_device {
1968 struct device *dev;
1969 struct drm_device *ddev;
1970 struct pci_dev *pdev;
97b2e202 1971
a8fe58ce
MB		 1972#ifdef CONFIG_DRM_AMD_ACP
1973 struct amdgpu_acp acp;
1974#endif
1975
97b2e202 1976 /* ASIC */
2f7d10b3 1977 enum amd_asic_type asic_type;
97b2e202
AD		 1978 uint32_t family;
1979 uint32_t rev_id;
1980 uint32_t external_rev_id;
1981 unsigned long flags;
1982 int usec_timeout;
1983 const struct amdgpu_asic_funcs *asic_funcs;
1984 bool shutdown;
97b2e202
AD		 1985 bool need_dma32;
1986 bool accel_working;
edf600da 1987 struct work_struct reset_work;
97b2e202
AD		 1988 struct notifier_block acpi_nb;
1989 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1990 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
edf600da 1991 unsigned debugfs_count;
97b2e202 1992#if defined(CONFIG_DEBUG_FS)
adcec288 1993 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
97b2e202
AD		 1994#endif
1995 struct amdgpu_atif atif;
1996 struct amdgpu_atcs atcs;
1997 struct mutex srbm_mutex;
1998 /* GRBM index mutex. Protects concurrent access to GRBM index */
1999 struct mutex grbm_idx_mutex;
2000 struct dev_pm_domain vga_pm_domain;
2001 bool have_disp_power_ref;
2002
2003 /* BIOS */
2004 uint8_t *bios;
2005 bool is_atom_bios;
97b2e202
AD		 2006 struct amdgpu_bo *stollen_vga_memory;
2007 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
2008
2009 /* Register/doorbell mmio */
2010 resource_size_t rmmio_base;
2011 resource_size_t rmmio_size;
2012 void __iomem *rmmio;
2013 /* protects concurrent MM_INDEX/DATA based register access */
2014 spinlock_t mmio_idx_lock;
2015 /* protects concurrent SMC based register access */
2016 spinlock_t smc_idx_lock;
2017 amdgpu_rreg_t smc_rreg;
2018 amdgpu_wreg_t smc_wreg;
2019 /* protects concurrent PCIE register access */
2020 spinlock_t pcie_idx_lock;
2021 amdgpu_rreg_t pcie_rreg;
2022 amdgpu_wreg_t pcie_wreg;
2023 /* protects concurrent UVD register access */
2024 spinlock_t uvd_ctx_idx_lock;
2025 amdgpu_rreg_t uvd_ctx_rreg;
2026 amdgpu_wreg_t uvd_ctx_wreg;
2027 /* protects concurrent DIDT register access */
2028 spinlock_t didt_idx_lock;
2029 amdgpu_rreg_t didt_rreg;
2030 amdgpu_wreg_t didt_wreg;
2031 /* protects concurrent ENDPOINT (audio) register access */
2032 spinlock_t audio_endpt_idx_lock;
2033 amdgpu_block_rreg_t audio_endpt_rreg;
2034 amdgpu_block_wreg_t audio_endpt_wreg;
2035 void __iomem *rio_mem;
2036 resource_size_t rio_mem_size;
2037 struct amdgpu_doorbell doorbell;
2038
2039 /* clock/pll info */
2040 struct amdgpu_clock clock;
2041
2042 /* MC */
2043 struct amdgpu_mc mc;
2044 struct amdgpu_gart gart;
2045 struct amdgpu_dummy_page dummy_page;
2046 struct amdgpu_vm_manager vm_manager;
2047
2048 /* memory management */
2049 struct amdgpu_mman mman;
97b2e202
AD		 2050 struct amdgpu_vram_scratch vram_scratch;
2051 struct amdgpu_wb wb;
2052 atomic64_t vram_usage;
2053 atomic64_t vram_vis_usage;
2054 atomic64_t gtt_usage;
2055 atomic64_t num_bytes_moved;
dbd5ed60 2056 atomic64_t num_evictions;
d94aed5a 2057 atomic_t gpu_reset_counter;
97b2e202
AD		 2058
2059 /* display */
2060 struct amdgpu_mode_info mode_info;
2061 struct work_struct hotplug_work;
2062 struct amdgpu_irq_src crtc_irq;
2063 struct amdgpu_irq_src pageflip_irq;
2064 struct amdgpu_irq_src hpd_irq;
2065
2066 /* rings */
76bf0db5 2067 u64 fence_context;
97b2e202
AD		 2068 unsigned num_rings;
2069 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2070 bool ib_pool_ready;
2071 struct amdgpu_sa_manager ring_tmp_bo;
2072
2073 /* interrupts */
2074 struct amdgpu_irq irq;
2075
1f7371b2
AD		 2076 /* powerplay */
2077 struct amd_powerplay powerplay;
e61710c5 2078 bool pp_enabled;
f3898ea1 2079 bool pp_force_state_enabled;
1f7371b2 2080
97b2e202
AD		 2081 /* dpm */
2082 struct amdgpu_pm pm;
2083 u32 cg_flags;
2084 u32 pg_flags;
2085
2086 /* amdgpu smumgr */
2087 struct amdgpu_smumgr smu;
2088
2089 /* gfx */
2090 struct amdgpu_gfx gfx;
2091
2092 /* sdma */
c113ea1c 2093 struct amdgpu_sdma sdma;
97b2e202
AD		 2094
2095 /* uvd */
97b2e202
AD		 2096 struct amdgpu_uvd uvd;
2097
2098 /* vce */
2099 struct amdgpu_vce vce;
2100
2101 /* firmwares */
2102 struct amdgpu_firmware firmware;
2103
2104 /* GDS */
2105 struct amdgpu_gds gds;
2106
2107 const struct amdgpu_ip_block_version *ip_blocks;
2108 int num_ip_blocks;
8faf0e08 2109 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2110 struct mutex mn_lock;
2111 DECLARE_HASHTABLE(mn_hash, 7);
2112
2113 /* tracking pinned memory */
2114 u64 vram_pin_size;
e131b914 2115 u64 invisible_pin_size;
97b2e202 2116 u64 gart_pin_size;
130e0371
OG		 2117
2118 /* amdkfd interface */
2119 struct kfd_dev *kfd;
23ca0e4e 2120
7e471e6f 2121 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2122};
2123
2124bool amdgpu_device_is_px(struct drm_device *dev);
2125int amdgpu_device_init(struct amdgpu_device *adev,
2126 struct drm_device *ddev,
2127 struct pci_dev *pdev,
2128 uint32_t flags);
2129void amdgpu_device_fini(struct amdgpu_device *adev);
2130int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2131
2132uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2133 bool always_indirect);
2134void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2135 bool always_indirect);
2136u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2137void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2138
2139u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2140void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2141
97b2e202
AD		 2142/*
2143 * Registers read & write functions.
2144 */
2145#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2146#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2147#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2148#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2149#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2150#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2151#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2152#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2153#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2154#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2155#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2156#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2157#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2158#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2159#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2160#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2161#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2162#define WREG32_P(reg, val, mask) \
2163 do { \
2164 uint32_t tmp_ = RREG32(reg); \
2165 tmp_ &= (mask); \
2166 tmp_ |= ((val) & ~(mask)); \
2167 WREG32(reg, tmp_); \
2168 } while (0)
2169#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2170#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2171#define WREG32_PLL_P(reg, val, mask) \
2172 do { \
2173 uint32_t tmp_ = RREG32_PLL(reg); \
2174 tmp_ &= (mask); \
2175 tmp_ |= ((val) & ~(mask)); \
2176 WREG32_PLL(reg, tmp_); \
2177 } while (0)
2178#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2179#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2180#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2181
2182#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2183#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2184
2185#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2186#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2187
2188#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2189 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2190 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2191
2192#define REG_GET_FIELD(value, reg, field) \
2193 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2194
2195/*
2196 * BIOS helpers.
2197 */
2198#define RBIOS8(i) (adev->bios[i])
2199#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2200#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2201
2202/*
2203 * RING helpers.
2204 */
2205static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2206{
2207 if (ring->count_dw <= 0)
86c2b790 2208 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2209 ring->ring[ring->wptr++] = v;
2210 ring->wptr &= ring->ptr_mask;
2211 ring->count_dw--;
97b2e202
AD		 2212}
2213
c113ea1c
AD		 2214static inline struct amdgpu_sdma_instance *
2215amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2216{
2217 struct amdgpu_device *adev = ring->adev;
2218 int i;
2219
c113ea1c
AD		 2220 for (i = 0; i < adev->sdma.num_instances; i++)
2221 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2222 break;
2223
2224 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2225 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2226 else
2227 return NULL;
2228}
2229
97b2e202
AD		 2230/*
2231 * ASICs macro.
2232 */
2233#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2234#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
97b2e202
AD		 2235#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2236#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2237#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
048765ad 2238#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
97b2e202 2239#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2240#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202 2241#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
97b2e202
AD		 2242#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2243#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2244#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2245#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2246#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2247#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2248#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2249#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2250#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2251#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2252#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
d88bf583 2253#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
b8c7b39e 2254#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
97b2e202 2255#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2256#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2257#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2258#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
11afbde8 2259#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
9e5d5309 2260#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
03ccf481
ML		 2261#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2262#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
97b2e202
AD		 2263#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2264#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2265#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2266#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2267#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2268#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2269#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2270#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2271#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2272#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2273#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2274#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2275#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
cb9e59d7 2276#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
97b2e202
AD		 2277#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2278#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2279#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2280#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2281#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2282#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2283#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2284#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2285#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2286#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2287#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2288#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2289#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2290#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
b95e31fd 2291#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
05fb7291 2292#define amdgpu_gfx_select_se_sh(adev, se, sh) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh))
3af76f23
RZ		 2293
2294#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2295 ((adev)->pp_enabled ? \
e61710c5 2296 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2297 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2298
2299#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2300 ((adev)->pp_enabled ? \
e61710c5 2301 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2302 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2303
2304#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2305 ((adev)->pp_enabled ? \
e61710c5 2306 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2307 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2308
2309#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2310 ((adev)->pp_enabled ? \
e61710c5 2311 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2312 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2313
2314#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2315 ((adev)->pp_enabled ? \
e61710c5 2316 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2317 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2318
1b5708ff 2319#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2320 ((adev)->pp_enabled ? \
e61710c5 2321 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2322 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2323
2324#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2325 ((adev)->pp_enabled ? \
e61710c5 2326 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2327 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2328
2329
2330#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2331 ((adev)->pp_enabled ? \
e61710c5 2332 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2333 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2334
2335#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2336 ((adev)->pp_enabled ? \
e61710c5 2337 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2338 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2339
2340#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2341 ((adev)->pp_enabled ? \
e61710c5 2342 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2343 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2344
2345#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2346 ((adev)->pp_enabled ? \
e61710c5 2347 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2348 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2349
2350#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2351 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2352
2353#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2354 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2355
f3898ea1
EH		 2356#define amdgpu_dpm_get_pp_num_states(adev, data) \
2357 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2358
2359#define amdgpu_dpm_get_pp_table(adev, table) \
2360 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2361
2362#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2363 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2364
2365#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2366 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2367
2368#define amdgpu_dpm_force_clock_level(adev, type, level) \
2369 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2370
428bafa8
EH		 2371#define amdgpu_dpm_get_sclk_od(adev) \
2372 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2373
2374#define amdgpu_dpm_set_sclk_od(adev, value) \
2375 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2376
f2bdc05f
EH		 2377#define amdgpu_dpm_get_mclk_od(adev) \
2378 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2379
2380#define amdgpu_dpm_set_mclk_od(adev, value) \
2381 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2382
e61710c5 2383#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2384 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2385
2386#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2387
2388/* Common functions */
2389int amdgpu_gpu_reset(struct amdgpu_device *adev);
2390void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2391bool amdgpu_card_posted(struct amdgpu_device *adev);
2392void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2393
97b2e202
AD		 2394int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2395int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2396 u32 ip_instance, u32 ring,
2397 struct amdgpu_ring **out_ring);
2398void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2399bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2f568dbd 2400int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
97b2e202
AD		 2401int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2402 uint32_t flags);
2403bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
cc325d19 2404struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2405bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2406 unsigned long end);
2f568dbd
CK		 2407bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2408 int *last_invalidated);
97b2e202
AD		 2409bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2410uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2411 struct ttm_mem_reg *mem);
2412void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2413void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2414void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2415void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2416 const u32 *registers,
2417 const u32 array_size);
2418
2419bool amdgpu_device_is_px(struct drm_device *dev);
2420/* atpx handler */
2421#if defined(CONFIG_VGA_SWITCHEROO)
2422void amdgpu_register_atpx_handler(void);
2423void amdgpu_unregister_atpx_handler(void);
a78fe133 2424bool amdgpu_has_atpx_dgpu_power_cntl(void);
2f5af82e 2425bool amdgpu_is_atpx_hybrid(void);
97b2e202
AD		 2426#else
2427static inline void amdgpu_register_atpx_handler(void) {}
2428static inline void amdgpu_unregister_atpx_handler(void) {}
a78fe133 2429static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2f5af82e 2430static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
97b2e202
AD		 2431#endif
2432
2433/*
2434 * KMS
2435 */
2436extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
f498d9ed 2437extern const int amdgpu_max_kms_ioctl;
97b2e202
AD		 2438
2439int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2440int amdgpu_driver_unload_kms(struct drm_device *dev);
2441void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2442int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2443void amdgpu_driver_postclose_kms(struct drm_device *dev,
2444 struct drm_file *file_priv);
2445void amdgpu_driver_preclose_kms(struct drm_device *dev,
2446 struct drm_file *file_priv);
2447int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2448int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2449u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2450int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2451void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2452int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2453 int *max_error,
2454 struct timeval *vblank_time,
2455 unsigned flags);
2456long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2457 unsigned long arg);
2458
97b2e202
AD		 2459/*
2460 * functions used by amdgpu_encoder.c
2461 */
2462struct amdgpu_afmt_acr {
2463 u32 clock;
2464
2465 int n_32khz;
2466 int cts_32khz;
2467
2468 int n_44_1khz;
2469 int cts_44_1khz;
2470
2471 int n_48khz;
2472 int cts_48khz;
2473
2474};
2475
2476struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2477
2478/* amdgpu_acpi.c */
2479#if defined(CONFIG_ACPI)
2480int amdgpu_acpi_init(struct amdgpu_device *adev);
2481void amdgpu_acpi_fini(struct amdgpu_device *adev);
2482bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2483int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2484 u8 perf_req, bool advertise);
2485int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2486#else
2487static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2488static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2489#endif
2490
2491struct amdgpu_bo_va_mapping *
2492amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2493 uint64_t addr, struct amdgpu_bo **bo);
2494
2495#include "amdgpu_object.h"
97b2e202 2496#endif
Linux kernel - Deliverables
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