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drma/dmgpu: move cg and pg flags into shared headers
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
97b2e202 56
b80d8475
AD		 57#include "gpu_scheduler.h"
58
97b2e202
AD		 59/*
60 * Modules parameters.
61 */
62extern int amdgpu_modeset;
63extern int amdgpu_vram_limit;
64extern int amdgpu_gart_size;
65extern int amdgpu_benchmarking;
66extern int amdgpu_testing;
67extern int amdgpu_audio;
68extern int amdgpu_disp_priority;
69extern int amdgpu_hw_i2c;
70extern int amdgpu_pcie_gen2;
71extern int amdgpu_msi;
72extern int amdgpu_lockup_timeout;
73extern int amdgpu_dpm;
74extern int amdgpu_smc_load_fw;
75extern int amdgpu_aspm;
76extern int amdgpu_runtime_pm;
77extern int amdgpu_hard_reset;
78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
b80d8475 85extern int amdgpu_enable_scheduler;
1333f723 86extern int amdgpu_sched_jobs;
4afcb303 87extern int amdgpu_sched_hw_submission;
3daea9e3 88extern int amdgpu_enable_semaphores;
1f7371b2 89extern int amdgpu_powerplay;
cd474ba0
AD		 90extern unsigned amdgpu_pcie_gen_cap;
91extern unsigned amdgpu_pcie_lane_cap;
97b2e202 92
4b559c90 93#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 94#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
95#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
96/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
97#define AMDGPU_IB_POOL_SIZE 16
98#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
99#define AMDGPUFB_CONN_LIMIT 4
100#define AMDGPU_BIOS_NUM_SCRATCH 8
101
97b2e202
AD		 102/* max number of rings */
103#define AMDGPU_MAX_RINGS 16
104#define AMDGPU_MAX_GFX_RINGS 1
105#define AMDGPU_MAX_COMPUTE_RINGS 8
106#define AMDGPU_MAX_VCE_RINGS 2
107
36f523a7
JZ		 108/* max number of IP instances */
109#define AMDGPU_MAX_SDMA_INSTANCES 2
110
97b2e202
AD		 111/* number of hw syncs before falling back on blocking */
112#define AMDGPU_NUM_SYNCS 4
113
114/* hardcode that limit for now */
115#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
116
117/* hard reset data */
118#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
119
120/* reset flags */
121#define AMDGPU_RESET_GFX (1 << 0)
122#define AMDGPU_RESET_COMPUTE (1 << 1)
123#define AMDGPU_RESET_DMA (1 << 2)
124#define AMDGPU_RESET_CP (1 << 3)
125#define AMDGPU_RESET_GRBM (1 << 4)
126#define AMDGPU_RESET_DMA1 (1 << 5)
127#define AMDGPU_RESET_RLC (1 << 6)
128#define AMDGPU_RESET_SEM (1 << 7)
129#define AMDGPU_RESET_IH (1 << 8)
130#define AMDGPU_RESET_VMC (1 << 9)
131#define AMDGPU_RESET_MC (1 << 10)
132#define AMDGPU_RESET_DISPLAY (1 << 11)
133#define AMDGPU_RESET_UVD (1 << 12)
134#define AMDGPU_RESET_VCE (1 << 13)
135#define AMDGPU_RESET_VCE1 (1 << 14)
136
97b2e202
AD		 137/* GFX current status */
138#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
139#define AMDGPU_GFX_SAFE_MODE 0x00000001L
140#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
141#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
142#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
143
144/* max cursor sizes (in pixels) */
145#define CIK_CURSOR_WIDTH 128
146#define CIK_CURSOR_HEIGHT 128
147
148struct amdgpu_device;
149struct amdgpu_fence;
150struct amdgpu_ib;
151struct amdgpu_vm;
152struct amdgpu_ring;
153struct amdgpu_semaphore;
154struct amdgpu_cs_parser;
bb977d37 155struct amdgpu_job;
97b2e202 156struct amdgpu_irq_src;
0b492a4c 157struct amdgpu_fpriv;
97b2e202
AD		 158
159enum amdgpu_cp_irq {
160 AMDGPU_CP_IRQ_GFX_EOP = 0,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
169
170 AMDGPU_CP_IRQ_LAST
171};
172
173enum amdgpu_sdma_irq {
174 AMDGPU_SDMA_IRQ_TRAP0 = 0,
175 AMDGPU_SDMA_IRQ_TRAP1,
176
177 AMDGPU_SDMA_IRQ_LAST
178};
179
180enum amdgpu_thermal_irq {
181 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
182 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
183
184 AMDGPU_THERMAL_IRQ_LAST
185};
186
97b2e202 187int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 188 enum amd_ip_block_type block_type,
189 enum amd_clockgating_state state);
97b2e202 190int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 191 enum amd_ip_block_type block_type,
192 enum amd_powergating_state state);
97b2e202
AD		 193
194struct amdgpu_ip_block_version {
5fc3aeeb 195 enum amd_ip_block_type type;
97b2e202
AD		 196 u32 major;
197 u32 minor;
198 u32 rev;
5fc3aeeb 199 const struct amd_ip_funcs *funcs;
97b2e202
AD		 200};
201
202int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 203 enum amd_ip_block_type type,
97b2e202
AD		 204 u32 major, u32 minor);
205
206const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
207 struct amdgpu_device *adev,
5fc3aeeb 208 enum amd_ip_block_type type);
97b2e202
AD		 209
210/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
211struct amdgpu_buffer_funcs {
212 /* maximum bytes in a single operation */
213 uint32_t copy_max_bytes;
214
215 /* number of dw to reserve per operation */
216 unsigned copy_num_dw;
217
218 /* used for buffer migration */
c7ae72c0 219 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 220 /* src addr in bytes */
221 uint64_t src_offset,
222 /* dst addr in bytes */
223 uint64_t dst_offset,
224 /* number of byte to transfer */
225 uint32_t byte_count);
226
227 /* maximum bytes in a single operation */
228 uint32_t fill_max_bytes;
229
230 /* number of dw to reserve per operation */
231 unsigned fill_num_dw;
232
233 /* used for buffer clearing */
6e7a3840 234 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 235 /* value to write to memory */
236 uint32_t src_data,
237 /* dst addr in bytes */
238 uint64_t dst_offset,
239 /* number of byte to fill */
240 uint32_t byte_count);
241};
242
243/* provided by hw blocks that can write ptes, e.g., sdma */
244struct amdgpu_vm_pte_funcs {
245 /* copy pte entries from GART */
246 void (*copy_pte)(struct amdgpu_ib *ib,
247 uint64_t pe, uint64_t src,
248 unsigned count);
249 /* write pte one entry at a time with addr mapping */
250 void (*write_pte)(struct amdgpu_ib *ib,
251 uint64_t pe,
252 uint64_t addr, unsigned count,
253 uint32_t incr, uint32_t flags);
254 /* for linear pte/pde updates without addr mapping */
255 void (*set_pte_pde)(struct amdgpu_ib *ib,
256 uint64_t pe,
257 uint64_t addr, unsigned count,
258 uint32_t incr, uint32_t flags);
259 /* pad the indirect buffer to the necessary number of dw */
260 void (*pad_ib)(struct amdgpu_ib *ib);
261};
262
263/* provided by the gmc block */
264struct amdgpu_gart_funcs {
265 /* flush the vm tlb via mmio */
266 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
267 uint32_t vmid);
268 /* write pte/pde updates using the cpu */
269 int (*set_pte_pde)(struct amdgpu_device *adev,
270 void *cpu_pt_addr, /* cpu addr of page table */
271 uint32_t gpu_page_idx, /* pte/pde to update */
272 uint64_t addr, /* addr to write into pte/pde */
273 uint32_t flags); /* access flags */
274};
275
276/* provided by the ih block */
277struct amdgpu_ih_funcs {
278 /* ring read/write ptr handling, called from interrupt context */
279 u32 (*get_wptr)(struct amdgpu_device *adev);
280 void (*decode_iv)(struct amdgpu_device *adev,
281 struct amdgpu_iv_entry *entry);
282 void (*set_rptr)(struct amdgpu_device *adev);
283};
284
285/* provided by hw blocks that expose a ring buffer for commands */
286struct amdgpu_ring_funcs {
287 /* ring read/write ptr handling */
288 u32 (*get_rptr)(struct amdgpu_ring *ring);
289 u32 (*get_wptr)(struct amdgpu_ring *ring);
290 void (*set_wptr)(struct amdgpu_ring *ring);
291 /* validating and patching of IBs */
292 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
293 /* command emit functions */
294 void (*emit_ib)(struct amdgpu_ring *ring,
295 struct amdgpu_ib *ib);
296 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 297 uint64_t seq, unsigned flags);
97b2e202
AD		 298 bool (*emit_semaphore)(struct amdgpu_ring *ring,
299 struct amdgpu_semaphore *semaphore,
300 bool emit_wait);
301 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
302 uint64_t pd_addr);
d2edb07b 303 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 304 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
305 uint32_t gds_base, uint32_t gds_size,
306 uint32_t gws_base, uint32_t gws_size,
307 uint32_t oa_base, uint32_t oa_size);
308 /* testing functions */
309 int (*test_ring)(struct amdgpu_ring *ring);
310 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 311 /* insert NOP packets */
312 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 313};
314
315/*
316 * BIOS.
317 */
318bool amdgpu_get_bios(struct amdgpu_device *adev);
319bool amdgpu_read_bios(struct amdgpu_device *adev);
320
321/*
322 * Dummy page
323 */
324struct amdgpu_dummy_page {
325 struct page *page;
326 dma_addr_t addr;
327};
328int amdgpu_dummy_page_init(struct amdgpu_device *adev);
329void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
330
331
332/*
333 * Clocks
334 */
335
336#define AMDGPU_MAX_PPLL 3
337
338struct amdgpu_clock {
339 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
340 struct amdgpu_pll spll;
341 struct amdgpu_pll mpll;
342 /* 10 Khz units */
343 uint32_t default_mclk;
344 uint32_t default_sclk;
345 uint32_t default_dispclk;
346 uint32_t current_dispclk;
347 uint32_t dp_extclk;
348 uint32_t max_pixel_clock;
349};
350
351/*
352 * Fences.
353 */
354struct amdgpu_fence_driver {
97b2e202
AD		 355 uint64_t gpu_addr;
356 volatile uint32_t *cpu_addr;
357 /* sync_seq is protected by ring emission lock */
358 uint64_t sync_seq[AMDGPU_MAX_RINGS];
359 atomic64_t last_seq;
360 bool initialized;
97b2e202
AD		 361 struct amdgpu_irq_src *irq_src;
362 unsigned irq_type;
c2776afe 363 struct timer_list fallback_timer;
7f06c236 364 wait_queue_head_t fence_queue;
97b2e202
AD		 365};
366
367/* some special values for the owner field */
368#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
369#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 370
890ee23f
CZ		 371#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
372#define AMDGPU_FENCE_FLAG_INT (1 << 1)
373
97b2e202
AD		 374struct amdgpu_fence {
375 struct fence base;
4cef9267 376
97b2e202
AD		 377 /* RB, DMA, etc. */
378 struct amdgpu_ring *ring;
379 uint64_t seq;
380
381 /* filp or special value for fence creator */
382 void *owner;
383
384 wait_queue_t fence_wake;
385};
386
387struct amdgpu_user_fence {
388 /* write-back bo */
389 struct amdgpu_bo *bo;
390 /* write-back address offset to bo start */
391 uint32_t offset;
392};
393
394int amdgpu_fence_driver_init(struct amdgpu_device *adev);
395void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
396void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
397
4f839a24 398int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 399int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
400 struct amdgpu_irq_src *irq_src,
401 unsigned irq_type);
5ceb54c6
AD		 402void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
403void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 404int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
405 struct amdgpu_fence **fence);
406void amdgpu_fence_process(struct amdgpu_ring *ring);
407int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
408int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
409unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
410
97b2e202
AD		 411bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
412 struct amdgpu_ring *ring);
413void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
414 struct amdgpu_ring *ring);
415
97b2e202
AD		 416/*
417 * TTM.
418 */
419struct amdgpu_mman {
420 struct ttm_bo_global_ref bo_global_ref;
421 struct drm_global_reference mem_global_ref;
422 struct ttm_bo_device bdev;
423 bool mem_global_referenced;
424 bool initialized;
425
426#if defined(CONFIG_DEBUG_FS)
427 struct dentry *vram;
428 struct dentry *gtt;
429#endif
430
431 /* buffer handling */
432 const struct amdgpu_buffer_funcs *buffer_funcs;
433 struct amdgpu_ring *buffer_funcs_ring;
434};
435
436int amdgpu_copy_buffer(struct amdgpu_ring *ring,
437 uint64_t src_offset,
438 uint64_t dst_offset,
439 uint32_t byte_count,
440 struct reservation_object *resv,
c7ae72c0 441 struct fence **fence);
97b2e202
AD		 442int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
443
444struct amdgpu_bo_list_entry {
445 struct amdgpu_bo *robj;
446 struct ttm_validate_buffer tv;
447 struct amdgpu_bo_va *bo_va;
448 unsigned prefered_domains;
449 unsigned allowed_domains;
450 uint32_t priority;
451};
452
453struct amdgpu_bo_va_mapping {
454 struct list_head list;
455 struct interval_tree_node it;
456 uint64_t offset;
457 uint32_t flags;
458};
459
460/* bo virtual addresses in a specific vm */
461struct amdgpu_bo_va {
69b576a1 462 struct mutex mutex;
97b2e202
AD		 463 /* protected by bo being reserved */
464 struct list_head bo_list;
bb1e38a4 465 struct fence *last_pt_update;
97b2e202
AD		 466 unsigned ref_count;
467
7fc11959 468 /* protected by vm mutex and spinlock */
97b2e202
AD		 469 struct list_head vm_status;
470
7fc11959
CK		 471 /* mappings for this bo_va */
472 struct list_head invalids;
473 struct list_head valids;
474
97b2e202
AD		 475 /* constant after initialization */
476 struct amdgpu_vm *vm;
477 struct amdgpu_bo *bo;
478};
479
7e5a547f
CZ		 480#define AMDGPU_GEM_DOMAIN_MAX 0x3
481
97b2e202
AD		 482struct amdgpu_bo {
483 /* Protected by gem.mutex */
484 struct list_head list;
485 /* Protected by tbo.reserved */
486 u32 initial_domain;
7e5a547f 487 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 488 struct ttm_placement placement;
489 struct ttm_buffer_object tbo;
490 struct ttm_bo_kmap_obj kmap;
491 u64 flags;
492 unsigned pin_count;
493 void *kptr;
494 u64 tiling_flags;
495 u64 metadata_flags;
496 void *metadata;
497 u32 metadata_size;
498 /* list of all virtual address to which this bo
499 * is associated to
500 */
501 struct list_head va;
502 /* Constant after initialization */
503 struct amdgpu_device *adev;
504 struct drm_gem_object gem_base;
82b9c55b 505 struct amdgpu_bo *parent;
97b2e202
AD		 506
507 struct ttm_bo_kmap_obj dma_buf_vmap;
508 pid_t pid;
509 struct amdgpu_mn *mn;
510 struct list_head mn_list;
511};
512#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
513
514void amdgpu_gem_object_free(struct drm_gem_object *obj);
515int amdgpu_gem_object_open(struct drm_gem_object *obj,
516 struct drm_file *file_priv);
517void amdgpu_gem_object_close(struct drm_gem_object *obj,
518 struct drm_file *file_priv);
519unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
520struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
521struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
522 struct dma_buf_attachment *attach,
523 struct sg_table *sg);
524struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
525 struct drm_gem_object *gobj,
526 int flags);
527int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
528void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
529struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
530void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
531void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
532int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
533
534/* sub-allocation manager, it has to be protected by another lock.
535 * By conception this is an helper for other part of the driver
536 * like the indirect buffer or semaphore, which both have their
537 * locking.
538 *
539 * Principe is simple, we keep a list of sub allocation in offset
540 * order (first entry has offset == 0, last entry has the highest
541 * offset).
542 *
543 * When allocating new object we first check if there is room at
544 * the end total_size - (last_object_offset + last_object_size) >=
545 * alloc_size. If so we allocate new object there.
546 *
547 * When there is not enough room at the end, we start waiting for
548 * each sub object until we reach object_offset+object_size >=
549 * alloc_size, this object then become the sub object we return.
550 *
551 * Alignment can't be bigger than page size.
552 *
553 * Hole are not considered for allocation to keep things simple.
554 * Assumption is that there won't be hole (all object on same
555 * alignment).
556 */
557struct amdgpu_sa_manager {
558 wait_queue_head_t wq;
559 struct amdgpu_bo *bo;
560 struct list_head *hole;
561 struct list_head flist[AMDGPU_MAX_RINGS];
562 struct list_head olist;
563 unsigned size;
564 uint64_t gpu_addr;
565 void *cpu_ptr;
566 uint32_t domain;
567 uint32_t align;
568};
569
570struct amdgpu_sa_bo;
571
572/* sub-allocation buffer */
573struct amdgpu_sa_bo {
574 struct list_head olist;
575 struct list_head flist;
576 struct amdgpu_sa_manager *manager;
577 unsigned soffset;
578 unsigned eoffset;
4ce9891e 579 struct fence *fence;
97b2e202
AD		 580};
581
582/*
583 * GEM objects.
584 */
585struct amdgpu_gem {
586 struct mutex mutex;
587 struct list_head objects;
588};
589
590int amdgpu_gem_init(struct amdgpu_device *adev);
591void amdgpu_gem_fini(struct amdgpu_device *adev);
592int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
593 int alignment, u32 initial_domain,
594 u64 flags, bool kernel,
595 struct drm_gem_object **obj);
596
597int amdgpu_mode_dumb_create(struct drm_file *file_priv,
598 struct drm_device *dev,
599 struct drm_mode_create_dumb *args);
600int amdgpu_mode_dumb_mmap(struct drm_file *filp,
601 struct drm_device *dev,
602 uint32_t handle, uint64_t *offset_p);
603
604/*
605 * Semaphores.
606 */
607struct amdgpu_semaphore {
608 struct amdgpu_sa_bo *sa_bo;
609 signed waiters;
610 uint64_t gpu_addr;
611};
612
613int amdgpu_semaphore_create(struct amdgpu_device *adev,
614 struct amdgpu_semaphore **semaphore);
615bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
616 struct amdgpu_semaphore *semaphore);
617bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
618 struct amdgpu_semaphore *semaphore);
619void amdgpu_semaphore_free(struct amdgpu_device *adev,
620 struct amdgpu_semaphore **semaphore,
4ce9891e 621 struct fence *fence);
97b2e202
AD		 622
623/*
624 * Synchronization
625 */
626struct amdgpu_sync {
627 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
16545c32 628 struct fence *sync_to[AMDGPU_MAX_RINGS];
f91b3a69 629 DECLARE_HASHTABLE(fences, 4);
3c62338c 630 struct fence *last_vm_update;
97b2e202
AD		 631};
632
633void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 634int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
635 struct fence *f);
97b2e202
AD		 636int amdgpu_sync_resv(struct amdgpu_device *adev,
637 struct amdgpu_sync *sync,
638 struct reservation_object *resv,
639 void *owner);
640int amdgpu_sync_rings(struct amdgpu_sync *sync,
641 struct amdgpu_ring *ring);
e61235db 642struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 643int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 644void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 645 struct fence *fence);
97b2e202
AD		 646
647/*
648 * GART structures, functions & helpers
649 */
650struct amdgpu_mc;
651
652#define AMDGPU_GPU_PAGE_SIZE 4096
653#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
654#define AMDGPU_GPU_PAGE_SHIFT 12
655#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
656
657struct amdgpu_gart {
658 dma_addr_t table_addr;
659 struct amdgpu_bo *robj;
660 void *ptr;
661 unsigned num_gpu_pages;
662 unsigned num_cpu_pages;
663 unsigned table_size;
664 struct page **pages;
665 dma_addr_t *pages_addr;
666 bool ready;
667 const struct amdgpu_gart_funcs *gart_funcs;
668};
669
670int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
671void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
672int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
673void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
674int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
675void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
676int amdgpu_gart_init(struct amdgpu_device *adev);
677void amdgpu_gart_fini(struct amdgpu_device *adev);
678void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
679 int pages);
680int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
681 int pages, struct page **pagelist,
682 dma_addr_t *dma_addr, uint32_t flags);
683
684/*
685 * GPU MC structures, functions & helpers
686 */
687struct amdgpu_mc {
688 resource_size_t aper_size;
689 resource_size_t aper_base;
690 resource_size_t agp_base;
691 /* for some chips with <= 32MB we need to lie
692 * about vram size near mc fb location */
693 u64 mc_vram_size;
694 u64 visible_vram_size;
695 u64 gtt_size;
696 u64 gtt_start;
697 u64 gtt_end;
698 u64 vram_start;
699 u64 vram_end;
700 unsigned vram_width;
701 u64 real_vram_size;
702 int vram_mtrr;
703 u64 gtt_base_align;
704 u64 mc_mask;
705 const struct firmware *fw; /* MC firmware */
706 uint32_t fw_version;
707 struct amdgpu_irq_src vm_fault;
81c59f54 708 uint32_t vram_type;
97b2e202
AD		 709};
710
711/*
712 * GPU doorbell structures, functions & helpers
713 */
714typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
715{
716 AMDGPU_DOORBELL_KIQ = 0x000,
717 AMDGPU_DOORBELL_HIQ = 0x001,
718 AMDGPU_DOORBELL_DIQ = 0x002,
719 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
720 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
721 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
722 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
723 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
724 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
725 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
726 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
727 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
728 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
729 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
730 AMDGPU_DOORBELL_IH = 0x1E8,
731 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
732 AMDGPU_DOORBELL_INVALID = 0xFFFF
733} AMDGPU_DOORBELL_ASSIGNMENT;
734
735struct amdgpu_doorbell {
736 /* doorbell mmio */
737 resource_size_t base;
738 resource_size_t size;
739 u32 __iomem *ptr;
740 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
741};
742
743void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
744 phys_addr_t *aperture_base,
745 size_t *aperture_size,
746 size_t *start_offset);
747
748/*
749 * IRQS.
750 */
751
752struct amdgpu_flip_work {
753 struct work_struct flip_work;
754 struct work_struct unpin_work;
755 struct amdgpu_device *adev;
756 int crtc_id;
757 uint64_t base;
758 struct drm_pending_vblank_event *event;
759 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 760 struct fence *excl;
761 unsigned shared_count;
762 struct fence **shared;
97b2e202
AD		 763};
764
765
766/*
767 * CP & rings.
768 */
769
770struct amdgpu_ib {
771 struct amdgpu_sa_bo *sa_bo;
772 uint32_t length_dw;
773 uint64_t gpu_addr;
774 uint32_t *ptr;
775 struct amdgpu_ring *ring;
776 struct amdgpu_fence *fence;
777 struct amdgpu_user_fence *user;
778 struct amdgpu_vm *vm;
3cb485f3 779 struct amdgpu_ctx *ctx;
97b2e202 780 struct amdgpu_sync sync;
97b2e202
AD		 781 uint32_t gds_base, gds_size;
782 uint32_t gws_base, gws_size;
783 uint32_t oa_base, oa_size;
de807f81 784 uint32_t flags;
5430a3ff
CK		 785 /* resulting sequence number */
786 uint64_t sequence;
97b2e202
AD		 787};
788
789enum amdgpu_ring_type {
790 AMDGPU_RING_TYPE_GFX,
791 AMDGPU_RING_TYPE_COMPUTE,
792 AMDGPU_RING_TYPE_SDMA,
793 AMDGPU_RING_TYPE_UVD,
794 AMDGPU_RING_TYPE_VCE
795};
796
c1b69ed0
CZ		 797extern struct amd_sched_backend_ops amdgpu_sched_ops;
798
3c704e93
CZ		 799int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
800 struct amdgpu_ring *ring,
801 struct amdgpu_ib *ibs,
802 unsigned num_ibs,
bb977d37 803 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 804 void *owner,
805 struct fence **fence);
3c704e93 806
97b2e202
AD		 807struct amdgpu_ring {
808 struct amdgpu_device *adev;
809 const struct amdgpu_ring_funcs *funcs;
810 struct amdgpu_fence_driver fence_drv;
4f839a24 811 struct amd_gpu_scheduler sched;
97b2e202 812
176e1ab1 813 spinlock_t fence_lock;
97b2e202
AD		 814 struct mutex *ring_lock;
815 struct amdgpu_bo *ring_obj;
816 volatile uint32_t *ring;
817 unsigned rptr_offs;
818 u64 next_rptr_gpu_addr;
819 volatile u32 *next_rptr_cpu_addr;
820 unsigned wptr;
821 unsigned wptr_old;
822 unsigned ring_size;
823 unsigned ring_free_dw;
824 int count_dw;
97b2e202
AD		 825 uint64_t gpu_addr;
826 uint32_t align_mask;
827 uint32_t ptr_mask;
828 bool ready;
829 u32 nop;
830 u32 idx;
831 u64 last_semaphore_signal_addr;
832 u64 last_semaphore_wait_addr;
833 u32 me;
834 u32 pipe;
835 u32 queue;
836 struct amdgpu_bo *mqd_obj;
837 u32 doorbell_index;
838 bool use_doorbell;
839 unsigned wptr_offs;
840 unsigned next_rptr_offs;
841 unsigned fence_offs;
3cb485f3 842 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 843 enum amdgpu_ring_type type;
844 char name[16];
4274f5d4 845 bool is_pte_ring;
97b2e202
AD		 846};
847
848/*
849 * VM
850 */
851
852/* maximum number of VMIDs */
853#define AMDGPU_NUM_VM 16
854
855/* number of entries in page table */
856#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
857
858/* PTBs (Page Table Blocks) need to be aligned to 32K */
859#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
860#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
861#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
862
863#define AMDGPU_PTE_VALID (1 << 0)
864#define AMDGPU_PTE_SYSTEM (1 << 1)
865#define AMDGPU_PTE_SNOOPED (1 << 2)
866
867/* VI only */
868#define AMDGPU_PTE_EXECUTABLE (1 << 4)
869
870#define AMDGPU_PTE_READABLE (1 << 5)
871#define AMDGPU_PTE_WRITEABLE (1 << 6)
872
873/* PTE (Page Table Entry) fragment field for different page sizes */
874#define AMDGPU_PTE_FRAG_4KB (0 << 7)
875#define AMDGPU_PTE_FRAG_64KB (4 << 7)
876#define AMDGPU_LOG2_PAGES_PER_FRAG 4
877
d9c13156
CK		 878/* How to programm VM fault handling */
879#define AMDGPU_VM_FAULT_STOP_NEVER 0
880#define AMDGPU_VM_FAULT_STOP_FIRST 1
881#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
882
97b2e202 883struct amdgpu_vm_pt {
ee1782c3
CK		 884 struct amdgpu_bo_list_entry entry;
885 uint64_t addr;
97b2e202
AD		 886};
887
888struct amdgpu_vm_id {
889 unsigned id;
890 uint64_t pd_gpu_addr;
891 /* last flushed PD/PT update */
3c62338c 892 struct fence *flushed_updates;
97b2e202
AD		 893};
894
895struct amdgpu_vm {
97b2e202
AD		 896 struct rb_root va;
897
7fc11959 898 /* protecting invalidated */
97b2e202
AD		 899 spinlock_t status_lock;
900
901 /* BOs moved, but not yet updated in the PT */
902 struct list_head invalidated;
903
7fc11959
CK		 904 /* BOs cleared in the PT because of a move */
905 struct list_head cleared;
906
907 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 908 struct list_head freed;
909
910 /* contains the page directory */
911 struct amdgpu_bo *page_directory;
912 unsigned max_pde_used;
05906dec 913 struct fence *page_directory_fence;
97b2e202
AD		 914
915 /* array of page tables, one for each page directory entry */
916 struct amdgpu_vm_pt *page_tables;
917
918 /* for id and flush management per ring */
919 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
c25867df
CZ		 920 /* for interval tree */
921 spinlock_t it_lock;
81d75a30 922 /* protecting freed */
923 spinlock_t freed_lock;
97b2e202
AD		 924};
925
926struct amdgpu_vm_manager {
1c16c0a7
CK		 927 struct {
928 struct fence *active;
929 atomic_long_t owner;
930 } ids[AMDGPU_NUM_VM];
931
8b4fb00b 932 uint32_t max_pfn;
97b2e202 933 /* number of VMIDs */
8b4fb00b 934 unsigned nvm;
97b2e202 935 /* vram base address for page table entry */
8b4fb00b 936 u64 vram_base_offset;
97b2e202 937 /* is vm enabled? */
8b4fb00b 938 bool enabled;
97b2e202
AD		 939 /* vm pte handling */
940 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
941 struct amdgpu_ring *vm_pte_funcs_ring;
942};
943
ea89f8c9 944void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 945int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
946void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 947void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
948 struct list_head *validated,
949 struct amdgpu_bo_list_entry *entry);
ee1782c3 950void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 951void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
952 struct amdgpu_vm *vm);
8b4fb00b
CK		 953int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
954 struct amdgpu_sync *sync);
955void amdgpu_vm_flush(struct amdgpu_ring *ring,
956 struct amdgpu_vm *vm,
957 struct fence *updates);
958void amdgpu_vm_fence(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm,
960 struct fence *fence);
961uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
962int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
963 struct amdgpu_vm *vm);
964int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
965 struct amdgpu_vm *vm);
966int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
967 struct amdgpu_sync *sync);
968int amdgpu_vm_bo_update(struct amdgpu_device *adev,
969 struct amdgpu_bo_va *bo_va,
970 struct ttm_mem_reg *mem);
971void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
972 struct amdgpu_bo *bo);
973struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
974 struct amdgpu_bo *bo);
975struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
976 struct amdgpu_vm *vm,
977 struct amdgpu_bo *bo);
978int amdgpu_vm_bo_map(struct amdgpu_device *adev,
979 struct amdgpu_bo_va *bo_va,
980 uint64_t addr, uint64_t offset,
981 uint64_t size, uint32_t flags);
982int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
983 struct amdgpu_bo_va *bo_va,
984 uint64_t addr);
985void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
986 struct amdgpu_bo_va *bo_va);
987int amdgpu_vm_free_job(struct amdgpu_job *job);
988
97b2e202
AD		 989/*
990 * context related structures
991 */
992
21c16bf6 993struct amdgpu_ctx_ring {
91404fb2 994 uint64_t sequence;
37cd0ca2 995 struct fence **fences;
91404fb2 996 struct amd_sched_entity entity;
21c16bf6
CK		 997};
998
97b2e202 999struct amdgpu_ctx {
0b492a4c 1000 struct kref refcount;
9cb7e5a9 1001 struct amdgpu_device *adev;
0b492a4c 1002 unsigned reset_counter;
21c16bf6 1003 spinlock_t ring_lock;
37cd0ca2 1004 struct fence **fences;
21c16bf6 1005 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1006};
1007
1008struct amdgpu_ctx_mgr {
0b492a4c
AD		 1009 struct amdgpu_device *adev;
1010 struct mutex lock;
1011 /* protected by lock */
1012 struct idr ctx_handles;
97b2e202
AD		 1013};
1014
d033a6de 1015int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
47f38501
CK		 1016 struct amdgpu_ctx *ctx);
1017void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1018
0b492a4c
AD		 1019struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1020int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1021
21c16bf6 1022uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1023 struct fence *fence);
21c16bf6
CK		 1024struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1025 struct amdgpu_ring *ring, uint64_t seq);
1026
0b492a4c
AD		 1027int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *filp);
1029
efd4ccb5
CK		 1030void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1031void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1032
97b2e202
AD		 1033/*
1034 * file private structure
1035 */
1036
1037struct amdgpu_fpriv {
1038 struct amdgpu_vm vm;
1039 struct mutex bo_list_lock;
1040 struct idr bo_list_handles;
0b492a4c 1041 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1042};
1043
1044/*
1045 * residency list
1046 */
1047
1048struct amdgpu_bo_list {
1049 struct mutex lock;
1050 struct amdgpu_bo *gds_obj;
1051 struct amdgpu_bo *gws_obj;
1052 struct amdgpu_bo *oa_obj;
1053 bool has_userptr;
1054 unsigned num_entries;
1055 struct amdgpu_bo_list_entry *array;
1056};
1057
1058struct amdgpu_bo_list *
1059amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1060void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1061void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1062
1063/*
1064 * GFX stuff
1065 */
1066#include "clearstate_defs.h"
1067
1068struct amdgpu_rlc {
1069 /* for power gating */
1070 struct amdgpu_bo *save_restore_obj;
1071 uint64_t save_restore_gpu_addr;
1072 volatile uint32_t *sr_ptr;
1073 const u32 *reg_list;
1074 u32 reg_list_size;
1075 /* for clear state */
1076 struct amdgpu_bo *clear_state_obj;
1077 uint64_t clear_state_gpu_addr;
1078 volatile uint32_t *cs_ptr;
1079 const struct cs_section_def *cs_data;
1080 u32 clear_state_size;
1081 /* for cp tables */
1082 struct amdgpu_bo *cp_table_obj;
1083 uint64_t cp_table_gpu_addr;
1084 volatile uint32_t *cp_table_ptr;
1085 u32 cp_table_size;
1086};
1087
1088struct amdgpu_mec {
1089 struct amdgpu_bo *hpd_eop_obj;
1090 u64 hpd_eop_gpu_addr;
1091 u32 num_pipe;
1092 u32 num_mec;
1093 u32 num_queue;
1094};
1095
1096/*
1097 * GPU scratch registers structures, functions & helpers
1098 */
1099struct amdgpu_scratch {
1100 unsigned num_reg;
1101 uint32_t reg_base;
1102 bool free[32];
1103 uint32_t reg[32];
1104};
1105
1106/*
1107 * GFX configurations
1108 */
1109struct amdgpu_gca_config {
1110 unsigned max_shader_engines;
1111 unsigned max_tile_pipes;
1112 unsigned max_cu_per_sh;
1113 unsigned max_sh_per_se;
1114 unsigned max_backends_per_se;
1115 unsigned max_texture_channel_caches;
1116 unsigned max_gprs;
1117 unsigned max_gs_threads;
1118 unsigned max_hw_contexts;
1119 unsigned sc_prim_fifo_size_frontend;
1120 unsigned sc_prim_fifo_size_backend;
1121 unsigned sc_hiz_tile_fifo_size;
1122 unsigned sc_earlyz_tile_fifo_size;
1123
1124 unsigned num_tile_pipes;
1125 unsigned backend_enable_mask;
1126 unsigned mem_max_burst_length_bytes;
1127 unsigned mem_row_size_in_kb;
1128 unsigned shader_engine_tile_size;
1129 unsigned num_gpus;
1130 unsigned multi_gpu_tile_size;
1131 unsigned mc_arb_ramcfg;
1132 unsigned gb_addr_config;
1133
1134 uint32_t tile_mode_array[32];
1135 uint32_t macrotile_mode_array[16];
1136};
1137
1138struct amdgpu_gfx {
1139 struct mutex gpu_clock_mutex;
1140 struct amdgpu_gca_config config;
1141 struct amdgpu_rlc rlc;
1142 struct amdgpu_mec mec;
1143 struct amdgpu_scratch scratch;
1144 const struct firmware *me_fw; /* ME firmware */
1145 uint32_t me_fw_version;
1146 const struct firmware *pfp_fw; /* PFP firmware */
1147 uint32_t pfp_fw_version;
1148 const struct firmware *ce_fw; /* CE firmware */
1149 uint32_t ce_fw_version;
1150 const struct firmware *rlc_fw; /* RLC firmware */
1151 uint32_t rlc_fw_version;
1152 const struct firmware *mec_fw; /* MEC firmware */
1153 uint32_t mec_fw_version;
1154 const struct firmware *mec2_fw; /* MEC2 firmware */
1155 uint32_t mec2_fw_version;
02558a00
KW		 1156 uint32_t me_feature_version;
1157 uint32_t ce_feature_version;
1158 uint32_t pfp_feature_version;
351643d7
JZ		 1159 uint32_t rlc_feature_version;
1160 uint32_t mec_feature_version;
1161 uint32_t mec2_feature_version;
97b2e202
AD		 1162 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1163 unsigned num_gfx_rings;
1164 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1165 unsigned num_compute_rings;
1166 struct amdgpu_irq_src eop_irq;
1167 struct amdgpu_irq_src priv_reg_irq;
1168 struct amdgpu_irq_src priv_inst_irq;
1169 /* gfx status */
1170 uint32_t gfx_current_status;
a101a899
KW		 1171 /* ce ram size*/
1172 unsigned ce_ram_size;
97b2e202
AD		 1173};
1174
1175int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1176 unsigned size, struct amdgpu_ib *ib);
1177void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1178int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1179 struct amdgpu_ib *ib, void *owner);
1180int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1181void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1182int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1183/* Ring access between begin & end cannot sleep */
1184void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1185int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1186int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1187void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 1188void amdgpu_ring_commit(struct amdgpu_ring *ring);
1189void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1190void amdgpu_ring_undo(struct amdgpu_ring *ring);
1191void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1192unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1193 uint32_t **data);
1194int amdgpu_ring_restore(struct amdgpu_ring *ring,
1195 unsigned size, uint32_t *data);
1196int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1197 unsigned ring_size, u32 nop, u32 align_mask,
1198 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1199 enum amdgpu_ring_type ring_type);
1200void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1201struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1202
1203/*
1204 * CS.
1205 */
1206struct amdgpu_cs_chunk {
1207 uint32_t chunk_id;
1208 uint32_t length_dw;
1209 uint32_t *kdata;
1210 void __user *user_ptr;
1211};
1212
1213struct amdgpu_cs_parser {
1214 struct amdgpu_device *adev;
1215 struct drm_file *filp;
3cb485f3 1216 struct amdgpu_ctx *ctx;
97b2e202
AD		 1217 struct amdgpu_bo_list *bo_list;
1218 /* chunks */
1219 unsigned nchunks;
1220 struct amdgpu_cs_chunk *chunks;
1221 /* relocations */
56467ebf 1222 struct amdgpu_bo_list_entry vm_pd;
97b2e202 1223 struct list_head validated;
984810fc 1224 struct fence *fence;
97b2e202
AD		 1225
1226 struct amdgpu_ib *ibs;
1227 uint32_t num_ibs;
1228
1229 struct ww_acquire_ctx ticket;
1230
1231 /* user fence */
91acbeb6
CK		 1232 struct amdgpu_user_fence uf;
1233 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1234};
1235
bb977d37
CZ		 1236struct amdgpu_job {
1237 struct amd_sched_job base;
1238 struct amdgpu_device *adev;
bb977d37
CZ		 1239 struct amdgpu_ib *ibs;
1240 uint32_t num_ibs;
e2840221 1241 void *owner;
bb977d37 1242 struct amdgpu_user_fence uf;
4c7eb91c 1243 int (*free_job)(struct amdgpu_job *job);
bb977d37 1244};
a6db8a33
JZ		 1245#define to_amdgpu_job(sched_job) \
1246 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1247
97b2e202
AD		 1248static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1249{
1250 return p->ibs[ib_idx].ptr[idx];
1251}
1252
1253/*
1254 * Writeback
1255 */
1256#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1257
1258struct amdgpu_wb {
1259 struct amdgpu_bo *wb_obj;
1260 volatile uint32_t *wb;
1261 uint64_t gpu_addr;
1262 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1263 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1264};
1265
1266int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1267void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1268
97b2e202 1269
97b2e202
AD		 1270
1271enum amdgpu_int_thermal_type {
1272 THERMAL_TYPE_NONE,
1273 THERMAL_TYPE_EXTERNAL,
1274 THERMAL_TYPE_EXTERNAL_GPIO,
1275 THERMAL_TYPE_RV6XX,
1276 THERMAL_TYPE_RV770,
1277 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1278 THERMAL_TYPE_EVERGREEN,
1279 THERMAL_TYPE_SUMO,
1280 THERMAL_TYPE_NI,
1281 THERMAL_TYPE_SI,
1282 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1283 THERMAL_TYPE_CI,
1284 THERMAL_TYPE_KV,
1285};
1286
1287enum amdgpu_dpm_auto_throttle_src {
1288 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1289 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1290};
1291
1292enum amdgpu_dpm_event_src {
1293 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1294 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1295 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1296 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1297 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1298};
1299
1300#define AMDGPU_MAX_VCE_LEVELS 6
1301
1302enum amdgpu_vce_level {
1303 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1304 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1305 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1306 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1307 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1308 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1309};
1310
1311struct amdgpu_ps {
1312 u32 caps; /* vbios flags */
1313 u32 class; /* vbios flags */
1314 u32 class2; /* vbios flags */
1315 /* UVD clocks */
1316 u32 vclk;
1317 u32 dclk;
1318 /* VCE clocks */
1319 u32 evclk;
1320 u32 ecclk;
1321 bool vce_active;
1322 enum amdgpu_vce_level vce_level;
1323 /* asic priv */
1324 void *ps_priv;
1325};
1326
1327struct amdgpu_dpm_thermal {
1328 /* thermal interrupt work */
1329 struct work_struct work;
1330 /* low temperature threshold */
1331 int min_temp;
1332 /* high temperature threshold */
1333 int max_temp;
1334 /* was last interrupt low to high or high to low */
1335 bool high_to_low;
1336 /* interrupt source */
1337 struct amdgpu_irq_src irq;
1338};
1339
1340enum amdgpu_clk_action
1341{
1342 AMDGPU_SCLK_UP = 1,
1343 AMDGPU_SCLK_DOWN
1344};
1345
1346struct amdgpu_blacklist_clocks
1347{
1348 u32 sclk;
1349 u32 mclk;
1350 enum amdgpu_clk_action action;
1351};
1352
1353struct amdgpu_clock_and_voltage_limits {
1354 u32 sclk;
1355 u32 mclk;
1356 u16 vddc;
1357 u16 vddci;
1358};
1359
1360struct amdgpu_clock_array {
1361 u32 count;
1362 u32 *values;
1363};
1364
1365struct amdgpu_clock_voltage_dependency_entry {
1366 u32 clk;
1367 u16 v;
1368};
1369
1370struct amdgpu_clock_voltage_dependency_table {
1371 u32 count;
1372 struct amdgpu_clock_voltage_dependency_entry *entries;
1373};
1374
1375union amdgpu_cac_leakage_entry {
1376 struct {
1377 u16 vddc;
1378 u32 leakage;
1379 };
1380 struct {
1381 u16 vddc1;
1382 u16 vddc2;
1383 u16 vddc3;
1384 };
1385};
1386
1387struct amdgpu_cac_leakage_table {
1388 u32 count;
1389 union amdgpu_cac_leakage_entry *entries;
1390};
1391
1392struct amdgpu_phase_shedding_limits_entry {
1393 u16 voltage;
1394 u32 sclk;
1395 u32 mclk;
1396};
1397
1398struct amdgpu_phase_shedding_limits_table {
1399 u32 count;
1400 struct amdgpu_phase_shedding_limits_entry *entries;
1401};
1402
1403struct amdgpu_uvd_clock_voltage_dependency_entry {
1404 u32 vclk;
1405 u32 dclk;
1406 u16 v;
1407};
1408
1409struct amdgpu_uvd_clock_voltage_dependency_table {
1410 u8 count;
1411 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1412};
1413
1414struct amdgpu_vce_clock_voltage_dependency_entry {
1415 u32 ecclk;
1416 u32 evclk;
1417 u16 v;
1418};
1419
1420struct amdgpu_vce_clock_voltage_dependency_table {
1421 u8 count;
1422 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1423};
1424
1425struct amdgpu_ppm_table {
1426 u8 ppm_design;
1427 u16 cpu_core_number;
1428 u32 platform_tdp;
1429 u32 small_ac_platform_tdp;
1430 u32 platform_tdc;
1431 u32 small_ac_platform_tdc;
1432 u32 apu_tdp;
1433 u32 dgpu_tdp;
1434 u32 dgpu_ulv_power;
1435 u32 tj_max;
1436};
1437
1438struct amdgpu_cac_tdp_table {
1439 u16 tdp;
1440 u16 configurable_tdp;
1441 u16 tdc;
1442 u16 battery_power_limit;
1443 u16 small_power_limit;
1444 u16 low_cac_leakage;
1445 u16 high_cac_leakage;
1446 u16 maximum_power_delivery_limit;
1447};
1448
1449struct amdgpu_dpm_dynamic_state {
1450 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1451 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1452 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1453 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1454 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1455 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1456 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1457 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1458 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1459 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1460 struct amdgpu_clock_array valid_sclk_values;
1461 struct amdgpu_clock_array valid_mclk_values;
1462 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1463 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1464 u32 mclk_sclk_ratio;
1465 u32 sclk_mclk_delta;
1466 u16 vddc_vddci_delta;
1467 u16 min_vddc_for_pcie_gen2;
1468 struct amdgpu_cac_leakage_table cac_leakage_table;
1469 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1470 struct amdgpu_ppm_table *ppm_table;
1471 struct amdgpu_cac_tdp_table *cac_tdp_table;
1472};
1473
1474struct amdgpu_dpm_fan {
1475 u16 t_min;
1476 u16 t_med;
1477 u16 t_high;
1478 u16 pwm_min;
1479 u16 pwm_med;
1480 u16 pwm_high;
1481 u8 t_hyst;
1482 u32 cycle_delay;
1483 u16 t_max;
1484 u8 control_mode;
1485 u16 default_max_fan_pwm;
1486 u16 default_fan_output_sensitivity;
1487 u16 fan_output_sensitivity;
1488 bool ucode_fan_control;
1489};
1490
1491enum amdgpu_pcie_gen {
1492 AMDGPU_PCIE_GEN1 = 0,
1493 AMDGPU_PCIE_GEN2 = 1,
1494 AMDGPU_PCIE_GEN3 = 2,
1495 AMDGPU_PCIE_GEN_INVALID = 0xffff
1496};
1497
1498enum amdgpu_dpm_forced_level {
1499 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1500 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1501 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1502};
1503
1504struct amdgpu_vce_state {
1505 /* vce clocks */
1506 u32 evclk;
1507 u32 ecclk;
1508 /* gpu clocks */
1509 u32 sclk;
1510 u32 mclk;
1511 u8 clk_idx;
1512 u8 pstate;
1513};
1514
1515struct amdgpu_dpm_funcs {
1516 int (*get_temperature)(struct amdgpu_device *adev);
1517 int (*pre_set_power_state)(struct amdgpu_device *adev);
1518 int (*set_power_state)(struct amdgpu_device *adev);
1519 void (*post_set_power_state)(struct amdgpu_device *adev);
1520 void (*display_configuration_changed)(struct amdgpu_device *adev);
1521 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1522 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1523 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1524 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1525 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1526 bool (*vblank_too_short)(struct amdgpu_device *adev);
1527 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1528 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1529 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1530 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1531 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1532 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1533 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1534};
1535
1536struct amdgpu_dpm {
1537 struct amdgpu_ps *ps;
1538 /* number of valid power states */
1539 int num_ps;
1540 /* current power state that is active */
1541 struct amdgpu_ps *current_ps;
1542 /* requested power state */
1543 struct amdgpu_ps *requested_ps;
1544 /* boot up power state */
1545 struct amdgpu_ps *boot_ps;
1546 /* default uvd power state */
1547 struct amdgpu_ps *uvd_ps;
1548 /* vce requirements */
1549 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1550 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1551 enum amd_pm_state_type state;
1552 enum amd_pm_state_type user_state;
97b2e202
AD		 1553 u32 platform_caps;
1554 u32 voltage_response_time;
1555 u32 backbias_response_time;
1556 void *priv;
1557 u32 new_active_crtcs;
1558 int new_active_crtc_count;
1559 u32 current_active_crtcs;
1560 int current_active_crtc_count;
1561 struct amdgpu_dpm_dynamic_state dyn_state;
1562 struct amdgpu_dpm_fan fan;
1563 u32 tdp_limit;
1564 u32 near_tdp_limit;
1565 u32 near_tdp_limit_adjusted;
1566 u32 sq_ramping_threshold;
1567 u32 cac_leakage;
1568 u16 tdp_od_limit;
1569 u32 tdp_adjustment;
1570 u16 load_line_slope;
1571 bool power_control;
1572 bool ac_power;
1573 /* special states active */
1574 bool thermal_active;
1575 bool uvd_active;
1576 bool vce_active;
1577 /* thermal handling */
1578 struct amdgpu_dpm_thermal thermal;
1579 /* forced levels */
1580 enum amdgpu_dpm_forced_level forced_level;
1581};
1582
1583struct amdgpu_pm {
1584 struct mutex mutex;
97b2e202
AD		 1585 u32 current_sclk;
1586 u32 current_mclk;
1587 u32 default_sclk;
1588 u32 default_mclk;
1589 struct amdgpu_i2c_chan *i2c_bus;
1590 /* internal thermal controller on rv6xx+ */
1591 enum amdgpu_int_thermal_type int_thermal_type;
1592 struct device *int_hwmon_dev;
1593 /* fan control parameters */
1594 bool no_fan;
1595 u8 fan_pulses_per_revolution;
1596 u8 fan_min_rpm;
1597 u8 fan_max_rpm;
1598 /* dpm */
1599 bool dpm_enabled;
c86f5ebf 1600 bool sysfs_initialized;
97b2e202
AD		 1601 struct amdgpu_dpm dpm;
1602 const struct firmware *fw; /* SMC firmware */
1603 uint32_t fw_version;
1604 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1605 uint32_t pcie_gen_mask;
1606 uint32_t pcie_mlw_mask;
7fb72a1f 1607 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1608};
1609
d0dd7f0c
AD		 1610void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1611
97b2e202
AD		 1612/*
1613 * UVD
1614 */
1615#define AMDGPU_MAX_UVD_HANDLES 10
1616#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1617#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1618#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1619
1620struct amdgpu_uvd {
1621 struct amdgpu_bo *vcpu_bo;
1622 void *cpu_addr;
1623 uint64_t gpu_addr;
97b2e202
AD		 1624 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1625 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1626 struct delayed_work idle_work;
1627 const struct firmware *fw; /* UVD firmware */
1628 struct amdgpu_ring ring;
1629 struct amdgpu_irq_src irq;
1630 bool address_64_bit;
1631};
1632
1633/*
1634 * VCE
1635 */
1636#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1637#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1638
6a585777
AD		 1639#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1640#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1641
97b2e202
AD		 1642struct amdgpu_vce {
1643 struct amdgpu_bo *vcpu_bo;
1644 uint64_t gpu_addr;
1645 unsigned fw_version;
1646 unsigned fb_version;
1647 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1648 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1649 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1650 struct delayed_work idle_work;
1651 const struct firmware *fw; /* VCE firmware */
1652 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1653 struct amdgpu_irq_src irq;
6a585777 1654 unsigned harvest_config;
97b2e202
AD		 1655};
1656
1657/*
1658 * SDMA
1659 */
c113ea1c 1660struct amdgpu_sdma_instance {
97b2e202
AD		 1661 /* SDMA firmware */
1662 const struct firmware *fw;
1663 uint32_t fw_version;
cfa2104f 1664 uint32_t feature_version;
97b2e202
AD		 1665
1666 struct amdgpu_ring ring;
18111de0 1667 bool burst_nop;
97b2e202
AD		 1668};
1669
c113ea1c
AD		 1670struct amdgpu_sdma {
1671 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1672 struct amdgpu_irq_src trap_irq;
1673 struct amdgpu_irq_src illegal_inst_irq;
1674 int num_instances;
1675};
1676
97b2e202
AD		 1677/*
1678 * Firmware
1679 */
1680struct amdgpu_firmware {
1681 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1682 bool smu_load;
1683 struct amdgpu_bo *fw_buf;
1684 unsigned int fw_size;
1685};
1686
1687/*
1688 * Benchmarking
1689 */
1690void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1691
1692
1693/*
1694 * Testing
1695 */
1696void amdgpu_test_moves(struct amdgpu_device *adev);
1697void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1698 struct amdgpu_ring *cpA,
1699 struct amdgpu_ring *cpB);
1700void amdgpu_test_syncing(struct amdgpu_device *adev);
1701
1702/*
1703 * MMU Notifier
1704 */
1705#if defined(CONFIG_MMU_NOTIFIER)
1706int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1707void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1708#else
1d1106b0 1709static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1710{
1711 return -ENODEV;
1712}
1d1106b0 1713static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1714#endif
1715
1716/*
1717 * Debugfs
1718 */
1719struct amdgpu_debugfs {
1720 struct drm_info_list *files;
1721 unsigned num_files;
1722};
1723
1724int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1725 struct drm_info_list *files,
1726 unsigned nfiles);
1727int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1728
1729#if defined(CONFIG_DEBUG_FS)
1730int amdgpu_debugfs_init(struct drm_minor *minor);
1731void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1732#endif
1733
1734/*
1735 * amdgpu smumgr functions
1736 */
1737struct amdgpu_smumgr_funcs {
1738 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1739 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1740 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1741};
1742
1743/*
1744 * amdgpu smumgr
1745 */
1746struct amdgpu_smumgr {
1747 struct amdgpu_bo *toc_buf;
1748 struct amdgpu_bo *smu_buf;
1749 /* asic priv smu data */
1750 void *priv;
1751 spinlock_t smu_lock;
1752 /* smumgr functions */
1753 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1754 /* ucode loading complete flag */
1755 uint32_t fw_flags;
1756};
1757
1758/*
1759 * ASIC specific register table accessible by UMD
1760 */
1761struct amdgpu_allowed_register_entry {
1762 uint32_t reg_offset;
1763 bool untouched;
1764 bool grbm_indexed;
1765};
1766
1767struct amdgpu_cu_info {
1768 uint32_t number; /* total active CU number */
1769 uint32_t ao_cu_mask;
1770 uint32_t bitmap[4][4];
1771};
1772
1773
1774/*
1775 * ASIC specific functions.
1776 */
1777struct amdgpu_asic_funcs {
1778 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1779 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1780 u8 *bios, u32 length_bytes);
97b2e202
AD		 1781 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1782 u32 sh_num, u32 reg_offset, u32 *value);
1783 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1784 int (*reset)(struct amdgpu_device *adev);
1785 /* wait for mc_idle */
1786 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1787 /* get the reference clock */
1788 u32 (*get_xclk)(struct amdgpu_device *adev);
1789 /* get the gpu clock counter */
1790 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1791 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1792 /* MM block clocks */
1793 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1794 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1795};
1796
1797/*
1798 * IOCTL.
1799 */
1800int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1801 struct drm_file *filp);
1802int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1803 struct drm_file *filp);
1804
1805int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1806 struct drm_file *filp);
1807int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1808 struct drm_file *filp);
1809int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1810 struct drm_file *filp);
1811int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *filp);
1815int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1818int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1819
1820int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822
1823/* VRAM scratch page for HDP bug, default vram page */
1824struct amdgpu_vram_scratch {
1825 struct amdgpu_bo *robj;
1826 volatile uint32_t *ptr;
1827 u64 gpu_addr;
1828};
1829
1830/*
1831 * ACPI
1832 */
1833struct amdgpu_atif_notification_cfg {
1834 bool enabled;
1835 int command_code;
1836};
1837
1838struct amdgpu_atif_notifications {
1839 bool display_switch;
1840 bool expansion_mode_change;
1841 bool thermal_state;
1842 bool forced_power_state;
1843 bool system_power_state;
1844 bool display_conf_change;
1845 bool px_gfx_switch;
1846 bool brightness_change;
1847 bool dgpu_display_event;
1848};
1849
1850struct amdgpu_atif_functions {
1851 bool system_params;
1852 bool sbios_requests;
1853 bool select_active_disp;
1854 bool lid_state;
1855 bool get_tv_standard;
1856 bool set_tv_standard;
1857 bool get_panel_expansion_mode;
1858 bool set_panel_expansion_mode;
1859 bool temperature_change;
1860 bool graphics_device_types;
1861};
1862
1863struct amdgpu_atif {
1864 struct amdgpu_atif_notifications notifications;
1865 struct amdgpu_atif_functions functions;
1866 struct amdgpu_atif_notification_cfg notification_cfg;
1867 struct amdgpu_encoder *encoder_for_bl;
1868};
1869
1870struct amdgpu_atcs_functions {
1871 bool get_ext_state;
1872 bool pcie_perf_req;
1873 bool pcie_dev_rdy;
1874 bool pcie_bus_width;
1875};
1876
1877struct amdgpu_atcs {
1878 struct amdgpu_atcs_functions functions;
1879};
1880
d03846af
CZ		 1881/*
1882 * CGS
1883 */
1884void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1885void amdgpu_cgs_destroy_device(void *cgs_device);
1886
1887
97b2e202
AD		 1888/*
1889 * Core structure, functions and helpers.
1890 */
1891typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1892typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1893
1894typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1895typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1896
8faf0e08
AD		 1897struct amdgpu_ip_block_status {
1898 bool valid;
1899 bool sw;
1900 bool hw;
1901};
1902
97b2e202
AD		 1903struct amdgpu_device {
1904 struct device *dev;
1905 struct drm_device *ddev;
1906 struct pci_dev *pdev;
97b2e202
AD		 1907
1908 /* ASIC */
2f7d10b3 1909 enum amd_asic_type asic_type;
97b2e202
AD		 1910 uint32_t family;
1911 uint32_t rev_id;
1912 uint32_t external_rev_id;
1913 unsigned long flags;
1914 int usec_timeout;
1915 const struct amdgpu_asic_funcs *asic_funcs;
1916 bool shutdown;
1917 bool suspend;
1918 bool need_dma32;
1919 bool accel_working;
97b2e202
AD		 1920 struct work_struct reset_work;
1921 struct notifier_block acpi_nb;
1922 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1923 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1924 unsigned debugfs_count;
1925#if defined(CONFIG_DEBUG_FS)
1926 struct dentry *debugfs_regs;
1927#endif
1928 struct amdgpu_atif atif;
1929 struct amdgpu_atcs atcs;
1930 struct mutex srbm_mutex;
1931 /* GRBM index mutex. Protects concurrent access to GRBM index */
1932 struct mutex grbm_idx_mutex;
1933 struct dev_pm_domain vga_pm_domain;
1934 bool have_disp_power_ref;
1935
1936 /* BIOS */
1937 uint8_t *bios;
1938 bool is_atom_bios;
1939 uint16_t bios_header_start;
1940 struct amdgpu_bo *stollen_vga_memory;
1941 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1942
1943 /* Register/doorbell mmio */
1944 resource_size_t rmmio_base;
1945 resource_size_t rmmio_size;
1946 void __iomem *rmmio;
1947 /* protects concurrent MM_INDEX/DATA based register access */
1948 spinlock_t mmio_idx_lock;
1949 /* protects concurrent SMC based register access */
1950 spinlock_t smc_idx_lock;
1951 amdgpu_rreg_t smc_rreg;
1952 amdgpu_wreg_t smc_wreg;
1953 /* protects concurrent PCIE register access */
1954 spinlock_t pcie_idx_lock;
1955 amdgpu_rreg_t pcie_rreg;
1956 amdgpu_wreg_t pcie_wreg;
1957 /* protects concurrent UVD register access */
1958 spinlock_t uvd_ctx_idx_lock;
1959 amdgpu_rreg_t uvd_ctx_rreg;
1960 amdgpu_wreg_t uvd_ctx_wreg;
1961 /* protects concurrent DIDT register access */
1962 spinlock_t didt_idx_lock;
1963 amdgpu_rreg_t didt_rreg;
1964 amdgpu_wreg_t didt_wreg;
1965 /* protects concurrent ENDPOINT (audio) register access */
1966 spinlock_t audio_endpt_idx_lock;
1967 amdgpu_block_rreg_t audio_endpt_rreg;
1968 amdgpu_block_wreg_t audio_endpt_wreg;
1969 void __iomem *rio_mem;
1970 resource_size_t rio_mem_size;
1971 struct amdgpu_doorbell doorbell;
1972
1973 /* clock/pll info */
1974 struct amdgpu_clock clock;
1975
1976 /* MC */
1977 struct amdgpu_mc mc;
1978 struct amdgpu_gart gart;
1979 struct amdgpu_dummy_page dummy_page;
1980 struct amdgpu_vm_manager vm_manager;
1981
1982 /* memory management */
1983 struct amdgpu_mman mman;
1984 struct amdgpu_gem gem;
1985 struct amdgpu_vram_scratch vram_scratch;
1986 struct amdgpu_wb wb;
1987 atomic64_t vram_usage;
1988 atomic64_t vram_vis_usage;
1989 atomic64_t gtt_usage;
1990 atomic64_t num_bytes_moved;
d94aed5a 1991 atomic_t gpu_reset_counter;
97b2e202
AD		 1992
1993 /* display */
1994 struct amdgpu_mode_info mode_info;
1995 struct work_struct hotplug_work;
1996 struct amdgpu_irq_src crtc_irq;
1997 struct amdgpu_irq_src pageflip_irq;
1998 struct amdgpu_irq_src hpd_irq;
1999
2000 /* rings */
97b2e202
AD		 2001 unsigned fence_context;
2002 struct mutex ring_lock;
2003 unsigned num_rings;
2004 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2005 bool ib_pool_ready;
2006 struct amdgpu_sa_manager ring_tmp_bo;
2007
2008 /* interrupts */
2009 struct amdgpu_irq irq;
2010
1f7371b2
AD		 2011 /* powerplay */
2012 struct amd_powerplay powerplay;
e61710c5 2013 bool pp_enabled;
1f7371b2 2014
97b2e202
AD		 2015 /* dpm */
2016 struct amdgpu_pm pm;
2017 u32 cg_flags;
2018 u32 pg_flags;
2019
2020 /* amdgpu smumgr */
2021 struct amdgpu_smumgr smu;
2022
2023 /* gfx */
2024 struct amdgpu_gfx gfx;
2025
2026 /* sdma */
c113ea1c 2027 struct amdgpu_sdma sdma;
97b2e202
AD		 2028
2029 /* uvd */
2030 bool has_uvd;
2031 struct amdgpu_uvd uvd;
2032
2033 /* vce */
2034 struct amdgpu_vce vce;
2035
2036 /* firmwares */
2037 struct amdgpu_firmware firmware;
2038
2039 /* GDS */
2040 struct amdgpu_gds gds;
2041
2042 const struct amdgpu_ip_block_version *ip_blocks;
2043 int num_ip_blocks;
8faf0e08 2044 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2045 struct mutex mn_lock;
2046 DECLARE_HASHTABLE(mn_hash, 7);
2047
2048 /* tracking pinned memory */
2049 u64 vram_pin_size;
2050 u64 gart_pin_size;
130e0371
OG		 2051
2052 /* amdkfd interface */
2053 struct kfd_dev *kfd;
23ca0e4e
CZ		 2054
2055 /* kernel conext for IB submission */
47f38501 2056 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2057};
2058
2059bool amdgpu_device_is_px(struct drm_device *dev);
2060int amdgpu_device_init(struct amdgpu_device *adev,
2061 struct drm_device *ddev,
2062 struct pci_dev *pdev,
2063 uint32_t flags);
2064void amdgpu_device_fini(struct amdgpu_device *adev);
2065int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2066
2067uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2068 bool always_indirect);
2069void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2070 bool always_indirect);
2071u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2072void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2073
2074u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2075void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2076
2077/*
2078 * Cast helper
2079 */
2080extern const struct fence_ops amdgpu_fence_ops;
2081static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2082{
2083 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2084
2085 if (__f->base.ops == &amdgpu_fence_ops)
2086 return __f;
2087
2088 return NULL;
2089}
2090
2091/*
2092 * Registers read & write functions.
2093 */
2094#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2095#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2096#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2097#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2098#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2099#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2100#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2101#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2102#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2103#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2104#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2105#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2106#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2107#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2108#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2109#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2110#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2111#define WREG32_P(reg, val, mask) \
2112 do { \
2113 uint32_t tmp_ = RREG32(reg); \
2114 tmp_ &= (mask); \
2115 tmp_ |= ((val) & ~(mask)); \
2116 WREG32(reg, tmp_); \
2117 } while (0)
2118#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2119#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2120#define WREG32_PLL_P(reg, val, mask) \
2121 do { \
2122 uint32_t tmp_ = RREG32_PLL(reg); \
2123 tmp_ &= (mask); \
2124 tmp_ |= ((val) & ~(mask)); \
2125 WREG32_PLL(reg, tmp_); \
2126 } while (0)
2127#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2128#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2129#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2130
2131#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2132#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2133
2134#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2135#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2136
2137#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2138 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2139 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2140
2141#define REG_GET_FIELD(value, reg, field) \
2142 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2143
2144/*
2145 * BIOS helpers.
2146 */
2147#define RBIOS8(i) (adev->bios[i])
2148#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2149#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2150
2151/*
2152 * RING helpers.
2153 */
2154static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2155{
2156 if (ring->count_dw <= 0)
86c2b790 2157 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2158 ring->ring[ring->wptr++] = v;
2159 ring->wptr &= ring->ptr_mask;
2160 ring->count_dw--;
2161 ring->ring_free_dw--;
2162}
2163
c113ea1c
AD		 2164static inline struct amdgpu_sdma_instance *
2165amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2166{
2167 struct amdgpu_device *adev = ring->adev;
2168 int i;
2169
c113ea1c
AD		 2170 for (i = 0; i < adev->sdma.num_instances; i++)
2171 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2172 break;
2173
2174 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2175 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2176 else
2177 return NULL;
2178}
2179
97b2e202
AD		 2180/*
2181 * ASICs macro.
2182 */
2183#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2184#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2185#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2186#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2187#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2188#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2189#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2190#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2191#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2192#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2193#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2194#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2195#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2196#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2197#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2198#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2199#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2200#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2201#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2202#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2203#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2204#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2205#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2206#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2207#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2208#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2209#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2210#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2211#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2212#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2213#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2214#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2215#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2216#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2217#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2218#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2219#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2220#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2221#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2222#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2223#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2224#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2225#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2226#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2227#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2228#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2229#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2230#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2231#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2232#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2233#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2234#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2235#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2236#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2237#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2238#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2239#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2240
2241#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2242 ((adev)->pp_enabled ? \
e61710c5 2243 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2244 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2245
2246#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2247 ((adev)->pp_enabled ? \
e61710c5 2248 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2249 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2250
2251#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2252 ((adev)->pp_enabled ? \
e61710c5 2253 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2254 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2255
2256#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2257 ((adev)->pp_enabled ? \
e61710c5 2258 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2259 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2260
2261#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2262 ((adev)->pp_enabled ? \
e61710c5 2263 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2264 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2265
1b5708ff 2266#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2267 ((adev)->pp_enabled ? \
e61710c5 2268 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2269 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2270
2271#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2272 ((adev)->pp_enabled ? \
e61710c5 2273 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2274 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2275
2276
2277#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2278 ((adev)->pp_enabled ? \
e61710c5 2279 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2280 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2281
2282#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2283 ((adev)->pp_enabled ? \
e61710c5 2284 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2285 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2286
2287#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2288 ((adev)->pp_enabled ? \
e61710c5 2289 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2290 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2291
2292#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2293 ((adev)->pp_enabled ? \
e61710c5 2294 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2295 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2296
2297#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2298 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2299
2300#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2301 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2302
e61710c5 2303#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2304 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2305
2306#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2307
2308/* Common functions */
2309int amdgpu_gpu_reset(struct amdgpu_device *adev);
2310void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2311bool amdgpu_card_posted(struct amdgpu_device *adev);
2312void amdgpu_update_display_priority(struct amdgpu_device *adev);
2313bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82 2314
97b2e202
AD		 2315int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2316int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2317 u32 ip_instance, u32 ring,
2318 struct amdgpu_ring **out_ring);
2319void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2320bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2321int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2322 uint32_t flags);
2323bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2324bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2325uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2326 struct ttm_mem_reg *mem);
2327void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2328void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2329void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2330void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2331 const u32 *registers,
2332 const u32 array_size);
2333
2334bool amdgpu_device_is_px(struct drm_device *dev);
2335/* atpx handler */
2336#if defined(CONFIG_VGA_SWITCHEROO)
2337void amdgpu_register_atpx_handler(void);
2338void amdgpu_unregister_atpx_handler(void);
2339#else
2340static inline void amdgpu_register_atpx_handler(void) {}
2341static inline void amdgpu_unregister_atpx_handler(void) {}
2342#endif
2343
2344/*
2345 * KMS
2346 */
2347extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2348extern int amdgpu_max_kms_ioctl;
2349
2350int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2351int amdgpu_driver_unload_kms(struct drm_device *dev);
2352void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2353int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2354void amdgpu_driver_postclose_kms(struct drm_device *dev,
2355 struct drm_file *file_priv);
2356void amdgpu_driver_preclose_kms(struct drm_device *dev,
2357 struct drm_file *file_priv);
2358int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2359int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2360u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2361int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2362void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2363int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2364 int *max_error,
2365 struct timeval *vblank_time,
2366 unsigned flags);
2367long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2368 unsigned long arg);
2369
97b2e202
AD		 2370/*
2371 * functions used by amdgpu_encoder.c
2372 */
2373struct amdgpu_afmt_acr {
2374 u32 clock;
2375
2376 int n_32khz;
2377 int cts_32khz;
2378
2379 int n_44_1khz;
2380 int cts_44_1khz;
2381
2382 int n_48khz;
2383 int cts_48khz;
2384
2385};
2386
2387struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2388
2389/* amdgpu_acpi.c */
2390#if defined(CONFIG_ACPI)
2391int amdgpu_acpi_init(struct amdgpu_device *adev);
2392void amdgpu_acpi_fini(struct amdgpu_device *adev);
2393bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2394int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2395 u8 perf_req, bool advertise);
2396int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2397#else
2398static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2399static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2400#endif
2401
2402struct amdgpu_bo_va_mapping *
2403amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2404 uint64_t addr, struct amdgpu_bo **bo);
2405
2406#include "amdgpu_object.h"
2407
2408#endif
Linux kernel - Deliverables
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