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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/amdgpu_drm.h> | |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_atombios.h" | |
30 | #include "amdgpu_i2c.h" | |
31 | ||
32 | #include "atom.h" | |
33 | #include "atom-bits.h" | |
34 | #include "atombios_encoders.h" | |
35 | #include "bif/bif_4_1_d.h" | |
36 | ||
37 | static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, | |
38 | ATOM_GPIO_I2C_ASSIGMENT *gpio, | |
39 | u8 index) | |
40 | { | |
41 | ||
42 | } | |
43 | ||
44 | static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) | |
45 | { | |
46 | struct amdgpu_i2c_bus_rec i2c; | |
47 | ||
48 | memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); | |
49 | ||
50 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); | |
51 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); | |
52 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); | |
53 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); | |
54 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); | |
55 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); | |
56 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); | |
57 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); | |
58 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); | |
59 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); | |
60 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); | |
61 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); | |
62 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); | |
63 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); | |
64 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); | |
65 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); | |
66 | ||
67 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) | |
68 | i2c.hw_capable = true; | |
69 | else | |
70 | i2c.hw_capable = false; | |
71 | ||
72 | if (gpio->sucI2cId.ucAccess == 0xa0) | |
73 | i2c.mm_i2c = true; | |
74 | else | |
75 | i2c.mm_i2c = false; | |
76 | ||
77 | i2c.i2c_id = gpio->sucI2cId.ucAccess; | |
78 | ||
79 | if (i2c.mask_clk_reg) | |
80 | i2c.valid = true; | |
81 | else | |
82 | i2c.valid = false; | |
83 | ||
84 | return i2c; | |
85 | } | |
86 | ||
87 | struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, | |
88 | uint8_t id) | |
89 | { | |
90 | struct atom_context *ctx = adev->mode_info.atom_context; | |
91 | ATOM_GPIO_I2C_ASSIGMENT *gpio; | |
92 | struct amdgpu_i2c_bus_rec i2c; | |
93 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
94 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
95 | uint16_t data_offset, size; | |
96 | int i, num_indices; | |
97 | ||
98 | memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); | |
99 | i2c.valid = false; | |
100 | ||
101 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
102 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
103 | ||
104 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
105 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
106 | ||
107 | gpio = &i2c_info->asGPIO_Info[0]; | |
108 | for (i = 0; i < num_indices; i++) { | |
109 | ||
110 | amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); | |
111 | ||
112 | if (gpio->sucI2cId.ucAccess == id) { | |
113 | i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); | |
114 | break; | |
115 | } | |
116 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) | |
117 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
118 | } | |
119 | } | |
120 | ||
121 | return i2c; | |
122 | } | |
123 | ||
124 | void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) | |
125 | { | |
126 | struct atom_context *ctx = adev->mode_info.atom_context; | |
127 | ATOM_GPIO_I2C_ASSIGMENT *gpio; | |
128 | struct amdgpu_i2c_bus_rec i2c; | |
129 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
130 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
131 | uint16_t data_offset, size; | |
132 | int i, num_indices; | |
133 | char stmp[32]; | |
134 | ||
135 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
136 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
137 | ||
138 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
139 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); | |
140 | ||
141 | gpio = &i2c_info->asGPIO_Info[0]; | |
142 | for (i = 0; i < num_indices; i++) { | |
143 | amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); | |
144 | ||
145 | i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); | |
146 | ||
147 | if (i2c.valid) { | |
148 | sprintf(stmp, "0x%x", i2c.i2c_id); | |
149 | adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); | |
150 | } | |
151 | gpio = (ATOM_GPIO_I2C_ASSIGMENT *) | |
152 | ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); | |
153 | } | |
154 | } | |
155 | } | |
156 | ||
157 | struct amdgpu_gpio_rec | |
158 | amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, | |
159 | u8 id) | |
160 | { | |
161 | struct atom_context *ctx = adev->mode_info.atom_context; | |
162 | struct amdgpu_gpio_rec gpio; | |
163 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); | |
164 | struct _ATOM_GPIO_PIN_LUT *gpio_info; | |
165 | ATOM_GPIO_PIN_ASSIGNMENT *pin; | |
166 | u16 data_offset, size; | |
167 | int i, num_indices; | |
168 | ||
169 | memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); | |
170 | gpio.valid = false; | |
171 | ||
172 | if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { | |
173 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); | |
174 | ||
175 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
176 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); | |
177 | ||
178 | pin = gpio_info->asGPIO_Pin; | |
179 | for (i = 0; i < num_indices; i++) { | |
180 | if (id == pin->ucGPIO_ID) { | |
181 | gpio.id = pin->ucGPIO_ID; | |
182 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); | |
183 | gpio.shift = pin->ucGpioPinBitShift; | |
184 | gpio.mask = (1 << pin->ucGpioPinBitShift); | |
185 | gpio.valid = true; | |
186 | break; | |
187 | } | |
188 | pin = (ATOM_GPIO_PIN_ASSIGNMENT *) | |
189 | ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); | |
190 | } | |
191 | } | |
192 | ||
193 | return gpio; | |
194 | } | |
195 | ||
196 | static struct amdgpu_hpd | |
197 | amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, | |
198 | struct amdgpu_gpio_rec *gpio) | |
199 | { | |
200 | struct amdgpu_hpd hpd; | |
201 | u32 reg; | |
202 | ||
203 | memset(&hpd, 0, sizeof(struct amdgpu_hpd)); | |
204 | ||
205 | reg = amdgpu_display_hpd_get_gpio_reg(adev); | |
206 | ||
207 | hpd.gpio = *gpio; | |
208 | if (gpio->reg == reg) { | |
209 | switch(gpio->mask) { | |
210 | case (1 << 0): | |
211 | hpd.hpd = AMDGPU_HPD_1; | |
212 | break; | |
213 | case (1 << 8): | |
214 | hpd.hpd = AMDGPU_HPD_2; | |
215 | break; | |
216 | case (1 << 16): | |
217 | hpd.hpd = AMDGPU_HPD_3; | |
218 | break; | |
219 | case (1 << 24): | |
220 | hpd.hpd = AMDGPU_HPD_4; | |
221 | break; | |
222 | case (1 << 26): | |
223 | hpd.hpd = AMDGPU_HPD_5; | |
224 | break; | |
225 | case (1 << 28): | |
226 | hpd.hpd = AMDGPU_HPD_6; | |
227 | break; | |
228 | default: | |
229 | hpd.hpd = AMDGPU_HPD_NONE; | |
230 | break; | |
231 | } | |
232 | } else | |
233 | hpd.hpd = AMDGPU_HPD_NONE; | |
234 | return hpd; | |
235 | } | |
236 | ||
d38ceaf9 AD |
237 | static const int object_connector_convert[] = { |
238 | DRM_MODE_CONNECTOR_Unknown, | |
239 | DRM_MODE_CONNECTOR_DVII, | |
240 | DRM_MODE_CONNECTOR_DVII, | |
241 | DRM_MODE_CONNECTOR_DVID, | |
242 | DRM_MODE_CONNECTOR_DVID, | |
243 | DRM_MODE_CONNECTOR_VGA, | |
244 | DRM_MODE_CONNECTOR_Composite, | |
245 | DRM_MODE_CONNECTOR_SVIDEO, | |
246 | DRM_MODE_CONNECTOR_Unknown, | |
247 | DRM_MODE_CONNECTOR_Unknown, | |
248 | DRM_MODE_CONNECTOR_9PinDIN, | |
249 | DRM_MODE_CONNECTOR_Unknown, | |
250 | DRM_MODE_CONNECTOR_HDMIA, | |
251 | DRM_MODE_CONNECTOR_HDMIB, | |
252 | DRM_MODE_CONNECTOR_LVDS, | |
253 | DRM_MODE_CONNECTOR_9PinDIN, | |
254 | DRM_MODE_CONNECTOR_Unknown, | |
255 | DRM_MODE_CONNECTOR_Unknown, | |
256 | DRM_MODE_CONNECTOR_Unknown, | |
257 | DRM_MODE_CONNECTOR_DisplayPort, | |
258 | DRM_MODE_CONNECTOR_eDP, | |
259 | DRM_MODE_CONNECTOR_Unknown | |
260 | }; | |
261 | ||
262 | bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) | |
263 | { | |
264 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
265 | struct atom_context *ctx = mode_info->atom_context; | |
266 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
267 | u16 size, data_offset; | |
268 | u8 frev, crev; | |
269 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; | |
270 | ATOM_ENCODER_OBJECT_TABLE *enc_obj; | |
271 | ATOM_OBJECT_TABLE *router_obj; | |
272 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; | |
273 | ATOM_OBJECT_HEADER *obj_header; | |
274 | int i, j, k, path_size, device_support; | |
275 | int connector_type; | |
276 | u16 conn_id, connector_object_id; | |
277 | struct amdgpu_i2c_bus_rec ddc_bus; | |
278 | struct amdgpu_router router; | |
279 | struct amdgpu_gpio_rec gpio; | |
280 | struct amdgpu_hpd hpd; | |
281 | ||
282 | if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) | |
283 | return false; | |
284 | ||
285 | if (crev < 2) | |
286 | return false; | |
287 | ||
288 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
289 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
290 | (ctx->bios + data_offset + | |
291 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
292 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) | |
293 | (ctx->bios + data_offset + | |
294 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); | |
295 | enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) | |
296 | (ctx->bios + data_offset + | |
297 | le16_to_cpu(obj_header->usEncoderObjectTableOffset)); | |
298 | router_obj = (ATOM_OBJECT_TABLE *) | |
299 | (ctx->bios + data_offset + | |
300 | le16_to_cpu(obj_header->usRouterObjectTableOffset)); | |
301 | device_support = le16_to_cpu(obj_header->usDeviceSupport); | |
302 | ||
303 | path_size = 0; | |
304 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { | |
305 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; | |
306 | ATOM_DISPLAY_OBJECT_PATH *path; | |
307 | addr += path_size; | |
308 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; | |
309 | path_size += le16_to_cpu(path->usSize); | |
310 | ||
311 | if (device_support & le16_to_cpu(path->usDeviceTag)) { | |
312 | uint8_t con_obj_id, con_obj_num, con_obj_type; | |
313 | ||
314 | con_obj_id = | |
315 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) | |
316 | >> OBJECT_ID_SHIFT; | |
317 | con_obj_num = | |
318 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) | |
319 | >> ENUM_ID_SHIFT; | |
320 | con_obj_type = | |
321 | (le16_to_cpu(path->usConnObjectId) & | |
322 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
323 | ||
611a1507 AD |
324 | /* Skip TV/CV support */ |
325 | if ((le16_to_cpu(path->usDeviceTag) == | |
326 | ATOM_DEVICE_TV1_SUPPORT) || | |
327 | (le16_to_cpu(path->usDeviceTag) == | |
328 | ATOM_DEVICE_CV_SUPPORT)) | |
329 | continue; | |
330 | ||
e1718d97 AD |
331 | if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { |
332 | DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", | |
333 | con_obj_id, le16_to_cpu(path->usDeviceTag)); | |
334 | continue; | |
335 | } | |
336 | ||
d38ceaf9 AD |
337 | connector_type = |
338 | object_connector_convert[con_obj_id]; | |
339 | connector_object_id = con_obj_id; | |
340 | ||
341 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | |
342 | continue; | |
343 | ||
344 | router.ddc_valid = false; | |
345 | router.cd_valid = false; | |
346 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { | |
347 | uint8_t grph_obj_id, grph_obj_num, grph_obj_type; | |
348 | ||
349 | grph_obj_id = | |
350 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
351 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
352 | grph_obj_num = | |
353 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
354 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
355 | grph_obj_type = | |
356 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
357 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
358 | ||
359 | if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { | |
360 | for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { | |
361 | u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); | |
362 | if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { | |
363 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
364 | (ctx->bios + data_offset + | |
365 | le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); | |
366 | ATOM_ENCODER_CAP_RECORD *cap_record; | |
367 | u16 caps = 0; | |
368 | ||
369 | while (record->ucRecordSize > 0 && | |
370 | record->ucRecordType > 0 && | |
371 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
372 | switch (record->ucRecordType) { | |
373 | case ATOM_ENCODER_CAP_RECORD_TYPE: | |
374 | cap_record =(ATOM_ENCODER_CAP_RECORD *) | |
375 | record; | |
376 | caps = le16_to_cpu(cap_record->usEncoderCap); | |
377 | break; | |
378 | } | |
379 | record = (ATOM_COMMON_RECORD_HEADER *) | |
380 | ((char *)record + record->ucRecordSize); | |
381 | } | |
382 | amdgpu_display_add_encoder(adev, encoder_obj, | |
383 | le16_to_cpu(path->usDeviceTag), | |
384 | caps); | |
385 | } | |
386 | } | |
387 | } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { | |
388 | for (k = 0; k < router_obj->ucNumberOfObjects; k++) { | |
389 | u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); | |
390 | if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { | |
391 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) | |
392 | (ctx->bios + data_offset + | |
393 | le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); | |
394 | ATOM_I2C_RECORD *i2c_record; | |
395 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; | |
396 | ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; | |
397 | ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; | |
398 | ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = | |
399 | (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) | |
400 | (ctx->bios + data_offset + | |
401 | le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); | |
402 | u8 *num_dst_objs = (u8 *) | |
403 | ((u8 *)router_src_dst_table + 1 + | |
404 | (router_src_dst_table->ucNumberOfSrc * 2)); | |
405 | u16 *dst_objs = (u16 *)(num_dst_objs + 1); | |
406 | int enum_id; | |
407 | ||
408 | router.router_id = router_obj_id; | |
409 | for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { | |
410 | if (le16_to_cpu(path->usConnObjectId) == | |
411 | le16_to_cpu(dst_objs[enum_id])) | |
412 | break; | |
413 | } | |
414 | ||
415 | while (record->ucRecordSize > 0 && | |
416 | record->ucRecordType > 0 && | |
417 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
418 | switch (record->ucRecordType) { | |
419 | case ATOM_I2C_RECORD_TYPE: | |
420 | i2c_record = | |
421 | (ATOM_I2C_RECORD *) | |
422 | record; | |
423 | i2c_config = | |
424 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
425 | &i2c_record->sucI2cId; | |
426 | router.i2c_info = | |
427 | amdgpu_atombios_lookup_i2c_gpio(adev, | |
428 | i2c_config-> | |
429 | ucAccess); | |
430 | router.i2c_addr = i2c_record->ucI2CAddr >> 1; | |
431 | break; | |
432 | case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: | |
433 | ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) | |
434 | record; | |
435 | router.ddc_valid = true; | |
436 | router.ddc_mux_type = ddc_path->ucMuxType; | |
437 | router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; | |
438 | router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; | |
439 | break; | |
440 | case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: | |
441 | cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) | |
442 | record; | |
443 | router.cd_valid = true; | |
444 | router.cd_mux_type = cd_path->ucMuxType; | |
445 | router.cd_mux_control_pin = cd_path->ucMuxControlPin; | |
446 | router.cd_mux_state = cd_path->ucMuxState[enum_id]; | |
447 | break; | |
448 | } | |
449 | record = (ATOM_COMMON_RECORD_HEADER *) | |
450 | ((char *)record + record->ucRecordSize); | |
451 | } | |
452 | } | |
453 | } | |
454 | } | |
455 | } | |
456 | ||
457 | /* look up gpio for ddc, hpd */ | |
458 | ddc_bus.valid = false; | |
459 | hpd.hpd = AMDGPU_HPD_NONE; | |
460 | if ((le16_to_cpu(path->usDeviceTag) & | |
461 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { | |
462 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { | |
463 | if (le16_to_cpu(path->usConnObjectId) == | |
464 | le16_to_cpu(con_obj->asObjects[j]. | |
465 | usObjectID)) { | |
466 | ATOM_COMMON_RECORD_HEADER | |
467 | *record = | |
468 | (ATOM_COMMON_RECORD_HEADER | |
469 | *) | |
470 | (ctx->bios + data_offset + | |
471 | le16_to_cpu(con_obj-> | |
472 | asObjects[j]. | |
473 | usRecordOffset)); | |
474 | ATOM_I2C_RECORD *i2c_record; | |
475 | ATOM_HPD_INT_RECORD *hpd_record; | |
476 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; | |
477 | ||
478 | while (record->ucRecordSize > 0 && | |
479 | record->ucRecordType > 0 && | |
480 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
481 | switch (record->ucRecordType) { | |
482 | case ATOM_I2C_RECORD_TYPE: | |
483 | i2c_record = | |
484 | (ATOM_I2C_RECORD *) | |
485 | record; | |
486 | i2c_config = | |
487 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
488 | &i2c_record->sucI2cId; | |
489 | ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, | |
490 | i2c_config-> | |
491 | ucAccess); | |
492 | break; | |
493 | case ATOM_HPD_INT_RECORD_TYPE: | |
494 | hpd_record = | |
495 | (ATOM_HPD_INT_RECORD *) | |
496 | record; | |
497 | gpio = amdgpu_atombios_lookup_gpio(adev, | |
498 | hpd_record->ucHPDIntGPIOID); | |
499 | hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); | |
500 | hpd.plugged_state = hpd_record->ucPlugged_PinState; | |
501 | break; | |
502 | } | |
503 | record = | |
504 | (ATOM_COMMON_RECORD_HEADER | |
505 | *) ((char *)record | |
506 | + | |
507 | record-> | |
508 | ucRecordSize); | |
509 | } | |
510 | break; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /* needed for aux chan transactions */ | |
516 | ddc_bus.hpd = hpd.hpd; | |
517 | ||
518 | conn_id = le16_to_cpu(path->usConnObjectId); | |
519 | ||
d38ceaf9 AD |
520 | amdgpu_display_add_connector(adev, |
521 | conn_id, | |
522 | le16_to_cpu(path->usDeviceTag), | |
523 | connector_type, &ddc_bus, | |
524 | connector_object_id, | |
525 | &hpd, | |
526 | &router); | |
527 | ||
528 | } | |
529 | } | |
530 | ||
531 | amdgpu_link_encoder_connector(adev->ddev); | |
532 | ||
533 | return true; | |
534 | } | |
535 | ||
536 | union firmware_info { | |
537 | ATOM_FIRMWARE_INFO info; | |
538 | ATOM_FIRMWARE_INFO_V1_2 info_12; | |
539 | ATOM_FIRMWARE_INFO_V1_3 info_13; | |
540 | ATOM_FIRMWARE_INFO_V1_4 info_14; | |
541 | ATOM_FIRMWARE_INFO_V2_1 info_21; | |
542 | ATOM_FIRMWARE_INFO_V2_2 info_22; | |
543 | }; | |
544 | ||
545 | int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) | |
546 | { | |
547 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
548 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
549 | uint8_t frev, crev; | |
550 | uint16_t data_offset; | |
551 | int ret = -EINVAL; | |
552 | ||
553 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
554 | &frev, &crev, &data_offset)) { | |
555 | int i; | |
556 | struct amdgpu_pll *ppll = &adev->clock.ppll[0]; | |
557 | struct amdgpu_pll *spll = &adev->clock.spll; | |
558 | struct amdgpu_pll *mpll = &adev->clock.mpll; | |
559 | union firmware_info *firmware_info = | |
560 | (union firmware_info *)(mode_info->atom_context->bios + | |
561 | data_offset); | |
562 | /* pixel clocks */ | |
563 | ppll->reference_freq = | |
564 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
565 | ppll->reference_div = 0; | |
566 | ||
a8a04c99 AD |
567 | ppll->pll_out_min = |
568 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); | |
d38ceaf9 AD |
569 | ppll->pll_out_max = |
570 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); | |
571 | ||
a8a04c99 AD |
572 | ppll->lcd_pll_out_min = |
573 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; | |
574 | if (ppll->lcd_pll_out_min == 0) | |
d38ceaf9 | 575 | ppll->lcd_pll_out_min = ppll->pll_out_min; |
a8a04c99 AD |
576 | ppll->lcd_pll_out_max = |
577 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; | |
578 | if (ppll->lcd_pll_out_max == 0) | |
d38ceaf9 | 579 | ppll->lcd_pll_out_max = ppll->pll_out_max; |
d38ceaf9 AD |
580 | |
581 | if (ppll->pll_out_min == 0) | |
582 | ppll->pll_out_min = 64800; | |
583 | ||
584 | ppll->pll_in_min = | |
585 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); | |
586 | ppll->pll_in_max = | |
587 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); | |
588 | ||
589 | ppll->min_post_div = 2; | |
590 | ppll->max_post_div = 0x7f; | |
591 | ppll->min_frac_feedback_div = 0; | |
592 | ppll->max_frac_feedback_div = 9; | |
593 | ppll->min_ref_div = 2; | |
594 | ppll->max_ref_div = 0x3ff; | |
595 | ppll->min_feedback_div = 4; | |
596 | ppll->max_feedback_div = 0xfff; | |
597 | ppll->best_vco = 0; | |
598 | ||
599 | for (i = 1; i < AMDGPU_MAX_PPLL; i++) | |
600 | adev->clock.ppll[i] = *ppll; | |
601 | ||
602 | /* system clock */ | |
603 | spll->reference_freq = | |
604 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); | |
605 | spll->reference_div = 0; | |
606 | ||
607 | spll->pll_out_min = | |
608 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); | |
609 | spll->pll_out_max = | |
610 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); | |
611 | ||
612 | /* ??? */ | |
613 | if (spll->pll_out_min == 0) | |
614 | spll->pll_out_min = 64800; | |
615 | ||
616 | spll->pll_in_min = | |
617 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); | |
618 | spll->pll_in_max = | |
619 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | |
620 | ||
621 | spll->min_post_div = 1; | |
622 | spll->max_post_div = 1; | |
623 | spll->min_ref_div = 2; | |
624 | spll->max_ref_div = 0xff; | |
625 | spll->min_feedback_div = 4; | |
626 | spll->max_feedback_div = 0xff; | |
627 | spll->best_vco = 0; | |
628 | ||
629 | /* memory clock */ | |
630 | mpll->reference_freq = | |
631 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); | |
632 | mpll->reference_div = 0; | |
633 | ||
634 | mpll->pll_out_min = | |
635 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); | |
636 | mpll->pll_out_max = | |
637 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); | |
638 | ||
639 | /* ??? */ | |
640 | if (mpll->pll_out_min == 0) | |
641 | mpll->pll_out_min = 64800; | |
642 | ||
643 | mpll->pll_in_min = | |
644 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); | |
645 | mpll->pll_in_max = | |
646 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); | |
647 | ||
648 | adev->clock.default_sclk = | |
649 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); | |
650 | adev->clock.default_mclk = | |
651 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); | |
652 | ||
653 | mpll->min_post_div = 1; | |
654 | mpll->max_post_div = 1; | |
655 | mpll->min_ref_div = 2; | |
656 | mpll->max_ref_div = 0xff; | |
657 | mpll->min_feedback_div = 4; | |
658 | mpll->max_feedback_div = 0xff; | |
659 | mpll->best_vco = 0; | |
660 | ||
661 | /* disp clock */ | |
662 | adev->clock.default_dispclk = | |
663 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); | |
80c083c5 AD |
664 | /* set a reasonable default for DP */ |
665 | if (adev->clock.default_dispclk < 53900) { | |
666 | DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", | |
667 | adev->clock.default_dispclk / 100); | |
668 | adev->clock.default_dispclk = 60000; | |
669 | } | |
d38ceaf9 AD |
670 | adev->clock.dp_extclk = |
671 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); | |
672 | adev->clock.current_dispclk = adev->clock.default_dispclk; | |
673 | ||
674 | adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); | |
675 | if (adev->clock.max_pixel_clock == 0) | |
676 | adev->clock.max_pixel_clock = 40000; | |
677 | ||
678 | /* not technically a clock, but... */ | |
679 | adev->mode_info.firmware_flags = | |
680 | le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); | |
681 | ||
682 | ret = 0; | |
683 | } | |
684 | ||
685 | adev->pm.current_sclk = adev->clock.default_sclk; | |
686 | adev->pm.current_mclk = adev->clock.default_mclk; | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
397a270e AD |
691 | union gfx_info { |
692 | ATOM_GFX_INFO_V2_1 info; | |
693 | }; | |
694 | ||
695 | int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) | |
696 | { | |
697 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
698 | int index = GetIndexIntoMasterTable(DATA, GFX_Info); | |
699 | uint8_t frev, crev; | |
700 | uint16_t data_offset; | |
701 | int ret = -EINVAL; | |
702 | ||
703 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
704 | &frev, &crev, &data_offset)) { | |
705 | union gfx_info *gfx_info = (union gfx_info *) | |
706 | (mode_info->atom_context->bios + data_offset); | |
707 | ||
708 | adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; | |
709 | adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; | |
710 | adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; | |
711 | adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; | |
712 | adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; | |
713 | adev->gfx.config.max_texture_channel_caches = | |
714 | gfx_info->info.max_texture_channel_caches; | |
715 | ||
716 | ret = 0; | |
717 | } | |
718 | return ret; | |
719 | } | |
720 | ||
d38ceaf9 AD |
721 | union igp_info { |
722 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
723 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
724 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; | |
725 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; | |
726 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; | |
727 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; | |
728 | }; | |
729 | ||
730 | static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, | |
731 | struct amdgpu_atom_ss *ss, | |
732 | int id) | |
733 | { | |
734 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
735 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
736 | u16 data_offset, size; | |
737 | union igp_info *igp_info; | |
738 | u8 frev, crev; | |
739 | u16 percentage = 0, rate = 0; | |
740 | ||
741 | /* get any igp specific overrides */ | |
742 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, | |
743 | &frev, &crev, &data_offset)) { | |
744 | igp_info = (union igp_info *) | |
745 | (mode_info->atom_context->bios + data_offset); | |
746 | switch (crev) { | |
747 | case 6: | |
748 | switch (id) { | |
749 | case ASIC_INTERNAL_SS_ON_TMDS: | |
750 | percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); | |
751 | rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); | |
752 | break; | |
753 | case ASIC_INTERNAL_SS_ON_HDMI: | |
754 | percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); | |
755 | rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); | |
756 | break; | |
757 | case ASIC_INTERNAL_SS_ON_LVDS: | |
758 | percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); | |
759 | rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); | |
760 | break; | |
761 | } | |
762 | break; | |
763 | case 7: | |
764 | switch (id) { | |
765 | case ASIC_INTERNAL_SS_ON_TMDS: | |
766 | percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); | |
767 | rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); | |
768 | break; | |
769 | case ASIC_INTERNAL_SS_ON_HDMI: | |
770 | percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); | |
771 | rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); | |
772 | break; | |
773 | case ASIC_INTERNAL_SS_ON_LVDS: | |
774 | percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); | |
775 | rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); | |
776 | break; | |
777 | } | |
778 | break; | |
779 | case 8: | |
780 | switch (id) { | |
781 | case ASIC_INTERNAL_SS_ON_TMDS: | |
782 | percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); | |
783 | rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); | |
784 | break; | |
785 | case ASIC_INTERNAL_SS_ON_HDMI: | |
786 | percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); | |
787 | rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); | |
788 | break; | |
789 | case ASIC_INTERNAL_SS_ON_LVDS: | |
790 | percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); | |
791 | rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); | |
792 | break; | |
793 | } | |
794 | break; | |
795 | case 9: | |
796 | switch (id) { | |
797 | case ASIC_INTERNAL_SS_ON_TMDS: | |
798 | percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); | |
799 | rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); | |
800 | break; | |
801 | case ASIC_INTERNAL_SS_ON_HDMI: | |
802 | percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); | |
803 | rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); | |
804 | break; | |
805 | case ASIC_INTERNAL_SS_ON_LVDS: | |
806 | percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); | |
807 | rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); | |
808 | break; | |
809 | } | |
810 | break; | |
811 | default: | |
812 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
813 | break; | |
814 | } | |
815 | if (percentage) | |
816 | ss->percentage = percentage; | |
817 | if (rate) | |
818 | ss->rate = rate; | |
819 | } | |
820 | } | |
821 | ||
822 | union asic_ss_info { | |
823 | struct _ATOM_ASIC_INTERNAL_SS_INFO info; | |
824 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; | |
825 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; | |
826 | }; | |
827 | ||
828 | union asic_ss_assignment { | |
829 | struct _ATOM_ASIC_SS_ASSIGNMENT v1; | |
830 | struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; | |
831 | struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; | |
832 | }; | |
833 | ||
834 | bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, | |
835 | struct amdgpu_atom_ss *ss, | |
836 | int id, u32 clock) | |
837 | { | |
838 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
839 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); | |
840 | uint16_t data_offset, size; | |
841 | union asic_ss_info *ss_info; | |
842 | union asic_ss_assignment *ss_assign; | |
843 | uint8_t frev, crev; | |
844 | int i, num_indices; | |
845 | ||
846 | if (id == ASIC_INTERNAL_MEMORY_SS) { | |
847 | if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) | |
848 | return false; | |
849 | } | |
850 | if (id == ASIC_INTERNAL_ENGINE_SS) { | |
851 | if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) | |
852 | return false; | |
853 | } | |
854 | ||
855 | memset(ss, 0, sizeof(struct amdgpu_atom_ss)); | |
856 | if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, | |
857 | &frev, &crev, &data_offset)) { | |
858 | ||
859 | ss_info = | |
860 | (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); | |
861 | ||
862 | switch (frev) { | |
863 | case 1: | |
864 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
865 | sizeof(ATOM_ASIC_SS_ASSIGNMENT); | |
866 | ||
867 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); | |
868 | for (i = 0; i < num_indices; i++) { | |
869 | if ((ss_assign->v1.ucClockIndication == id) && | |
870 | (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { | |
871 | ss->percentage = | |
872 | le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); | |
873 | ss->type = ss_assign->v1.ucSpreadSpectrumMode; | |
874 | ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); | |
875 | ss->percentage_divider = 100; | |
876 | return true; | |
877 | } | |
878 | ss_assign = (union asic_ss_assignment *) | |
879 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); | |
880 | } | |
881 | break; | |
882 | case 2: | |
883 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
884 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); | |
885 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); | |
886 | for (i = 0; i < num_indices; i++) { | |
887 | if ((ss_assign->v2.ucClockIndication == id) && | |
888 | (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { | |
889 | ss->percentage = | |
890 | le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); | |
891 | ss->type = ss_assign->v2.ucSpreadSpectrumMode; | |
892 | ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); | |
893 | ss->percentage_divider = 100; | |
894 | if ((crev == 2) && | |
895 | ((id == ASIC_INTERNAL_ENGINE_SS) || | |
896 | (id == ASIC_INTERNAL_MEMORY_SS))) | |
897 | ss->rate /= 100; | |
898 | return true; | |
899 | } | |
900 | ss_assign = (union asic_ss_assignment *) | |
901 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); | |
902 | } | |
903 | break; | |
904 | case 3: | |
905 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / | |
906 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); | |
907 | ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); | |
908 | for (i = 0; i < num_indices; i++) { | |
909 | if ((ss_assign->v3.ucClockIndication == id) && | |
910 | (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { | |
911 | ss->percentage = | |
912 | le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); | |
913 | ss->type = ss_assign->v3.ucSpreadSpectrumMode; | |
914 | ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); | |
915 | if (ss_assign->v3.ucSpreadSpectrumMode & | |
916 | SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) | |
917 | ss->percentage_divider = 1000; | |
918 | else | |
919 | ss->percentage_divider = 100; | |
920 | if ((id == ASIC_INTERNAL_ENGINE_SS) || | |
921 | (id == ASIC_INTERNAL_MEMORY_SS)) | |
922 | ss->rate /= 100; | |
2f7d10b3 | 923 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
924 | amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); |
925 | return true; | |
926 | } | |
927 | ss_assign = (union asic_ss_assignment *) | |
928 | ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); | |
929 | } | |
930 | break; | |
931 | default: | |
932 | DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); | |
933 | break; | |
934 | } | |
935 | ||
936 | } | |
937 | return false; | |
938 | } | |
939 | ||
940 | union get_clock_dividers { | |
941 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; | |
942 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; | |
943 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; | |
944 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; | |
945 | struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; | |
946 | struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; | |
947 | struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; | |
948 | }; | |
949 | ||
950 | int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, | |
951 | u8 clock_type, | |
952 | u32 clock, | |
953 | bool strobe_mode, | |
954 | struct atom_clock_dividers *dividers) | |
955 | { | |
956 | union get_clock_dividers args; | |
957 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); | |
958 | u8 frev, crev; | |
959 | ||
960 | memset(&args, 0, sizeof(args)); | |
961 | memset(dividers, 0, sizeof(struct atom_clock_dividers)); | |
962 | ||
963 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
964 | return -EINVAL; | |
965 | ||
966 | switch (crev) { | |
967 | case 4: | |
968 | /* fusion */ | |
969 | args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
970 | ||
971 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
972 | ||
973 | dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; | |
974 | dividers->real_clock = le32_to_cpu(args.v4.ulClock); | |
975 | break; | |
976 | case 6: | |
977 | /* CI */ | |
978 | /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ | |
979 | args.v6_in.ulClock.ulComputeClockFlag = clock_type; | |
980 | args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ | |
981 | ||
982 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
983 | ||
984 | dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); | |
985 | dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); | |
986 | dividers->ref_div = args.v6_out.ucPllRefDiv; | |
987 | dividers->post_div = args.v6_out.ucPllPostDiv; | |
988 | dividers->flags = args.v6_out.ucPllCntlFlag; | |
989 | dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); | |
990 | dividers->post_divider = args.v6_out.ulClock.ucPostDiv; | |
991 | break; | |
992 | default: | |
993 | return -EINVAL; | |
994 | } | |
995 | return 0; | |
996 | } | |
997 | ||
998 | int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, | |
999 | u32 clock, | |
1000 | bool strobe_mode, | |
1001 | struct atom_mpll_param *mpll_param) | |
1002 | { | |
1003 | COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; | |
1004 | int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); | |
1005 | u8 frev, crev; | |
1006 | ||
1007 | memset(&args, 0, sizeof(args)); | |
1008 | memset(mpll_param, 0, sizeof(struct atom_mpll_param)); | |
1009 | ||
1010 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1011 | return -EINVAL; | |
1012 | ||
1013 | switch (frev) { | |
1014 | case 2: | |
1015 | switch (crev) { | |
1016 | case 1: | |
1017 | /* SI */ | |
1018 | args.ulClock = cpu_to_le32(clock); /* 10 khz */ | |
1019 | args.ucInputFlag = 0; | |
1020 | if (strobe_mode) | |
1021 | args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; | |
1022 | ||
1023 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1024 | ||
1025 | mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); | |
1026 | mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); | |
1027 | mpll_param->post_div = args.ucPostDiv; | |
1028 | mpll_param->dll_speed = args.ucDllSpeed; | |
1029 | mpll_param->bwcntl = args.ucBWCntl; | |
1030 | mpll_param->vco_mode = | |
1031 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); | |
1032 | mpll_param->yclk_sel = | |
1033 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; | |
1034 | mpll_param->qdr = | |
1035 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; | |
1036 | mpll_param->half_rate = | |
1037 | (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; | |
1038 | break; | |
1039 | default: | |
1040 | return -EINVAL; | |
1041 | } | |
1042 | break; | |
1043 | default: | |
1044 | return -EINVAL; | |
1045 | } | |
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) | |
1050 | { | |
1051 | GET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1052 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); | |
1053 | ||
1054 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1055 | return le32_to_cpu(args.ulReturnEngineClock); | |
1056 | } | |
1057 | ||
1058 | uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) | |
1059 | { | |
1060 | GET_MEMORY_CLOCK_PS_ALLOCATION args; | |
1061 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); | |
1062 | ||
1063 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1064 | return le32_to_cpu(args.ulReturnMemoryClock); | |
1065 | } | |
1066 | ||
1067 | void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, | |
1068 | uint32_t eng_clock) | |
1069 | { | |
1070 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1071 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); | |
1072 | ||
1073 | args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ | |
1074 | ||
1075 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1076 | } | |
1077 | ||
1078 | void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, | |
1079 | uint32_t mem_clock) | |
1080 | { | |
1081 | SET_MEMORY_CLOCK_PS_ALLOCATION args; | |
1082 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); | |
1083 | ||
2f7d10b3 | 1084 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
1085 | return; |
1086 | ||
1087 | args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ | |
1088 | ||
1089 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1090 | } | |
1091 | ||
1092 | void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, | |
1093 | u32 eng_clock, u32 mem_clock) | |
1094 | { | |
1095 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1096 | int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); | |
1097 | u32 tmp; | |
1098 | ||
1099 | memset(&args, 0, sizeof(args)); | |
1100 | ||
1101 | tmp = eng_clock & SET_CLOCK_FREQ_MASK; | |
1102 | tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); | |
1103 | ||
1104 | args.ulTargetEngineClock = cpu_to_le32(tmp); | |
1105 | if (mem_clock) | |
1106 | args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); | |
1107 | ||
1108 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1109 | } | |
1110 | ||
1111 | union set_voltage { | |
1112 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; | |
1113 | struct _SET_VOLTAGE_PARAMETERS v1; | |
1114 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; | |
1115 | struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; | |
1116 | }; | |
1117 | ||
1118 | void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, | |
1119 | u16 voltage_level, | |
1120 | u8 voltage_type) | |
1121 | { | |
1122 | union set_voltage args; | |
1123 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
1124 | u8 frev, crev, volt_index = voltage_level; | |
1125 | ||
1126 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1127 | return; | |
1128 | ||
1129 | /* 0xff01 is a flag rather then an actual voltage */ | |
1130 | if (voltage_level == 0xff01) | |
1131 | return; | |
1132 | ||
1133 | switch (crev) { | |
1134 | case 1: | |
1135 | args.v1.ucVoltageType = voltage_type; | |
1136 | args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; | |
1137 | args.v1.ucVoltageIndex = volt_index; | |
1138 | break; | |
1139 | case 2: | |
1140 | args.v2.ucVoltageType = voltage_type; | |
1141 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; | |
1142 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); | |
1143 | break; | |
1144 | case 3: | |
1145 | args.v3.ucVoltageType = voltage_type; | |
1146 | args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; | |
1147 | args.v3.usVoltageLevel = cpu_to_le16(voltage_level); | |
1148 | break; | |
1149 | default: | |
1150 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1151 | return; | |
1152 | } | |
1153 | ||
1154 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1155 | } | |
1156 | ||
1157 | int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, | |
1158 | u16 *leakage_id) | |
1159 | { | |
1160 | union set_voltage args; | |
1161 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); | |
1162 | u8 frev, crev; | |
1163 | ||
1164 | if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) | |
1165 | return -EINVAL; | |
1166 | ||
1167 | switch (crev) { | |
1168 | case 3: | |
1169 | case 4: | |
1170 | args.v3.ucVoltageType = 0; | |
1171 | args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; | |
1172 | args.v3.usVoltageLevel = 0; | |
1173 | ||
1174 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1175 | ||
1176 | *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); | |
1177 | break; | |
1178 | default: | |
1179 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1180 | return -EINVAL; | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, | |
1187 | u16 *vddc, u16 *vddci, | |
1188 | u16 virtual_voltage_id, | |
1189 | u16 vbios_voltage_id) | |
1190 | { | |
1191 | int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); | |
1192 | u8 frev, crev; | |
1193 | u16 data_offset, size; | |
1194 | int i, j; | |
1195 | ATOM_ASIC_PROFILING_INFO_V2_1 *profile; | |
1196 | u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; | |
1197 | ||
1198 | *vddc = 0; | |
1199 | *vddci = 0; | |
1200 | ||
1201 | if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1202 | &frev, &crev, &data_offset)) | |
1203 | return -EINVAL; | |
1204 | ||
1205 | profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) | |
1206 | (adev->mode_info.atom_context->bios + data_offset); | |
1207 | ||
1208 | switch (frev) { | |
1209 | case 1: | |
1210 | return -EINVAL; | |
1211 | case 2: | |
1212 | switch (crev) { | |
1213 | case 1: | |
1214 | if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) | |
1215 | return -EINVAL; | |
1216 | leakage_bin = (u16 *) | |
1217 | (adev->mode_info.atom_context->bios + data_offset + | |
1218 | le16_to_cpu(profile->usLeakageBinArrayOffset)); | |
1219 | vddc_id_buf = (u16 *) | |
1220 | (adev->mode_info.atom_context->bios + data_offset + | |
1221 | le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); | |
1222 | vddc_buf = (u16 *) | |
1223 | (adev->mode_info.atom_context->bios + data_offset + | |
1224 | le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); | |
1225 | vddci_id_buf = (u16 *) | |
1226 | (adev->mode_info.atom_context->bios + data_offset + | |
1227 | le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); | |
1228 | vddci_buf = (u16 *) | |
1229 | (adev->mode_info.atom_context->bios + data_offset + | |
1230 | le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); | |
1231 | ||
1232 | if (profile->ucElbVDDC_Num > 0) { | |
1233 | for (i = 0; i < profile->ucElbVDDC_Num; i++) { | |
1234 | if (vddc_id_buf[i] == virtual_voltage_id) { | |
1235 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
1236 | if (vbios_voltage_id <= leakage_bin[j]) { | |
1237 | *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; | |
1238 | break; | |
1239 | } | |
1240 | } | |
1241 | break; | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | if (profile->ucElbVDDCI_Num > 0) { | |
1246 | for (i = 0; i < profile->ucElbVDDCI_Num; i++) { | |
1247 | if (vddci_id_buf[i] == virtual_voltage_id) { | |
1248 | for (j = 0; j < profile->ucLeakageBinNum; j++) { | |
1249 | if (vbios_voltage_id <= leakage_bin[j]) { | |
1250 | *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | break; | |
1255 | } | |
1256 | } | |
1257 | } | |
1258 | break; | |
1259 | default: | |
1260 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1261 | return -EINVAL; | |
1262 | } | |
1263 | break; | |
1264 | default: | |
1265 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1266 | return -EINVAL; | |
1267 | } | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | union get_voltage_info { | |
1273 | struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; | |
1274 | struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; | |
1275 | }; | |
1276 | ||
1277 | int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, | |
1278 | u16 virtual_voltage_id, | |
1279 | u16 *voltage) | |
1280 | { | |
1281 | int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); | |
1282 | u32 entry_id; | |
1283 | u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; | |
1284 | union get_voltage_info args; | |
1285 | ||
1286 | for (entry_id = 0; entry_id < count; entry_id++) { | |
1287 | if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == | |
1288 | virtual_voltage_id) | |
1289 | break; | |
1290 | } | |
1291 | ||
1292 | if (entry_id >= count) | |
1293 | return -EINVAL; | |
1294 | ||
1295 | args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; | |
1296 | args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; | |
1297 | args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); | |
1298 | args.in.ulSCLKFreq = | |
1299 | cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); | |
1300 | ||
1301 | amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); | |
1302 | ||
1303 | *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | union voltage_object_info { | |
1309 | struct _ATOM_VOLTAGE_OBJECT_INFO v1; | |
1310 | struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; | |
1311 | struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; | |
1312 | }; | |
1313 | ||
1314 | union voltage_object { | |
1315 | struct _ATOM_VOLTAGE_OBJECT v1; | |
1316 | struct _ATOM_VOLTAGE_OBJECT_V2 v2; | |
1317 | union _ATOM_VOLTAGE_OBJECT_V3 v3; | |
1318 | }; | |
1319 | ||
1320 | ||
1321 | static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, | |
1322 | u8 voltage_type, u8 voltage_mode) | |
1323 | { | |
1324 | u32 size = le16_to_cpu(v3->sHeader.usStructureSize); | |
1325 | u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); | |
1326 | u8 *start = (u8*)v3; | |
1327 | ||
1328 | while (offset < size) { | |
1329 | ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); | |
1330 | if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && | |
1331 | (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) | |
1332 | return vo; | |
1333 | offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); | |
1334 | } | |
1335 | return NULL; | |
1336 | } | |
1337 | ||
1338 | bool | |
1339 | amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, | |
1340 | u8 voltage_type, u8 voltage_mode) | |
1341 | { | |
1342 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
1343 | u8 frev, crev; | |
1344 | u16 data_offset, size; | |
1345 | union voltage_object_info *voltage_info; | |
1346 | ||
1347 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1348 | &frev, &crev, &data_offset)) { | |
1349 | voltage_info = (union voltage_object_info *) | |
1350 | (adev->mode_info.atom_context->bios + data_offset); | |
1351 | ||
1352 | switch (frev) { | |
1353 | case 3: | |
1354 | switch (crev) { | |
1355 | case 1: | |
1356 | if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, | |
1357 | voltage_type, voltage_mode)) | |
1358 | return true; | |
1359 | break; | |
1360 | default: | |
1361 | DRM_ERROR("unknown voltage object table\n"); | |
1362 | return false; | |
1363 | } | |
1364 | break; | |
1365 | default: | |
1366 | DRM_ERROR("unknown voltage object table\n"); | |
1367 | return false; | |
1368 | } | |
1369 | ||
1370 | } | |
1371 | return false; | |
1372 | } | |
1373 | ||
1374 | int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, | |
1375 | u8 voltage_type, u8 voltage_mode, | |
1376 | struct atom_voltage_table *voltage_table) | |
1377 | { | |
1378 | int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); | |
1379 | u8 frev, crev; | |
1380 | u16 data_offset, size; | |
1381 | int i; | |
1382 | union voltage_object_info *voltage_info; | |
1383 | union voltage_object *voltage_object = NULL; | |
1384 | ||
1385 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1386 | &frev, &crev, &data_offset)) { | |
1387 | voltage_info = (union voltage_object_info *) | |
1388 | (adev->mode_info.atom_context->bios + data_offset); | |
1389 | ||
1390 | switch (frev) { | |
1391 | case 3: | |
1392 | switch (crev) { | |
1393 | case 1: | |
1394 | voltage_object = (union voltage_object *) | |
1395 | amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, | |
1396 | voltage_type, voltage_mode); | |
1397 | if (voltage_object) { | |
1398 | ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = | |
1399 | &voltage_object->v3.asGpioVoltageObj; | |
1400 | VOLTAGE_LUT_ENTRY_V2 *lut; | |
1401 | if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) | |
1402 | return -EINVAL; | |
1403 | lut = &gpio->asVolGpioLut[0]; | |
1404 | for (i = 0; i < gpio->ucGpioEntryNum; i++) { | |
1405 | voltage_table->entries[i].value = | |
1406 | le16_to_cpu(lut->usVoltageValue); | |
1407 | voltage_table->entries[i].smio_low = | |
1408 | le32_to_cpu(lut->ulVoltageId); | |
1409 | lut = (VOLTAGE_LUT_ENTRY_V2 *) | |
1410 | ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); | |
1411 | } | |
1412 | voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); | |
1413 | voltage_table->count = gpio->ucGpioEntryNum; | |
1414 | voltage_table->phase_delay = gpio->ucPhaseDelay; | |
1415 | return 0; | |
1416 | } | |
1417 | break; | |
1418 | default: | |
1419 | DRM_ERROR("unknown voltage object table\n"); | |
1420 | return -EINVAL; | |
1421 | } | |
1422 | break; | |
1423 | default: | |
1424 | DRM_ERROR("unknown voltage object table\n"); | |
1425 | return -EINVAL; | |
1426 | } | |
1427 | } | |
1428 | return -EINVAL; | |
1429 | } | |
1430 | ||
1431 | union vram_info { | |
1432 | struct _ATOM_VRAM_INFO_V3 v1_3; | |
1433 | struct _ATOM_VRAM_INFO_V4 v1_4; | |
1434 | struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; | |
1435 | }; | |
1436 | ||
1437 | #define MEM_ID_MASK 0xff000000 | |
1438 | #define MEM_ID_SHIFT 24 | |
1439 | #define CLOCK_RANGE_MASK 0x00ffffff | |
1440 | #define CLOCK_RANGE_SHIFT 0 | |
1441 | #define LOW_NIBBLE_MASK 0xf | |
1442 | #define DATA_EQU_PREV 0 | |
1443 | #define DATA_FROM_TABLE 4 | |
1444 | ||
1445 | int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, | |
1446 | u8 module_index, | |
1447 | struct atom_mc_reg_table *reg_table) | |
1448 | { | |
1449 | int index = GetIndexIntoMasterTable(DATA, VRAM_Info); | |
1450 | u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; | |
1451 | u32 i = 0, j; | |
1452 | u16 data_offset, size; | |
1453 | union vram_info *vram_info; | |
1454 | ||
1455 | memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); | |
1456 | ||
1457 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1458 | &frev, &crev, &data_offset)) { | |
1459 | vram_info = (union vram_info *) | |
1460 | (adev->mode_info.atom_context->bios + data_offset); | |
1461 | switch (frev) { | |
1462 | case 1: | |
1463 | DRM_ERROR("old table version %d, %d\n", frev, crev); | |
1464 | return -EINVAL; | |
1465 | case 2: | |
1466 | switch (crev) { | |
1467 | case 1: | |
1468 | if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { | |
1469 | ATOM_INIT_REG_BLOCK *reg_block = | |
1470 | (ATOM_INIT_REG_BLOCK *) | |
1471 | ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); | |
1472 | ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = | |
1473 | (ATOM_MEMORY_SETTING_DATA_BLOCK *) | |
1474 | ((u8 *)reg_block + (2 * sizeof(u16)) + | |
1475 | le16_to_cpu(reg_block->usRegIndexTblSize)); | |
1476 | ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; | |
1477 | num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / | |
1478 | sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; | |
1479 | if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) | |
1480 | return -EINVAL; | |
1481 | while (i < num_entries) { | |
1482 | if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) | |
1483 | break; | |
1484 | reg_table->mc_reg_address[i].s1 = | |
1485 | (u16)(le16_to_cpu(format->usRegIndex)); | |
1486 | reg_table->mc_reg_address[i].pre_reg_data = | |
1487 | (u8)(format->ucPreRegDataLength); | |
1488 | i++; | |
1489 | format = (ATOM_INIT_REG_INDEX_FORMAT *) | |
1490 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); | |
1491 | } | |
1492 | reg_table->last = i; | |
1493 | while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && | |
1494 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { | |
1495 | t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) | |
1496 | >> MEM_ID_SHIFT); | |
1497 | if (module_index == t_mem_id) { | |
1498 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = | |
1499 | (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) | |
1500 | >> CLOCK_RANGE_SHIFT); | |
1501 | for (i = 0, j = 1; i < reg_table->last; i++) { | |
1502 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { | |
1503 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
1504 | (u32)le32_to_cpu(*((u32 *)reg_data + j)); | |
1505 | j++; | |
1506 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { | |
1507 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | |
1508 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; | |
1509 | } | |
1510 | } | |
1511 | num_ranges++; | |
1512 | } | |
1513 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) | |
1514 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); | |
1515 | } | |
1516 | if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) | |
1517 | return -EINVAL; | |
1518 | reg_table->num_entries = num_ranges; | |
1519 | } else | |
1520 | return -EINVAL; | |
1521 | break; | |
1522 | default: | |
1523 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1524 | return -EINVAL; | |
1525 | } | |
1526 | break; | |
1527 | default: | |
1528 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
1529 | return -EINVAL; | |
1530 | } | |
1531 | return 0; | |
1532 | } | |
1533 | return -EINVAL; | |
1534 | } | |
1535 | ||
e74adf20 AD |
1536 | bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) |
1537 | { | |
1538 | int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); | |
1539 | u8 frev, crev; | |
1540 | u16 data_offset, size; | |
1541 | ||
1542 | if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, | |
1543 | &frev, &crev, &data_offset)) | |
1544 | return true; | |
1545 | ||
1546 | return false; | |
1547 | } | |
1548 | ||
d38ceaf9 AD |
1549 | void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) |
1550 | { | |
1551 | uint32_t bios_6_scratch; | |
1552 | ||
1553 | bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); | |
1554 | ||
1555 | if (lock) { | |
1556 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; | |
1557 | bios_6_scratch &= ~ATOM_S6_ACC_MODE; | |
1558 | } else { | |
1559 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; | |
1560 | bios_6_scratch |= ATOM_S6_ACC_MODE; | |
1561 | } | |
1562 | ||
1563 | WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); | |
1564 | } | |
1565 | ||
1566 | void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) | |
1567 | { | |
1568 | uint32_t bios_2_scratch, bios_6_scratch; | |
1569 | ||
1570 | bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); | |
1571 | bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); | |
1572 | ||
1573 | /* let the bios control the backlight */ | |
1574 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; | |
1575 | ||
1576 | /* tell the bios not to handle mode switching */ | |
1577 | bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; | |
1578 | ||
1579 | /* clear the vbios dpms state */ | |
1580 | bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; | |
1581 | ||
1582 | WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); | |
1583 | WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); | |
1584 | } | |
1585 | ||
1586 | void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) | |
1587 | { | |
1588 | int i; | |
1589 | ||
1590 | for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) | |
1591 | adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); | |
1592 | } | |
1593 | ||
1594 | void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) | |
1595 | { | |
1596 | int i; | |
1597 | ||
1598 | for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) | |
1599 | WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); | |
1600 | } | |
1601 | ||
1602 | /* Atom needs data in little endian format | |
1603 | * so swap as appropriate when copying data to | |
1604 | * or from atom. Note that atom operates on | |
1605 | * dw units. | |
1606 | */ | |
1607 | void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) | |
1608 | { | |
1609 | #ifdef __BIG_ENDIAN | |
1610 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ | |
1611 | u32 *dst32, *src32; | |
1612 | int i; | |
1613 | ||
1614 | memcpy(src_tmp, src, num_bytes); | |
1615 | src32 = (u32 *)src_tmp; | |
1616 | dst32 = (u32 *)dst_tmp; | |
1617 | if (to_le) { | |
1618 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
1619 | dst32[i] = cpu_to_le32(src32[i]); | |
1620 | memcpy(dst, dst_tmp, num_bytes); | |
1621 | } else { | |
1622 | u8 dws = num_bytes & ~3; | |
1623 | for (i = 0; i < ((num_bytes + 3) / 4); i++) | |
1624 | dst32[i] = le32_to_cpu(src32[i]); | |
1625 | memcpy(dst, dst_tmp, dws); | |
1626 | if (num_bytes % 4) { | |
1627 | for (i = 0; i < (num_bytes % 4); i++) | |
1628 | dst[dws+i] = dst_tmp[dws+i]; | |
1629 | } | |
1630 | } | |
1631 | #else | |
1632 | memcpy(dst, src, num_bytes); | |
1633 | #endif | |
1634 | } |