[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cgs.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 *
 */
#include <linux/pci.h>
#include "amdgpu.h"
#include "cgs_linux.h"

struct amdgpu_cgs_device {
	struct cgs_device base;
	struct amdgpu_device *adev;
};

#define CGS_FUNC_ADEV							\
	struct amdgpu_device *adev =					\
		((struct amdgpu_cgs_device *)cgs_device)->adev

static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
				   uint64_t *mc_start, uint64_t *mc_size,
				   uint64_t *mem_size)
{
	return 0;
}

static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
				uint64_t size,
				uint64_t min_offset, uint64_t max_offset,
				cgs_handle_t *kmem_handle, uint64_t *mcaddr)
{
	return 0;
}

static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
{
	return 0;
}

static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
				    enum cgs_gpu_mem_type type,
				    uint64_t size, uint64_t align,
				    uint64_t min_offset, uint64_t max_offset,
				    cgs_handle_t *handle)
{
	return 0;
}

static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
				     cgs_handle_t *handle)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
				   uint64_t *mcaddr)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
				   void **map)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
{
	/* TODO */
	return 0;
}

static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
{
	CGS_FUNC_ADEV;
	return RREG32(offset);
}

static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
				      uint32_t value)
{
	CGS_FUNC_ADEV;
	WREG32(offset, value);
}

static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
					     enum cgs_ind_reg space,
					     unsigned index)
{
	CGS_FUNC_ADEV;
	switch (space) {
	case CGS_IND_REG__MMIO:
		return RREG32_IDX(index);
	case CGS_IND_REG__PCIE:
		return RREG32_PCIE(index);
	case CGS_IND_REG__SMC:
		return RREG32_SMC(index);
	case CGS_IND_REG__UVD_CTX:
		return RREG32_UVD_CTX(index);
	case CGS_IND_REG__DIDT:
		return RREG32_DIDT(index);
	case CGS_IND_REG__AUDIO_ENDPT:
		DRM_ERROR("audio endpt register access not implemented.\n");
		return 0;
	}
	WARN(1, "Invalid indirect register space");
	return 0;
}

static void amdgpu_cgs_write_ind_register(void *cgs_device,
					  enum cgs_ind_reg space,
					  unsigned index, uint32_t value)
{
	CGS_FUNC_ADEV;
	switch (space) {
	case CGS_IND_REG__MMIO:
		return WREG32_IDX(index, value);
	case CGS_IND_REG__PCIE:
		return WREG32_PCIE(index, value);
	case CGS_IND_REG__SMC:
		return WREG32_SMC(index, value);
	case CGS_IND_REG__UVD_CTX:
		return WREG32_UVD_CTX(index, value);
	case CGS_IND_REG__DIDT:
		return WREG32_DIDT(index, value);
	case CGS_IND_REG__AUDIO_ENDPT:
		DRM_ERROR("audio endpt register access not implemented.\n");
		return;
	}
	WARN(1, "Invalid indirect register space");
}

static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
{
	CGS_FUNC_ADEV;
	uint8_t val;
	int ret = pci_read_config_byte(adev->pdev, addr, &val);
	if (WARN(ret, "pci_read_config_byte error"))
		return 0;
	return val;
}

static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
{
	CGS_FUNC_ADEV;
	uint16_t val;
	int ret = pci_read_config_word(adev->pdev, addr, &val);
	if (WARN(ret, "pci_read_config_word error"))
		return 0;
	return val;
}

static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
						 unsigned addr)
{
	CGS_FUNC_ADEV;
	uint32_t val;
	int ret = pci_read_config_dword(adev->pdev, addr, &val);
	if (WARN(ret, "pci_read_config_dword error"))
		return 0;
	return val;
}

static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
					     uint8_t value)
{
	CGS_FUNC_ADEV;
	int ret = pci_write_config_byte(adev->pdev, addr, value);
	WARN(ret, "pci_write_config_byte error");
}

static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
					     uint16_t value)
{
	CGS_FUNC_ADEV;
	int ret = pci_write_config_word(adev->pdev, addr, value);
	WARN(ret, "pci_write_config_word error");
}

static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
					      uint32_t value)
{
	CGS_FUNC_ADEV;
	int ret = pci_write_config_dword(adev->pdev, addr, value);
	WARN(ret, "pci_write_config_dword error");
}

static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
						  unsigned table, uint16_t *size,
						  uint8_t *frev, uint8_t *crev)
{
	/* TODO */
	return NULL;
}

static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
					      uint8_t *frev, uint8_t *crev)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
					  void *args)
{
	/* TODO */
	return 0;
}


static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
				     int active)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
				       enum cgs_clock clock, unsigned freq)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
					enum cgs_engine engine, int powered)
{
	/* TODO */
	return 0;
}


static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
					    enum cgs_clock clock,
					    struct cgs_clock_limits *limits)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
					  const uint32_t *voltages)
{
	DRM_ERROR("not implemented");
	return -EPERM;
}

static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
				     unsigned num_types,
				     cgs_irq_source_set_func_t set,
				     cgs_irq_handler_func_t handler,
				     void *private_data)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
{
	/* TODO */
	return 0;
}

static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
{
	/* TODO */
	return 0;
}

static const struct cgs_ops amdgpu_cgs_ops = {
	amdgpu_cgs_gpu_mem_info,
	amdgpu_cgs_gmap_kmem,
	amdgpu_cgs_gunmap_kmem,
	amdgpu_cgs_alloc_gpu_mem,
	amdgpu_cgs_free_gpu_mem,
	amdgpu_cgs_gmap_gpu_mem,
	amdgpu_cgs_gunmap_gpu_mem,
	amdgpu_cgs_kmap_gpu_mem,
	amdgpu_cgs_kunmap_gpu_mem,
	amdgpu_cgs_read_register,
	amdgpu_cgs_write_register,
	amdgpu_cgs_read_ind_register,
	amdgpu_cgs_write_ind_register,
	amdgpu_cgs_read_pci_config_byte,
	amdgpu_cgs_read_pci_config_word,
	amdgpu_cgs_read_pci_config_dword,
	amdgpu_cgs_write_pci_config_byte,
	amdgpu_cgs_write_pci_config_word,
	amdgpu_cgs_write_pci_config_dword,
	amdgpu_cgs_atom_get_data_table,
	amdgpu_cgs_atom_get_cmd_table_revs,
	amdgpu_cgs_atom_exec_cmd_table,
	amdgpu_cgs_create_pm_request,
	amdgpu_cgs_destroy_pm_request,
	amdgpu_cgs_set_pm_request,
	amdgpu_cgs_pm_request_clock,
	amdgpu_cgs_pm_request_engine,
	amdgpu_cgs_pm_query_clock_limits,
	amdgpu_cgs_set_camera_voltages
};

static const struct cgs_os_ops amdgpu_cgs_os_ops = {
	amdgpu_cgs_import_gpu_mem,
	amdgpu_cgs_add_irq_source,
	amdgpu_cgs_irq_get,
	amdgpu_cgs_irq_put
};

void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
{
	struct amdgpu_cgs_device *cgs_device =
		kmalloc(sizeof(*cgs_device), GFP_KERNEL);

	if (!cgs_device) {
		DRM_ERROR("Couldn't allocate CGS device structure\n");
		return NULL;
	}

	cgs_device->base.ops = &amdgpu_cgs_ops;
	cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
	cgs_device->adev = adev;

	return cgs_device;
}

void amdgpu_cgs_destroy_device(void *cgs_device)
{
	kfree(cgs_device);
}
Commit	Line	Data
d03846af CZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*
	23	*/
97cb7f6e	24	#include <linux/pci.h>
d03846af CZ	25	#include "amdgpu.h"
	26	#include "cgs_linux.h"
	27
	28	struct amdgpu_cgs_device {
	29	struct cgs_device base;
	30	struct amdgpu_device *adev;
	31	};
	32
	33	#define CGS_FUNC_ADEV \
	34	struct amdgpu_device *adev = \
	35	((struct amdgpu_cgs_device *)cgs_device)->adev
	36
	37	static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
	38	uint64_t mc_start, uint64_t mc_size,
	39	uint64_t *mem_size)
	40	{
	41	return 0;
	42	}
	43
	44	static int amdgpu_cgs_gmap_kmem(void cgs_device, void kmem,
	45	uint64_t size,
	46	uint64_t min_offset, uint64_t max_offset,
	47	cgs_handle_t kmem_handle, uint64_t mcaddr)
	48	{
	49	return 0;
	50	}
	51
	52	static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
	53	{
	54	return 0;
	55	}
	56
	57	static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
	58	enum cgs_gpu_mem_type type,
	59	uint64_t size, uint64_t align,
	60	uint64_t min_offset, uint64_t max_offset,
	61	cgs_handle_t *handle)
	62	{
	63	return 0;
	64	}
	65
	66	static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
	67	cgs_handle_t *handle)
	68	{
	69	/* TODO */
	70	return 0;
	71	}
	72
	73	static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
	74	{
	75	/* TODO */
	76	return 0;
	77	}
	78
	79	static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
	80	uint64_t *mcaddr)
	81	{
	82	/* TODO */
	83	return 0;
	84	}
	85
	86	static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
	87	{
	88	/* TODO */
89	return 0;
90	}
91
92	static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
93	void **map)
94	{
95	/* TODO */
96	return 0;
97	}
98
99	static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
100	{
101	/* TODO */
102	return 0;
103	}
104
105	static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
106	{
aba684d8 CZ	107	CGS_FUNC_ADEV;
aba684d8 CZ	108	return RREG32(offset);
d03846af CZ	109	}
	110
	111	static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
	112	uint32_t value)
	113	{
aba684d8 CZ	114	CGS_FUNC_ADEV;
aba684d8 CZ	115	WREG32(offset, value);
d03846af CZ	116	}
	117
	118	static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
	119	enum cgs_ind_reg space,
	120	unsigned index)
	121	{
aba684d8 CZ	122	CGS_FUNC_ADEV;
	123	switch (space) {
	124	case CGS_IND_REG__MMIO:
	125	return RREG32_IDX(index);
	126	case CGS_IND_REG__PCIE:
	127	return RREG32_PCIE(index);
	128	case CGS_IND_REG__SMC:
	129	return RREG32_SMC(index);
	130	case CGS_IND_REG__UVD_CTX:
	131	return RREG32_UVD_CTX(index);
	132	case CGS_IND_REG__DIDT:
	133	return RREG32_DIDT(index);
	134	case CGS_IND_REG__AUDIO_ENDPT:
	135	DRM_ERROR("audio endpt register access not implemented.\n");
	136	return 0;
	137	}
	138	WARN(1, "Invalid indirect register space");
d03846af CZ	139	return 0;
	140	}
	141
	142	static void amdgpu_cgs_write_ind_register(void *cgs_device,
	143	enum cgs_ind_reg space,
	144	unsigned index, uint32_t value)
	145	{
aba684d8 CZ	146	CGS_FUNC_ADEV;
	147	switch (space) {
	148	case CGS_IND_REG__MMIO:
	149	return WREG32_IDX(index, value);
	150	case CGS_IND_REG__PCIE:
	151	return WREG32_PCIE(index, value);
	152	case CGS_IND_REG__SMC:
	153	return WREG32_SMC(index, value);
	154	case CGS_IND_REG__UVD_CTX:
	155	return WREG32_UVD_CTX(index, value);
	156	case CGS_IND_REG__DIDT:
	157	return WREG32_DIDT(index, value);
	158	case CGS_IND_REG__AUDIO_ENDPT:
	159	DRM_ERROR("audio endpt register access not implemented.\n");
	160	return;
	161	}
	162	WARN(1, "Invalid indirect register space");
d03846af CZ	163	}
	164
	165	static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
	166	{
97cb7f6e CZ	167	CGS_FUNC_ADEV;
	168	uint8_t val;
	169	int ret = pci_read_config_byte(adev->pdev, addr, &val);
	170	if (WARN(ret, "pci_read_config_byte error"))
	171	return 0;
	172	return val;
d03846af CZ	173	}
	174
	175	static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
	176	{
97cb7f6e CZ	177	CGS_FUNC_ADEV;
	178	uint16_t val;
	179	int ret = pci_read_config_word(adev->pdev, addr, &val);
	180	if (WARN(ret, "pci_read_config_word error"))
	181	return 0;
	182	return val;
d03846af CZ	183	}
	184
	185	static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
	186	unsigned addr)
	187	{
97cb7f6e CZ	188	CGS_FUNC_ADEV;
	189	uint32_t val;
	190	int ret = pci_read_config_dword(adev->pdev, addr, &val);
	191	if (WARN(ret, "pci_read_config_dword error"))
	192	return 0;
	193	return val;
d03846af CZ	194	}
	195
	196	static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
	197	uint8_t value)
	198	{
97cb7f6e CZ	199	CGS_FUNC_ADEV;
	200	int ret = pci_write_config_byte(adev->pdev, addr, value);
	201	WARN(ret, "pci_write_config_byte error");
d03846af CZ	202	}
	203
	204	static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
	205	uint16_t value)
	206	{
97cb7f6e CZ	207	CGS_FUNC_ADEV;
	208	int ret = pci_write_config_word(adev->pdev, addr, value);
	209	WARN(ret, "pci_write_config_word error");
d03846af CZ	210	}
	211
	212	static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
	213	uint32_t value)
	214	{
97cb7f6e CZ	215	CGS_FUNC_ADEV;
	216	int ret = pci_write_config_dword(adev->pdev, addr, value);
	217	WARN(ret, "pci_write_config_dword error");
d03846af CZ	218	}
	219
	220	static const void amdgpu_cgs_atom_get_data_table(void cgs_device,
	221	unsigned table, uint16_t *size,
	222	uint8_t frev, uint8_t crev)
	223	{
	224	/* TODO */
	225	return NULL;
	226	}
	227
	228	static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
	229	uint8_t frev, uint8_t crev)
	230	{
	231	/* TODO */
	232	return 0;
	233	}
	234
	235	static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
	236	void *args)
	237	{
	238	/* TODO */
	239	return 0;
	240	}
	241
	242
	243	static int amdgpu_cgs_create_pm_request(void cgs_device, cgs_handle_t request)
	244	{
	245	/* TODO */
	246	return 0;
	247	}
	248
	249	static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
	250	{
	251	/* TODO */
	252	return 0;
	253	}
	254
	255	static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
	256	int active)
	257	{
	258	/* TODO */
	259	return 0;
	260	}
	261
	262	static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
	263	enum cgs_clock clock, unsigned freq)
	264	{
	265	/* TODO */
	266	return 0;
	267	}
	268
	269	static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
	270	enum cgs_engine engine, int powered)
	271	{
	272	/* TODO */
	273	return 0;
	274	}
	275
	276
	277
	278	static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
	279	enum cgs_clock clock,
	280	struct cgs_clock_limits *limits)
	281	{
282	/* TODO */
283	return 0;
284	}
285
286	static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
287	const uint32_t *voltages)
288	{
289	DRM_ERROR("not implemented");
290	return -EPERM;
291	}
292
293	static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
294	unsigned num_types,
295	cgs_irq_source_set_func_t set,
296	cgs_irq_handler_func_t handler,
297	void *private_data)
298	{
299	/* TODO */
300	return 0;
301	}
302
303	static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
304	{
305	/* TODO */
306	return 0;
307	}
308
309	static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
310	{
311	/* TODO */
312	return 0;
313	}
314
315	static const struct cgs_ops amdgpu_cgs_ops = {
316	amdgpu_cgs_gpu_mem_info,
317	amdgpu_cgs_gmap_kmem,
318	amdgpu_cgs_gunmap_kmem,
319	amdgpu_cgs_alloc_gpu_mem,
320	amdgpu_cgs_free_gpu_mem,
321	amdgpu_cgs_gmap_gpu_mem,
322	amdgpu_cgs_gunmap_gpu_mem,
323	amdgpu_cgs_kmap_gpu_mem,
324	amdgpu_cgs_kunmap_gpu_mem,
325	amdgpu_cgs_read_register,
326	amdgpu_cgs_write_register,
327	amdgpu_cgs_read_ind_register,
328	amdgpu_cgs_write_ind_register,
329	amdgpu_cgs_read_pci_config_byte,
330	amdgpu_cgs_read_pci_config_word,
331	amdgpu_cgs_read_pci_config_dword,
332	amdgpu_cgs_write_pci_config_byte,
333	amdgpu_cgs_write_pci_config_word,
334	amdgpu_cgs_write_pci_config_dword,
335	amdgpu_cgs_atom_get_data_table,
336	amdgpu_cgs_atom_get_cmd_table_revs,
337	amdgpu_cgs_atom_exec_cmd_table,
338	amdgpu_cgs_create_pm_request,
339	amdgpu_cgs_destroy_pm_request,
340	amdgpu_cgs_set_pm_request,
341	amdgpu_cgs_pm_request_clock,
342	amdgpu_cgs_pm_request_engine,
343	amdgpu_cgs_pm_query_clock_limits,
344	amdgpu_cgs_set_camera_voltages
345	};
346
347	static const struct cgs_os_ops amdgpu_cgs_os_ops = {
348	amdgpu_cgs_import_gpu_mem,
349	amdgpu_cgs_add_irq_source,
350	amdgpu_cgs_irq_get,
351	amdgpu_cgs_irq_put
352	};
353
354	void amdgpu_cgs_create_device(struct amdgpu_device adev)
355	{
356	struct amdgpu_cgs_device *cgs_device =
357	kmalloc(sizeof(*cgs_device), GFP_KERNEL);
358
359	if (!cgs_device) {
360	DRM_ERROR("Couldn't allocate CGS device structure\n");
361	return NULL;
362	}
363
364	cgs_device->base.ops = &amdgpu_cgs_ops;
365	cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
366	cgs_device->adev = adev;
367
368	return cgs_device;
369	}
370
371	void amdgpu_cgs_destroy_device(void *cgs_device)
372	{
373	kfree(cgs_device);
374	}