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1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include "amdgpu.h" | |
25 | #include "cgs_linux.h" | |
26 | ||
27 | struct amdgpu_cgs_device { | |
28 | struct cgs_device base; | |
29 | struct amdgpu_device *adev; | |
30 | }; | |
31 | ||
32 | #define CGS_FUNC_ADEV \ | |
33 | struct amdgpu_device *adev = \ | |
34 | ((struct amdgpu_cgs_device *)cgs_device)->adev | |
35 | ||
36 | static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type, | |
37 | uint64_t *mc_start, uint64_t *mc_size, | |
38 | uint64_t *mem_size) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | ||
43 | static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem, | |
44 | uint64_t size, | |
45 | uint64_t min_offset, uint64_t max_offset, | |
46 | cgs_handle_t *kmem_handle, uint64_t *mcaddr) | |
47 | { | |
48 | return 0; | |
49 | } | |
50 | ||
51 | static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle) | |
52 | { | |
53 | return 0; | |
54 | } | |
55 | ||
56 | static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, | |
57 | enum cgs_gpu_mem_type type, | |
58 | uint64_t size, uint64_t align, | |
59 | uint64_t min_offset, uint64_t max_offset, | |
60 | cgs_handle_t *handle) | |
61 | { | |
62 | return 0; | |
63 | } | |
64 | ||
65 | static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd, | |
66 | cgs_handle_t *handle) | |
67 | { | |
68 | /* TODO */ | |
69 | return 0; | |
70 | } | |
71 | ||
72 | static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) | |
73 | { | |
74 | /* TODO */ | |
75 | return 0; | |
76 | } | |
77 | ||
78 | static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle, | |
79 | uint64_t *mcaddr) | |
80 | { | |
81 | /* TODO */ | |
82 | return 0; | |
83 | } | |
84 | ||
85 | static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) | |
86 | { | |
87 | /* TODO */ | |
88 | return 0; | |
89 | } | |
90 | ||
91 | static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle, | |
92 | void **map) | |
93 | { | |
94 | /* TODO */ | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle) | |
99 | { | |
100 | /* TODO */ | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset) | |
105 | { | |
106 | /* TODO */ | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset, | |
111 | uint32_t value) | |
112 | { | |
113 | /* TODO */ | |
114 | return; | |
115 | } | |
116 | ||
117 | static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device, | |
118 | enum cgs_ind_reg space, | |
119 | unsigned index) | |
120 | { | |
121 | /* TODO */ | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static void amdgpu_cgs_write_ind_register(void *cgs_device, | |
126 | enum cgs_ind_reg space, | |
127 | unsigned index, uint32_t value) | |
128 | { | |
129 | /* TODO */ | |
130 | return; | |
131 | } | |
132 | ||
133 | static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr) | |
134 | { | |
135 | /* TODO */ | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr) | |
140 | { | |
141 | /* TODO */ | |
142 | return 0; | |
143 | } | |
144 | ||
145 | static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device, | |
146 | unsigned addr) | |
147 | { | |
148 | /* TODO */ | |
149 | return 0; | |
150 | } | |
151 | ||
152 | static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr, | |
153 | uint8_t value) | |
154 | { | |
155 | /* TODO */ | |
156 | return; | |
157 | } | |
158 | ||
159 | static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr, | |
160 | uint16_t value) | |
161 | { | |
162 | /* TODO */ | |
163 | return; | |
164 | } | |
165 | ||
166 | static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr, | |
167 | uint32_t value) | |
168 | { | |
169 | /* TODO */ | |
170 | return; | |
171 | } | |
172 | ||
173 | static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device, | |
174 | unsigned table, uint16_t *size, | |
175 | uint8_t *frev, uint8_t *crev) | |
176 | { | |
177 | /* TODO */ | |
178 | return NULL; | |
179 | } | |
180 | ||
181 | static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table, | |
182 | uint8_t *frev, uint8_t *crev) | |
183 | { | |
184 | /* TODO */ | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table, | |
189 | void *args) | |
190 | { | |
191 | /* TODO */ | |
192 | return 0; | |
193 | } | |
194 | ||
195 | ||
196 | static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request) | |
197 | { | |
198 | /* TODO */ | |
199 | return 0; | |
200 | } | |
201 | ||
202 | static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request) | |
203 | { | |
204 | /* TODO */ | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request, | |
209 | int active) | |
210 | { | |
211 | /* TODO */ | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request, | |
216 | enum cgs_clock clock, unsigned freq) | |
217 | { | |
218 | /* TODO */ | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request, | |
223 | enum cgs_engine engine, int powered) | |
224 | { | |
225 | /* TODO */ | |
226 | return 0; | |
227 | } | |
228 | ||
229 | ||
230 | ||
231 | static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device, | |
232 | enum cgs_clock clock, | |
233 | struct cgs_clock_limits *limits) | |
234 | { | |
235 | /* TODO */ | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask, | |
240 | const uint32_t *voltages) | |
241 | { | |
242 | DRM_ERROR("not implemented"); | |
243 | return -EPERM; | |
244 | } | |
245 | ||
246 | static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id, | |
247 | unsigned num_types, | |
248 | cgs_irq_source_set_func_t set, | |
249 | cgs_irq_handler_func_t handler, | |
250 | void *private_data) | |
251 | { | |
252 | /* TODO */ | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type) | |
257 | { | |
258 | /* TODO */ | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type) | |
263 | { | |
264 | /* TODO */ | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static const struct cgs_ops amdgpu_cgs_ops = { | |
269 | amdgpu_cgs_gpu_mem_info, | |
270 | amdgpu_cgs_gmap_kmem, | |
271 | amdgpu_cgs_gunmap_kmem, | |
272 | amdgpu_cgs_alloc_gpu_mem, | |
273 | amdgpu_cgs_free_gpu_mem, | |
274 | amdgpu_cgs_gmap_gpu_mem, | |
275 | amdgpu_cgs_gunmap_gpu_mem, | |
276 | amdgpu_cgs_kmap_gpu_mem, | |
277 | amdgpu_cgs_kunmap_gpu_mem, | |
278 | amdgpu_cgs_read_register, | |
279 | amdgpu_cgs_write_register, | |
280 | amdgpu_cgs_read_ind_register, | |
281 | amdgpu_cgs_write_ind_register, | |
282 | amdgpu_cgs_read_pci_config_byte, | |
283 | amdgpu_cgs_read_pci_config_word, | |
284 | amdgpu_cgs_read_pci_config_dword, | |
285 | amdgpu_cgs_write_pci_config_byte, | |
286 | amdgpu_cgs_write_pci_config_word, | |
287 | amdgpu_cgs_write_pci_config_dword, | |
288 | amdgpu_cgs_atom_get_data_table, | |
289 | amdgpu_cgs_atom_get_cmd_table_revs, | |
290 | amdgpu_cgs_atom_exec_cmd_table, | |
291 | amdgpu_cgs_create_pm_request, | |
292 | amdgpu_cgs_destroy_pm_request, | |
293 | amdgpu_cgs_set_pm_request, | |
294 | amdgpu_cgs_pm_request_clock, | |
295 | amdgpu_cgs_pm_request_engine, | |
296 | amdgpu_cgs_pm_query_clock_limits, | |
297 | amdgpu_cgs_set_camera_voltages | |
298 | }; | |
299 | ||
300 | static const struct cgs_os_ops amdgpu_cgs_os_ops = { | |
301 | amdgpu_cgs_import_gpu_mem, | |
302 | amdgpu_cgs_add_irq_source, | |
303 | amdgpu_cgs_irq_get, | |
304 | amdgpu_cgs_irq_put | |
305 | }; | |
306 | ||
307 | void *amdgpu_cgs_create_device(struct amdgpu_device *adev) | |
308 | { | |
309 | struct amdgpu_cgs_device *cgs_device = | |
310 | kmalloc(sizeof(*cgs_device), GFP_KERNEL); | |
311 | ||
312 | if (!cgs_device) { | |
313 | DRM_ERROR("Couldn't allocate CGS device structure\n"); | |
314 | return NULL; | |
315 | } | |
316 | ||
317 | cgs_device->base.ops = &amdgpu_cgs_ops; | |
318 | cgs_device->base.os_ops = &amdgpu_cgs_os_ops; | |
319 | cgs_device->adev = adev; | |
320 | ||
321 | return cgs_device; | |
322 | } | |
323 | ||
324 | void amdgpu_cgs_destroy_device(void *cgs_device) | |
325 | { | |
326 | kfree(cgs_device); | |
327 | } |