Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
27 | #include <linux/list_sort.h> | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | #define AMDGPU_CS_MAX_PRIORITY 32u | |
34 | #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) | |
35 | ||
36 | /* This is based on the bucket sort with O(n) time complexity. | |
37 | * An item with priority "i" is added to bucket[i]. The lists are then | |
38 | * concatenated in descending order. | |
39 | */ | |
40 | struct amdgpu_cs_buckets { | |
41 | struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; | |
42 | }; | |
43 | ||
44 | static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) | |
45 | { | |
46 | unsigned i; | |
47 | ||
48 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) | |
49 | INIT_LIST_HEAD(&b->bucket[i]); | |
50 | } | |
51 | ||
52 | static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, | |
53 | struct list_head *item, unsigned priority) | |
54 | { | |
55 | /* Since buffers which appear sooner in the relocation list are | |
56 | * likely to be used more often than buffers which appear later | |
57 | * in the list, the sort mustn't change the ordering of buffers | |
58 | * with the same priority, i.e. it must be stable. | |
59 | */ | |
60 | list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); | |
61 | } | |
62 | ||
63 | static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, | |
64 | struct list_head *out_list) | |
65 | { | |
66 | unsigned i; | |
67 | ||
68 | /* Connect the sorted buckets in the output list. */ | |
69 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { | |
70 | list_splice(&b->bucket[i], out_list); | |
71 | } | |
72 | } | |
73 | ||
74 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
75 | u32 ip_instance, u32 ring, | |
76 | struct amdgpu_ring **out_ring) | |
77 | { | |
78 | /* Right now all IPs have only one instance - multiple rings. */ | |
79 | if (ip_instance != 0) { | |
80 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | switch (ip_type) { | |
85 | default: | |
86 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
87 | return -EINVAL; | |
88 | case AMDGPU_HW_IP_GFX: | |
89 | if (ring < adev->gfx.num_gfx_rings) { | |
90 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
91 | } else { | |
92 | DRM_ERROR("only %d gfx rings are supported now\n", | |
93 | adev->gfx.num_gfx_rings); | |
94 | return -EINVAL; | |
95 | } | |
96 | break; | |
97 | case AMDGPU_HW_IP_COMPUTE: | |
98 | if (ring < adev->gfx.num_compute_rings) { | |
99 | *out_ring = &adev->gfx.compute_ring[ring]; | |
100 | } else { | |
101 | DRM_ERROR("only %d compute rings are supported now\n", | |
102 | adev->gfx.num_compute_rings); | |
103 | return -EINVAL; | |
104 | } | |
105 | break; | |
106 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
107 | if (ring < adev->sdma.num_instances) { |
108 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 109 | } else { |
c113ea1c AD |
110 | DRM_ERROR("only %d SDMA rings are supported\n", |
111 | adev->sdma.num_instances); | |
d38ceaf9 AD |
112 | return -EINVAL; |
113 | } | |
114 | break; | |
115 | case AMDGPU_HW_IP_UVD: | |
116 | *out_ring = &adev->uvd.ring; | |
117 | break; | |
118 | case AMDGPU_HW_IP_VCE: | |
119 | if (ring < 2){ | |
120 | *out_ring = &adev->vce.ring[ring]; | |
121 | } else { | |
122 | DRM_ERROR("only two VCE rings are supported\n"); | |
123 | return -EINVAL; | |
124 | } | |
125 | break; | |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
130 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) | |
131 | { | |
132 | union drm_amdgpu_cs *cs = data; | |
133 | uint64_t *chunk_array_user; | |
1d263474 | 134 | uint64_t *chunk_array; |
d38ceaf9 | 135 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
54313503 DC |
136 | unsigned size; |
137 | int i; | |
1d263474 | 138 | int ret; |
d38ceaf9 | 139 | |
1d263474 DC |
140 | if (cs->in.num_chunks == 0) |
141 | return 0; | |
142 | ||
143 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
144 | if (!chunk_array) | |
145 | return -ENOMEM; | |
d38ceaf9 | 146 | |
3cb485f3 CK |
147 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
148 | if (!p->ctx) { | |
1d263474 DC |
149 | ret = -EINVAL; |
150 | goto free_chunk; | |
3cb485f3 | 151 | } |
1d263474 | 152 | |
a3348bb8 | 153 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); |
d38ceaf9 AD |
154 | |
155 | /* get chunks */ | |
156 | INIT_LIST_HEAD(&p->validated); | |
028423b0 | 157 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
158 | if (copy_from_user(chunk_array, chunk_array_user, |
159 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 DC |
160 | ret = -EFAULT; |
161 | goto put_bo_list; | |
d38ceaf9 AD |
162 | } |
163 | ||
164 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 165 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 166 | GFP_KERNEL); |
1d263474 DC |
167 | if (!p->chunks) { |
168 | ret = -ENOMEM; | |
169 | goto put_bo_list; | |
d38ceaf9 AD |
170 | } |
171 | ||
172 | for (i = 0; i < p->nchunks; i++) { | |
173 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
174 | struct drm_amdgpu_cs_chunk user_chunk; | |
175 | uint32_t __user *cdata; | |
176 | ||
028423b0 | 177 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
178 | if (copy_from_user(&user_chunk, chunk_ptr, |
179 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
180 | ret = -EFAULT; |
181 | i--; | |
182 | goto free_partial_kdata; | |
d38ceaf9 AD |
183 | } |
184 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
185 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
186 | |
187 | size = p->chunks[i].length_dw; | |
028423b0 | 188 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
189 | p->chunks[i].user_ptr = cdata; |
190 | ||
191 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
192 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
193 | ret = -ENOMEM; |
194 | i--; | |
195 | goto free_partial_kdata; | |
d38ceaf9 AD |
196 | } |
197 | size *= sizeof(uint32_t); | |
198 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
199 | ret = -EFAULT; |
200 | goto free_partial_kdata; | |
d38ceaf9 AD |
201 | } |
202 | ||
9a5e8fb1 CK |
203 | switch (p->chunks[i].chunk_id) { |
204 | case AMDGPU_CHUNK_ID_IB: | |
205 | p->num_ibs++; | |
206 | break; | |
207 | ||
208 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 AD |
209 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
210 | if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) { | |
211 | uint32_t handle; | |
212 | struct drm_gem_object *gobj; | |
213 | struct drm_amdgpu_cs_chunk_fence *fence_data; | |
214 | ||
215 | fence_data = (void *)p->chunks[i].kdata; | |
216 | handle = fence_data->handle; | |
217 | gobj = drm_gem_object_lookup(p->adev->ddev, | |
218 | p->filp, handle); | |
219 | if (gobj == NULL) { | |
1d263474 DC |
220 | ret = -EINVAL; |
221 | goto free_partial_kdata; | |
d38ceaf9 AD |
222 | } |
223 | ||
224 | p->uf.bo = gem_to_amdgpu_bo(gobj); | |
225 | p->uf.offset = fence_data->offset; | |
226 | } else { | |
1d263474 DC |
227 | ret = -EINVAL; |
228 | goto free_partial_kdata; | |
d38ceaf9 | 229 | } |
9a5e8fb1 CK |
230 | break; |
231 | ||
2b48d323 CK |
232 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
233 | break; | |
234 | ||
9a5e8fb1 | 235 | default: |
1d263474 DC |
236 | ret = -EINVAL; |
237 | goto free_partial_kdata; | |
d38ceaf9 AD |
238 | } |
239 | } | |
240 | ||
e60b344f | 241 | |
b203dd95 | 242 | p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); |
1d263474 DC |
243 | if (!p->ibs) { |
244 | ret = -ENOMEM; | |
245 | goto free_all_kdata; | |
246 | } | |
d38ceaf9 | 247 | |
d38ceaf9 | 248 | kfree(chunk_array); |
1d263474 DC |
249 | return 0; |
250 | ||
251 | free_all_kdata: | |
252 | i = p->nchunks - 1; | |
253 | free_partial_kdata: | |
254 | for (; i >= 0; i--) | |
255 | drm_free_large(p->chunks[i].kdata); | |
256 | kfree(p->chunks); | |
257 | put_bo_list: | |
258 | if (p->bo_list) | |
259 | amdgpu_bo_list_put(p->bo_list); | |
260 | amdgpu_ctx_put(p->ctx); | |
261 | free_chunk: | |
262 | kfree(chunk_array); | |
263 | ||
264 | return ret; | |
d38ceaf9 AD |
265 | } |
266 | ||
267 | /* Returns how many bytes TTM can move per IB. | |
268 | */ | |
269 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
270 | { | |
271 | u64 real_vram_size = adev->mc.real_vram_size; | |
272 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
273 | ||
274 | /* This function is based on the current VRAM usage. | |
275 | * | |
276 | * - If all of VRAM is free, allow relocating the number of bytes that | |
277 | * is equal to 1/4 of the size of VRAM for this IB. | |
278 | ||
279 | * - If more than one half of VRAM is occupied, only allow relocating | |
280 | * 1 MB of data for this IB. | |
281 | * | |
282 | * - From 0 to one half of used VRAM, the threshold decreases | |
283 | * linearly. | |
284 | * __________________ | |
285 | * 1/4 of -|\ | | |
286 | * VRAM | \ | | |
287 | * | \ | | |
288 | * | \ | | |
289 | * | \ | | |
290 | * | \ | | |
291 | * | \ | | |
292 | * | \________|1 MB | |
293 | * |----------------| | |
294 | * VRAM 0 % 100 % | |
295 | * used used | |
296 | * | |
297 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
298 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
299 | * can be moved as long as the threshold isn't crossed before | |
300 | * the relocation takes place. We don't want to disable buffer | |
301 | * relocations completely. | |
302 | * | |
303 | * The idea is that buffers should be placed in VRAM at creation time | |
304 | * and TTM should only do a minimum number of relocations during | |
305 | * command submission. In practice, you need to submit at least | |
306 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
307 | * | |
308 | * Also, things can get pretty crazy under memory pressure and actual | |
309 | * VRAM usage can change a lot, so playing safe even at 50% does | |
310 | * consistently increase performance. | |
311 | */ | |
312 | ||
313 | u64 half_vram = real_vram_size >> 1; | |
314 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
315 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
316 | return max(bytes_moved_threshold, 1024*1024ull); | |
317 | } | |
318 | ||
a5b75058 CK |
319 | int amdgpu_cs_list_validate(struct amdgpu_device *adev, |
320 | struct amdgpu_vm *vm, | |
321 | struct list_head *validated) | |
d38ceaf9 | 322 | { |
d38ceaf9 | 323 | struct amdgpu_bo_list_entry *lobj; |
d38ceaf9 AD |
324 | struct amdgpu_bo *bo; |
325 | u64 bytes_moved = 0, initial_bytes_moved; | |
326 | u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); | |
327 | int r; | |
328 | ||
a5b75058 | 329 | list_for_each_entry(lobj, validated, tv.head) { |
d38ceaf9 AD |
330 | bo = lobj->robj; |
331 | if (!bo->pin_count) { | |
332 | u32 domain = lobj->prefered_domains; | |
333 | u32 current_domain = | |
334 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
335 | ||
336 | /* Check if this buffer will be moved and don't move it | |
337 | * if we have moved too many buffers for this IB already. | |
338 | * | |
339 | * Note that this allows moving at least one buffer of | |
340 | * any size, because it doesn't take the current "bo" | |
341 | * into account. We don't want to disallow buffer moves | |
342 | * completely. | |
343 | */ | |
270e869d | 344 | if ((lobj->allowed_domains & current_domain) != 0 && |
d38ceaf9 AD |
345 | (domain & current_domain) == 0 && /* will be moved */ |
346 | bytes_moved > bytes_moved_threshold) { | |
347 | /* don't move it */ | |
348 | domain = current_domain; | |
349 | } | |
350 | ||
351 | retry: | |
352 | amdgpu_ttm_placement_from_domain(bo, domain); | |
353 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); | |
354 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
355 | bytes_moved += atomic64_read(&adev->num_bytes_moved) - | |
356 | initial_bytes_moved; | |
357 | ||
358 | if (unlikely(r)) { | |
359 | if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { | |
360 | domain = lobj->allowed_domains; | |
361 | goto retry; | |
362 | } | |
d38ceaf9 AD |
363 | return r; |
364 | } | |
365 | } | |
366 | lobj->bo_va = amdgpu_vm_bo_find(vm, bo); | |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) | |
372 | { | |
373 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
374 | struct amdgpu_cs_buckets buckets; | |
a5b75058 | 375 | struct list_head duplicates; |
840d5144 | 376 | bool need_mmap_lock = false; |
d38ceaf9 AD |
377 | int i, r; |
378 | ||
840d5144 | 379 | if (p->bo_list) { |
380 | need_mmap_lock = p->bo_list->has_userptr; | |
381 | amdgpu_cs_buckets_init(&buckets); | |
382 | for (i = 0; i < p->bo_list->num_entries; i++) | |
383 | amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, | |
384 | p->bo_list->array[i].priority); | |
d38ceaf9 | 385 | |
840d5144 | 386 | amdgpu_cs_buckets_get_list(&buckets, &p->validated); |
387 | } | |
d38ceaf9 | 388 | |
3c0eea6c | 389 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 390 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 391 | |
d38ceaf9 AD |
392 | if (need_mmap_lock) |
393 | down_read(¤t->mm->mmap_sem); | |
394 | ||
a5b75058 CK |
395 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); |
396 | if (unlikely(r != 0)) | |
397 | goto error_reserve; | |
398 | ||
56467ebf CK |
399 | p->vm_bos = amdgpu_vm_get_pt_bos(&fpriv->vm, &duplicates); |
400 | if (!p->vm_bos) { | |
401 | r = -ENOMEM; | |
402 | goto error_validate; | |
403 | } | |
404 | ||
a5b75058 CK |
405 | r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &p->validated); |
406 | if (r) | |
407 | goto error_validate; | |
408 | ||
409 | r = amdgpu_cs_list_validate(p->adev, &fpriv->vm, &duplicates); | |
410 | ||
411 | error_validate: | |
412 | if (r) | |
413 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
d38ceaf9 | 414 | |
a5b75058 | 415 | error_reserve: |
d38ceaf9 AD |
416 | if (need_mmap_lock) |
417 | up_read(¤t->mm->mmap_sem); | |
418 | ||
419 | return r; | |
420 | } | |
421 | ||
422 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
423 | { | |
424 | struct amdgpu_bo_list_entry *e; | |
425 | int r; | |
426 | ||
427 | list_for_each_entry(e, &p->validated, tv.head) { | |
428 | struct reservation_object *resv = e->robj->tbo.resv; | |
429 | r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); | |
430 | ||
431 | if (r) | |
432 | return r; | |
433 | } | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static int cmp_size_smaller_first(void *priv, struct list_head *a, | |
438 | struct list_head *b) | |
439 | { | |
440 | struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); | |
441 | struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); | |
442 | ||
443 | /* Sort A before B if A is smaller. */ | |
444 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; | |
445 | } | |
446 | ||
984810fc CK |
447 | /** |
448 | * cs_parser_fini() - clean parser states | |
449 | * @parser: parser structure holding parsing context. | |
450 | * @error: error number | |
451 | * | |
452 | * If error is set than unvalidate buffer, otherwise just free memory | |
453 | * used by parsing context. | |
454 | **/ | |
455 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 456 | { |
984810fc CK |
457 | unsigned i; |
458 | ||
d38ceaf9 AD |
459 | if (!error) { |
460 | /* Sort the buffer list from the smallest to largest buffer, | |
461 | * which affects the order of buffers in the LRU list. | |
462 | * This assures that the smallest buffers are added first | |
463 | * to the LRU list, so they are likely to be later evicted | |
464 | * first, instead of large buffers whose eviction is more | |
465 | * expensive. | |
466 | * | |
467 | * This slightly lowers the number of bytes moved by TTM | |
468 | * per frame under memory pressure. | |
469 | */ | |
470 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
471 | ||
472 | ttm_eu_fence_buffer_objects(&parser->ticket, | |
984810fc CK |
473 | &parser->validated, |
474 | parser->fence); | |
d38ceaf9 AD |
475 | } else if (backoff) { |
476 | ttm_eu_backoff_reservation(&parser->ticket, | |
477 | &parser->validated); | |
478 | } | |
984810fc | 479 | fence_put(parser->fence); |
7e52a81c | 480 | |
3cb485f3 CK |
481 | if (parser->ctx) |
482 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
483 | if (parser->bo_list) |
484 | amdgpu_bo_list_put(parser->bo_list); | |
485 | ||
d38ceaf9 AD |
486 | drm_free_large(parser->vm_bos); |
487 | for (i = 0; i < parser->nchunks; i++) | |
488 | drm_free_large(parser->chunks[i].kdata); | |
489 | kfree(parser->chunks); | |
e4a58a28 CK |
490 | if (parser->ibs) |
491 | for (i = 0; i < parser->num_ibs; i++) | |
492 | amdgpu_ib_free(parser->adev, &parser->ibs[i]); | |
493 | kfree(parser->ibs); | |
494 | if (parser->uf.bo) | |
495 | drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); | |
d38ceaf9 AD |
496 | } |
497 | ||
498 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
499 | struct amdgpu_vm *vm) | |
500 | { | |
501 | struct amdgpu_device *adev = p->adev; | |
502 | struct amdgpu_bo_va *bo_va; | |
503 | struct amdgpu_bo *bo; | |
504 | int i, r; | |
505 | ||
506 | r = amdgpu_vm_update_page_directory(adev, vm); | |
507 | if (r) | |
508 | return r; | |
509 | ||
05906dec BN |
510 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); |
511 | if (r) | |
512 | return r; | |
513 | ||
d38ceaf9 AD |
514 | r = amdgpu_vm_clear_freed(adev, vm); |
515 | if (r) | |
516 | return r; | |
517 | ||
518 | if (p->bo_list) { | |
519 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
520 | struct fence *f; |
521 | ||
d38ceaf9 AD |
522 | /* ignore duplicates */ |
523 | bo = p->bo_list->array[i].robj; | |
524 | if (!bo) | |
525 | continue; | |
526 | ||
527 | bo_va = p->bo_list->array[i].bo_va; | |
528 | if (bo_va == NULL) | |
529 | continue; | |
530 | ||
531 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
532 | if (r) | |
533 | return r; | |
534 | ||
bb1e38a4 | 535 | f = bo_va->last_pt_update; |
91e1a520 CK |
536 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); |
537 | if (r) | |
538 | return r; | |
d38ceaf9 | 539 | } |
b495bd3a CK |
540 | |
541 | } | |
542 | ||
543 | r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); | |
544 | ||
545 | if (amdgpu_vm_debug && p->bo_list) { | |
546 | /* Invalidate all BOs to test for userspace bugs */ | |
547 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
548 | /* ignore duplicates */ | |
549 | bo = p->bo_list->array[i].robj; | |
550 | if (!bo) | |
551 | continue; | |
552 | ||
553 | amdgpu_vm_bo_invalidate(adev, bo); | |
554 | } | |
d38ceaf9 AD |
555 | } |
556 | ||
b495bd3a | 557 | return r; |
d38ceaf9 AD |
558 | } |
559 | ||
560 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
561 | struct amdgpu_cs_parser *parser) | |
562 | { | |
563 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
564 | struct amdgpu_vm *vm = &fpriv->vm; | |
565 | struct amdgpu_ring *ring; | |
566 | int i, r; | |
567 | ||
568 | if (parser->num_ibs == 0) | |
569 | return 0; | |
570 | ||
571 | /* Only for UVD/VCE VM emulation */ | |
572 | for (i = 0; i < parser->num_ibs; i++) { | |
573 | ring = parser->ibs[i].ring; | |
574 | if (ring->funcs->parse_cs) { | |
575 | r = amdgpu_ring_parse_cs(ring, parser, i); | |
576 | if (r) | |
577 | return r; | |
578 | } | |
579 | } | |
580 | ||
d38ceaf9 | 581 | r = amdgpu_bo_vm_update_pte(parser, vm); |
984810fc CK |
582 | if (!r) |
583 | amdgpu_cs_sync_rings(parser); | |
d38ceaf9 | 584 | |
d38ceaf9 AD |
585 | return r; |
586 | } | |
587 | ||
588 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
589 | { | |
590 | if (r == -EDEADLK) { | |
591 | r = amdgpu_gpu_reset(adev); | |
592 | if (!r) | |
593 | r = -EAGAIN; | |
594 | } | |
595 | return r; | |
596 | } | |
597 | ||
598 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
599 | struct amdgpu_cs_parser *parser) | |
600 | { | |
601 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
602 | struct amdgpu_vm *vm = &fpriv->vm; | |
603 | int i, j; | |
604 | int r; | |
605 | ||
606 | for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { | |
607 | struct amdgpu_cs_chunk *chunk; | |
608 | struct amdgpu_ib *ib; | |
609 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 610 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
611 | |
612 | chunk = &parser->chunks[i]; | |
613 | ib = &parser->ibs[j]; | |
614 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
615 | ||
616 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
617 | continue; | |
618 | ||
d38ceaf9 AD |
619 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
620 | chunk_ib->ip_instance, chunk_ib->ring, | |
621 | &ring); | |
3ccec53c | 622 | if (r) |
d38ceaf9 | 623 | return r; |
d38ceaf9 AD |
624 | |
625 | if (ring->funcs->parse_cs) { | |
4802ce11 | 626 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 627 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
628 | uint64_t offset; |
629 | uint8_t *kptr; | |
3ccec53c | 630 | |
4802ce11 CK |
631 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
632 | &aobj); | |
3ccec53c MO |
633 | if (!aobj) { |
634 | DRM_ERROR("IB va_start is invalid\n"); | |
635 | return -EINVAL; | |
d38ceaf9 AD |
636 | } |
637 | ||
4802ce11 CK |
638 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
639 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
640 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
3ccec53c | 644 | /* the IB should be reserved at this point */ |
4802ce11 | 645 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 646 | if (r) { |
d38ceaf9 AD |
647 | return r; |
648 | } | |
649 | ||
4802ce11 CK |
650 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
651 | kptr += chunk_ib->va_start - offset; | |
652 | ||
d38ceaf9 AD |
653 | r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); |
654 | if (r) { | |
655 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
656 | return r; |
657 | } | |
658 | ||
659 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
660 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 AD |
661 | } else { |
662 | r = amdgpu_ib_get(ring, vm, 0, ib); | |
663 | if (r) { | |
664 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
665 | return r; |
666 | } | |
667 | ||
668 | ib->gpu_addr = chunk_ib->va_start; | |
669 | } | |
d38ceaf9 | 670 | |
3ccec53c | 671 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 672 | ib->flags = chunk_ib->flags; |
3cb485f3 | 673 | ib->ctx = parser->ctx; |
d38ceaf9 AD |
674 | j++; |
675 | } | |
676 | ||
677 | if (!parser->num_ibs) | |
678 | return 0; | |
679 | ||
680 | /* add GDS resources to first IB */ | |
681 | if (parser->bo_list) { | |
682 | struct amdgpu_bo *gds = parser->bo_list->gds_obj; | |
683 | struct amdgpu_bo *gws = parser->bo_list->gws_obj; | |
684 | struct amdgpu_bo *oa = parser->bo_list->oa_obj; | |
685 | struct amdgpu_ib *ib = &parser->ibs[0]; | |
686 | ||
687 | if (gds) { | |
688 | ib->gds_base = amdgpu_bo_gpu_offset(gds); | |
689 | ib->gds_size = amdgpu_bo_size(gds); | |
690 | } | |
691 | if (gws) { | |
692 | ib->gws_base = amdgpu_bo_gpu_offset(gws); | |
693 | ib->gws_size = amdgpu_bo_size(gws); | |
694 | } | |
695 | if (oa) { | |
696 | ib->oa_base = amdgpu_bo_gpu_offset(oa); | |
697 | ib->oa_size = amdgpu_bo_size(oa); | |
698 | } | |
699 | } | |
d38ceaf9 AD |
700 | /* wrap the last IB with user fence */ |
701 | if (parser->uf.bo) { | |
702 | struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; | |
703 | ||
704 | /* UVD & VCE fw doesn't support user fences */ | |
705 | if (ib->ring->type == AMDGPU_RING_TYPE_UVD || | |
706 | ib->ring->type == AMDGPU_RING_TYPE_VCE) | |
707 | return -EINVAL; | |
708 | ||
709 | ib->user = &parser->uf; | |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
2b48d323 CK |
715 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
716 | struct amdgpu_cs_parser *p) | |
717 | { | |
76a1ea61 | 718 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
719 | struct amdgpu_ib *ib; |
720 | int i, j, r; | |
721 | ||
722 | if (!p->num_ibs) | |
723 | return 0; | |
724 | ||
725 | /* Add dependencies to first IB */ | |
726 | ib = &p->ibs[0]; | |
727 | for (i = 0; i < p->nchunks; ++i) { | |
728 | struct drm_amdgpu_cs_chunk_dep *deps; | |
729 | struct amdgpu_cs_chunk *chunk; | |
730 | unsigned num_deps; | |
731 | ||
732 | chunk = &p->chunks[i]; | |
733 | ||
734 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
735 | continue; | |
736 | ||
737 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
738 | num_deps = chunk->length_dw * 4 / | |
739 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
740 | ||
741 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 742 | struct amdgpu_ring *ring; |
76a1ea61 | 743 | struct amdgpu_ctx *ctx; |
21c16bf6 | 744 | struct fence *fence; |
2b48d323 CK |
745 | |
746 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
747 | deps[j].ip_instance, | |
748 | deps[j].ring, &ring); | |
749 | if (r) | |
750 | return r; | |
751 | ||
76a1ea61 CK |
752 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
753 | if (ctx == NULL) | |
754 | return -EINVAL; | |
755 | ||
21c16bf6 CK |
756 | fence = amdgpu_ctx_get_fence(ctx, ring, |
757 | deps[j].handle); | |
758 | if (IS_ERR(fence)) { | |
759 | r = PTR_ERR(fence); | |
76a1ea61 | 760 | amdgpu_ctx_put(ctx); |
2b48d323 | 761 | return r; |
91e1a520 | 762 | |
21c16bf6 CK |
763 | } else if (fence) { |
764 | r = amdgpu_sync_fence(adev, &ib->sync, fence); | |
765 | fence_put(fence); | |
766 | amdgpu_ctx_put(ctx); | |
767 | if (r) | |
768 | return r; | |
769 | } | |
2b48d323 CK |
770 | } |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
4c7eb91c | 776 | static int amdgpu_cs_free_job(struct amdgpu_job *job) |
bb977d37 CZ |
777 | { |
778 | int i; | |
4c7eb91c JZ |
779 | if (job->ibs) |
780 | for (i = 0; i < job->num_ibs; i++) | |
781 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
782 | kfree(job->ibs); | |
783 | if (job->uf.bo) | |
784 | drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base); | |
bb977d37 CZ |
785 | return 0; |
786 | } | |
787 | ||
049fc527 CZ |
788 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
789 | { | |
790 | struct amdgpu_device *adev = dev->dev_private; | |
791 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 792 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
793 | bool reserved_buffers = false; |
794 | int i, r; | |
049fc527 | 795 | |
0c418f10 | 796 | if (!adev->accel_working) |
049fc527 | 797 | return -EBUSY; |
2b48d323 | 798 | |
7e52a81c CK |
799 | parser.adev = adev; |
800 | parser.filp = filp; | |
801 | ||
802 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 803 | if (r) { |
049fc527 | 804 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 805 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
806 | r = amdgpu_cs_handle_lockup(adev, r); |
807 | return r; | |
808 | } | |
7e52a81c | 809 | r = amdgpu_cs_parser_relocs(&parser); |
26a6980c CK |
810 | if (r == -ENOMEM) |
811 | DRM_ERROR("Not enough memory for command submission!\n"); | |
812 | else if (r && r != -ERESTARTSYS) | |
813 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
814 | else if (!r) { | |
815 | reserved_buffers = true; | |
7e52a81c | 816 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
817 | } |
818 | ||
819 | if (!r) { | |
7e52a81c | 820 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
821 | if (r) |
822 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
823 | } | |
824 | ||
825 | if (r) | |
826 | goto out; | |
827 | ||
7e52a81c CK |
828 | for (i = 0; i < parser.num_ibs; i++) |
829 | trace_amdgpu_cs(&parser, i); | |
26a6980c | 830 | |
7e52a81c | 831 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
832 | if (r) |
833 | goto out; | |
834 | ||
7e52a81c | 835 | if (amdgpu_enable_scheduler && parser.num_ibs) { |
7e52a81c | 836 | struct amdgpu_ring * ring = parser.ibs->ring; |
e2840221 CK |
837 | struct amd_sched_fence *fence; |
838 | struct amdgpu_job *job; | |
7e52a81c | 839 | |
bb977d37 | 840 | job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); |
4cfdcd9c DC |
841 | if (!job) { |
842 | r = -ENOMEM; | |
843 | goto out; | |
844 | } | |
7e52a81c | 845 | |
4f839a24 | 846 | job->base.sched = &ring->sched; |
7e52a81c CK |
847 | job->base.s_entity = &parser.ctx->rings[ring->idx].entity; |
848 | job->adev = parser.adev; | |
e2840221 CK |
849 | job->owner = parser.filp; |
850 | job->free_job = amdgpu_cs_free_job; | |
851 | ||
5d82730a CK |
852 | job->ibs = parser.ibs; |
853 | job->num_ibs = parser.num_ibs; | |
854 | parser.ibs = NULL; | |
855 | parser.num_ibs = 0; | |
856 | ||
bb977d37 | 857 | if (job->ibs[job->num_ibs - 1].user) { |
7e52a81c | 858 | job->uf = parser.uf; |
bb977d37 | 859 | job->ibs[job->num_ibs - 1].user = &job->uf; |
7e52a81c | 860 | parser.uf.bo = NULL; |
bb977d37 CZ |
861 | } |
862 | ||
e2840221 CK |
863 | fence = amd_sched_fence_create(job->base.s_entity, |
864 | parser.filp); | |
865 | if (!fence) { | |
866 | r = -ENOMEM; | |
bb977d37 CZ |
867 | amdgpu_cs_free_job(job); |
868 | kfree(job); | |
f556cb0c CZ |
869 | goto out; |
870 | } | |
e2840221 | 871 | job->base.s_fence = fence; |
984810fc | 872 | parser.fence = fence_get(&fence->base); |
e2840221 CK |
873 | |
874 | cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring, | |
875 | &fence->base); | |
e4a58a28 | 876 | job->ibs[job->num_ibs - 1].sequence = cs->out.handle; |
eb98d1c5 | 877 | |
7034decf | 878 | trace_amdgpu_cs_ioctl(job); |
e2840221 CK |
879 | amd_sched_entity_push_job(&job->base); |
880 | ||
984810fc CK |
881 | } else { |
882 | struct amdgpu_fence *fence; | |
e2840221 | 883 | |
984810fc CK |
884 | r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs, |
885 | parser.filp); | |
886 | fence = parser.ibs[parser.num_ibs - 1].fence; | |
887 | parser.fence = fence_get(&fence->base); | |
888 | cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence; | |
d38ceaf9 AD |
889 | } |
890 | ||
d38ceaf9 | 891 | out: |
7e52a81c | 892 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
893 | r = amdgpu_cs_handle_lockup(adev, r); |
894 | return r; | |
895 | } | |
896 | ||
897 | /** | |
898 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
899 | * | |
900 | * @dev: drm device | |
901 | * @data: data from userspace | |
902 | * @filp: file private | |
903 | * | |
904 | * Wait for the command submission identified by handle to finish. | |
905 | */ | |
906 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
907 | struct drm_file *filp) | |
908 | { | |
909 | union drm_amdgpu_wait_cs *wait = data; | |
910 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 911 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 912 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 913 | struct amdgpu_ctx *ctx; |
21c16bf6 | 914 | struct fence *fence; |
d38ceaf9 AD |
915 | long r; |
916 | ||
21c16bf6 CK |
917 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
918 | wait->in.ring, &ring); | |
919 | if (r) | |
920 | return r; | |
921 | ||
66b3cf2a JZ |
922 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
923 | if (ctx == NULL) | |
924 | return -EINVAL; | |
d38ceaf9 | 925 | |
4b559c90 CZ |
926 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
927 | if (IS_ERR(fence)) | |
928 | r = PTR_ERR(fence); | |
929 | else if (fence) { | |
930 | r = fence_wait_timeout(fence, true, timeout); | |
931 | fence_put(fence); | |
932 | } else | |
933 | r = 1; | |
049fc527 | 934 | |
66b3cf2a | 935 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
936 | if (r < 0) |
937 | return r; | |
938 | ||
939 | memset(wait, 0, sizeof(*wait)); | |
940 | wait->out.status = (r == 0); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
945 | /** | |
946 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
947 | * | |
948 | * @parser: command submission parser context | |
949 | * @addr: VM address | |
950 | * @bo: resulting BO of the mapping found | |
951 | * | |
952 | * Search the buffer objects in the command submission context for a certain | |
953 | * virtual memory address. Returns allocation structure when found, NULL | |
954 | * otherwise. | |
955 | */ | |
956 | struct amdgpu_bo_va_mapping * | |
957 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
958 | uint64_t addr, struct amdgpu_bo **bo) | |
959 | { | |
960 | struct amdgpu_bo_list_entry *reloc; | |
961 | struct amdgpu_bo_va_mapping *mapping; | |
962 | ||
963 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
964 | ||
965 | list_for_each_entry(reloc, &parser->validated, tv.head) { | |
966 | if (!reloc->bo_va) | |
967 | continue; | |
968 | ||
7fc11959 CK |
969 | list_for_each_entry(mapping, &reloc->bo_va->valids, list) { |
970 | if (mapping->it.start > addr || | |
971 | addr > mapping->it.last) | |
972 | continue; | |
973 | ||
974 | *bo = reloc->bo_va->bo; | |
975 | return mapping; | |
976 | } | |
977 | ||
978 | list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { | |
d38ceaf9 AD |
979 | if (mapping->it.start > addr || |
980 | addr > mapping->it.last) | |
981 | continue; | |
982 | ||
983 | *bo = reloc->bo_va->bo; | |
984 | return mapping; | |
985 | } | |
986 | } | |
987 | ||
988 | return NULL; | |
989 | } |