Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
27 | #include <linux/list_sort.h> | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | #define AMDGPU_CS_MAX_PRIORITY 32u | |
34 | #define AMDGPU_CS_NUM_BUCKETS (AMDGPU_CS_MAX_PRIORITY + 1) | |
35 | ||
36 | /* This is based on the bucket sort with O(n) time complexity. | |
37 | * An item with priority "i" is added to bucket[i]. The lists are then | |
38 | * concatenated in descending order. | |
39 | */ | |
40 | struct amdgpu_cs_buckets { | |
41 | struct list_head bucket[AMDGPU_CS_NUM_BUCKETS]; | |
42 | }; | |
43 | ||
44 | static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b) | |
45 | { | |
46 | unsigned i; | |
47 | ||
48 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) | |
49 | INIT_LIST_HEAD(&b->bucket[i]); | |
50 | } | |
51 | ||
52 | static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b, | |
53 | struct list_head *item, unsigned priority) | |
54 | { | |
55 | /* Since buffers which appear sooner in the relocation list are | |
56 | * likely to be used more often than buffers which appear later | |
57 | * in the list, the sort mustn't change the ordering of buffers | |
58 | * with the same priority, i.e. it must be stable. | |
59 | */ | |
60 | list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]); | |
61 | } | |
62 | ||
63 | static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b, | |
64 | struct list_head *out_list) | |
65 | { | |
66 | unsigned i; | |
67 | ||
68 | /* Connect the sorted buckets in the output list. */ | |
69 | for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) { | |
70 | list_splice(&b->bucket[i], out_list); | |
71 | } | |
72 | } | |
73 | ||
74 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, | |
75 | u32 ip_instance, u32 ring, | |
76 | struct amdgpu_ring **out_ring) | |
77 | { | |
78 | /* Right now all IPs have only one instance - multiple rings. */ | |
79 | if (ip_instance != 0) { | |
80 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | switch (ip_type) { | |
85 | default: | |
86 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
87 | return -EINVAL; | |
88 | case AMDGPU_HW_IP_GFX: | |
89 | if (ring < adev->gfx.num_gfx_rings) { | |
90 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
91 | } else { | |
92 | DRM_ERROR("only %d gfx rings are supported now\n", | |
93 | adev->gfx.num_gfx_rings); | |
94 | return -EINVAL; | |
95 | } | |
96 | break; | |
97 | case AMDGPU_HW_IP_COMPUTE: | |
98 | if (ring < adev->gfx.num_compute_rings) { | |
99 | *out_ring = &adev->gfx.compute_ring[ring]; | |
100 | } else { | |
101 | DRM_ERROR("only %d compute rings are supported now\n", | |
102 | adev->gfx.num_compute_rings); | |
103 | return -EINVAL; | |
104 | } | |
105 | break; | |
106 | case AMDGPU_HW_IP_DMA: | |
107 | if (ring < 2) { | |
108 | *out_ring = &adev->sdma[ring].ring; | |
109 | } else { | |
110 | DRM_ERROR("only two SDMA rings are supported\n"); | |
111 | return -EINVAL; | |
112 | } | |
113 | break; | |
114 | case AMDGPU_HW_IP_UVD: | |
115 | *out_ring = &adev->uvd.ring; | |
116 | break; | |
117 | case AMDGPU_HW_IP_VCE: | |
118 | if (ring < 2){ | |
119 | *out_ring = &adev->vce.ring[ring]; | |
120 | } else { | |
121 | DRM_ERROR("only two VCE rings are supported\n"); | |
122 | return -EINVAL; | |
123 | } | |
124 | break; | |
125 | } | |
126 | return 0; | |
127 | } | |
128 | ||
049fc527 CZ |
129 | struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, |
130 | struct drm_file *filp, | |
131 | struct amdgpu_ctx *ctx, | |
132 | struct amdgpu_ib *ibs, | |
133 | uint32_t num_ibs) | |
134 | { | |
135 | struct amdgpu_cs_parser *parser; | |
136 | int i; | |
137 | ||
138 | parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL); | |
139 | if (!parser) | |
140 | return NULL; | |
141 | ||
142 | parser->adev = adev; | |
143 | parser->filp = filp; | |
144 | parser->ctx = ctx; | |
145 | parser->ibs = ibs; | |
146 | parser->num_ibs = num_ibs; | |
049fc527 CZ |
147 | for (i = 0; i < num_ibs; i++) |
148 | ibs[i].ctx = ctx; | |
149 | ||
150 | return parser; | |
151 | } | |
152 | ||
d38ceaf9 AD |
153 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
154 | { | |
155 | union drm_amdgpu_cs *cs = data; | |
156 | uint64_t *chunk_array_user; | |
157 | uint64_t *chunk_array = NULL; | |
158 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
049fc527 | 159 | struct amdgpu_bo_list *bo_list = NULL; |
d38ceaf9 AD |
160 | unsigned size, i; |
161 | int r = 0; | |
162 | ||
163 | if (!cs->in.num_chunks) | |
164 | goto out; | |
165 | ||
3cb485f3 CK |
166 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
167 | if (!p->ctx) { | |
168 | r = -EINVAL; | |
169 | goto out; | |
170 | } | |
049fc527 | 171 | bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); |
1939e3e2 | 172 | if (!amdgpu_enable_scheduler) |
049fc527 | 173 | p->bo_list = bo_list; |
1939e3e2 | 174 | else { |
175 | if (bo_list && !bo_list->has_userptr) { | |
176 | p->bo_list = amdgpu_bo_list_clone(bo_list); | |
177 | amdgpu_bo_list_put(bo_list); | |
178 | if (!p->bo_list) | |
179 | return -ENOMEM; | |
180 | } else if (bo_list && bo_list->has_userptr) | |
181 | p->bo_list = bo_list; | |
182 | else | |
183 | p->bo_list = NULL; | |
184 | } | |
d38ceaf9 AD |
185 | |
186 | /* get chunks */ | |
187 | INIT_LIST_HEAD(&p->validated); | |
e60b344f | 188 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); |
d38ceaf9 AD |
189 | if (chunk_array == NULL) { |
190 | r = -ENOMEM; | |
191 | goto out; | |
192 | } | |
193 | ||
e60b344f | 194 | chunk_array_user = (uint64_t __user *)(cs->in.chunks); |
d38ceaf9 AD |
195 | if (copy_from_user(chunk_array, chunk_array_user, |
196 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
197 | r = -EFAULT; | |
198 | goto out; | |
199 | } | |
200 | ||
201 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 202 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 AD |
203 | GFP_KERNEL); |
204 | if (p->chunks == NULL) { | |
205 | r = -ENOMEM; | |
206 | goto out; | |
207 | } | |
208 | ||
209 | for (i = 0; i < p->nchunks; i++) { | |
210 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
211 | struct drm_amdgpu_cs_chunk user_chunk; | |
212 | uint32_t __user *cdata; | |
213 | ||
e60b344f | 214 | chunk_ptr = (void __user *)chunk_array[i]; |
d38ceaf9 AD |
215 | if (copy_from_user(&user_chunk, chunk_ptr, |
216 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
217 | r = -EFAULT; | |
218 | goto out; | |
219 | } | |
220 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
221 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
222 | |
223 | size = p->chunks[i].length_dw; | |
e60b344f | 224 | cdata = (void __user *)user_chunk.chunk_data; |
d38ceaf9 AD |
225 | p->chunks[i].user_ptr = cdata; |
226 | ||
227 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
228 | if (p->chunks[i].kdata == NULL) { | |
229 | r = -ENOMEM; | |
230 | goto out; | |
231 | } | |
232 | size *= sizeof(uint32_t); | |
233 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
234 | r = -EFAULT; | |
235 | goto out; | |
236 | } | |
237 | ||
9a5e8fb1 CK |
238 | switch (p->chunks[i].chunk_id) { |
239 | case AMDGPU_CHUNK_ID_IB: | |
240 | p->num_ibs++; | |
241 | break; | |
242 | ||
243 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 AD |
244 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
245 | if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) { | |
246 | uint32_t handle; | |
247 | struct drm_gem_object *gobj; | |
248 | struct drm_amdgpu_cs_chunk_fence *fence_data; | |
249 | ||
250 | fence_data = (void *)p->chunks[i].kdata; | |
251 | handle = fence_data->handle; | |
252 | gobj = drm_gem_object_lookup(p->adev->ddev, | |
253 | p->filp, handle); | |
254 | if (gobj == NULL) { | |
255 | r = -EINVAL; | |
256 | goto out; | |
257 | } | |
258 | ||
259 | p->uf.bo = gem_to_amdgpu_bo(gobj); | |
260 | p->uf.offset = fence_data->offset; | |
261 | } else { | |
262 | r = -EINVAL; | |
263 | goto out; | |
264 | } | |
9a5e8fb1 CK |
265 | break; |
266 | ||
2b48d323 CK |
267 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
268 | break; | |
269 | ||
9a5e8fb1 CK |
270 | default: |
271 | r = -EINVAL; | |
272 | goto out; | |
d38ceaf9 AD |
273 | } |
274 | } | |
275 | ||
e60b344f | 276 | |
277 | p->ibs = kmalloc_array(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL); | |
278 | if (!p->ibs) | |
d38ceaf9 | 279 | r = -ENOMEM; |
d38ceaf9 | 280 | |
d38ceaf9 AD |
281 | out: |
282 | kfree(chunk_array); | |
283 | return r; | |
284 | } | |
285 | ||
286 | /* Returns how many bytes TTM can move per IB. | |
287 | */ | |
288 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
289 | { | |
290 | u64 real_vram_size = adev->mc.real_vram_size; | |
291 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
292 | ||
293 | /* This function is based on the current VRAM usage. | |
294 | * | |
295 | * - If all of VRAM is free, allow relocating the number of bytes that | |
296 | * is equal to 1/4 of the size of VRAM for this IB. | |
297 | ||
298 | * - If more than one half of VRAM is occupied, only allow relocating | |
299 | * 1 MB of data for this IB. | |
300 | * | |
301 | * - From 0 to one half of used VRAM, the threshold decreases | |
302 | * linearly. | |
303 | * __________________ | |
304 | * 1/4 of -|\ | | |
305 | * VRAM | \ | | |
306 | * | \ | | |
307 | * | \ | | |
308 | * | \ | | |
309 | * | \ | | |
310 | * | \ | | |
311 | * | \________|1 MB | |
312 | * |----------------| | |
313 | * VRAM 0 % 100 % | |
314 | * used used | |
315 | * | |
316 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
317 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
318 | * can be moved as long as the threshold isn't crossed before | |
319 | * the relocation takes place. We don't want to disable buffer | |
320 | * relocations completely. | |
321 | * | |
322 | * The idea is that buffers should be placed in VRAM at creation time | |
323 | * and TTM should only do a minimum number of relocations during | |
324 | * command submission. In practice, you need to submit at least | |
325 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
326 | * | |
327 | * Also, things can get pretty crazy under memory pressure and actual | |
328 | * VRAM usage can change a lot, so playing safe even at 50% does | |
329 | * consistently increase performance. | |
330 | */ | |
331 | ||
332 | u64 half_vram = real_vram_size >> 1; | |
333 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
334 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
335 | return max(bytes_moved_threshold, 1024*1024ull); | |
336 | } | |
337 | ||
338 | int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p) | |
339 | { | |
340 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
341 | struct amdgpu_vm *vm = &fpriv->vm; | |
342 | struct amdgpu_device *adev = p->adev; | |
343 | struct amdgpu_bo_list_entry *lobj; | |
344 | struct list_head duplicates; | |
345 | struct amdgpu_bo *bo; | |
346 | u64 bytes_moved = 0, initial_bytes_moved; | |
347 | u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev); | |
348 | int r; | |
349 | ||
350 | INIT_LIST_HEAD(&duplicates); | |
351 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates); | |
352 | if (unlikely(r != 0)) { | |
353 | return r; | |
354 | } | |
355 | ||
356 | list_for_each_entry(lobj, &p->validated, tv.head) { | |
357 | bo = lobj->robj; | |
358 | if (!bo->pin_count) { | |
359 | u32 domain = lobj->prefered_domains; | |
360 | u32 current_domain = | |
361 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
362 | ||
363 | /* Check if this buffer will be moved and don't move it | |
364 | * if we have moved too many buffers for this IB already. | |
365 | * | |
366 | * Note that this allows moving at least one buffer of | |
367 | * any size, because it doesn't take the current "bo" | |
368 | * into account. We don't want to disallow buffer moves | |
369 | * completely. | |
370 | */ | |
371 | if (current_domain != AMDGPU_GEM_DOMAIN_CPU && | |
372 | (domain & current_domain) == 0 && /* will be moved */ | |
373 | bytes_moved > bytes_moved_threshold) { | |
374 | /* don't move it */ | |
375 | domain = current_domain; | |
376 | } | |
377 | ||
378 | retry: | |
379 | amdgpu_ttm_placement_from_domain(bo, domain); | |
380 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); | |
381 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
382 | bytes_moved += atomic64_read(&adev->num_bytes_moved) - | |
383 | initial_bytes_moved; | |
384 | ||
385 | if (unlikely(r)) { | |
386 | if (r != -ERESTARTSYS && domain != lobj->allowed_domains) { | |
387 | domain = lobj->allowed_domains; | |
388 | goto retry; | |
389 | } | |
390 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
391 | return r; | |
392 | } | |
393 | } | |
394 | lobj->bo_va = amdgpu_vm_bo_find(vm, bo); | |
395 | } | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p) | |
400 | { | |
401 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
402 | struct amdgpu_cs_buckets buckets; | |
840d5144 | 403 | bool need_mmap_lock = false; |
d38ceaf9 AD |
404 | int i, r; |
405 | ||
840d5144 | 406 | if (p->bo_list) { |
407 | need_mmap_lock = p->bo_list->has_userptr; | |
408 | amdgpu_cs_buckets_init(&buckets); | |
409 | for (i = 0; i < p->bo_list->num_entries; i++) | |
410 | amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head, | |
411 | p->bo_list->array[i].priority); | |
d38ceaf9 | 412 | |
840d5144 | 413 | amdgpu_cs_buckets_get_list(&buckets, &p->validated); |
414 | } | |
d38ceaf9 | 415 | |
d38ceaf9 AD |
416 | p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm, |
417 | &p->validated); | |
418 | ||
d38ceaf9 AD |
419 | if (need_mmap_lock) |
420 | down_read(¤t->mm->mmap_sem); | |
421 | ||
422 | r = amdgpu_cs_list_validate(p); | |
423 | ||
424 | if (need_mmap_lock) | |
425 | up_read(¤t->mm->mmap_sem); | |
426 | ||
427 | return r; | |
428 | } | |
429 | ||
430 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
431 | { | |
432 | struct amdgpu_bo_list_entry *e; | |
433 | int r; | |
434 | ||
435 | list_for_each_entry(e, &p->validated, tv.head) { | |
436 | struct reservation_object *resv = e->robj->tbo.resv; | |
437 | r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp); | |
438 | ||
439 | if (r) | |
440 | return r; | |
441 | } | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static int cmp_size_smaller_first(void *priv, struct list_head *a, | |
446 | struct list_head *b) | |
447 | { | |
448 | struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head); | |
449 | struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head); | |
450 | ||
451 | /* Sort A before B if A is smaller. */ | |
452 | return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; | |
453 | } | |
454 | ||
049fc527 CZ |
455 | static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff) |
456 | { | |
d38ceaf9 AD |
457 | if (!error) { |
458 | /* Sort the buffer list from the smallest to largest buffer, | |
459 | * which affects the order of buffers in the LRU list. | |
460 | * This assures that the smallest buffers are added first | |
461 | * to the LRU list, so they are likely to be later evicted | |
462 | * first, instead of large buffers whose eviction is more | |
463 | * expensive. | |
464 | * | |
465 | * This slightly lowers the number of bytes moved by TTM | |
466 | * per frame under memory pressure. | |
467 | */ | |
468 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); | |
469 | ||
470 | ttm_eu_fence_buffer_objects(&parser->ticket, | |
471 | &parser->validated, | |
472 | &parser->ibs[parser->num_ibs-1].fence->base); | |
473 | } else if (backoff) { | |
474 | ttm_eu_backoff_reservation(&parser->ticket, | |
475 | &parser->validated); | |
476 | } | |
049fc527 | 477 | } |
d38ceaf9 | 478 | |
049fc527 CZ |
479 | static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser) |
480 | { | |
481 | unsigned i; | |
3cb485f3 CK |
482 | if (parser->ctx) |
483 | amdgpu_ctx_put(parser->ctx); | |
049fc527 | 484 | if (parser->bo_list) { |
1939e3e2 | 485 | if (amdgpu_enable_scheduler && !parser->bo_list->has_userptr) |
049fc527 CZ |
486 | amdgpu_bo_list_free(parser->bo_list); |
487 | else | |
488 | amdgpu_bo_list_put(parser->bo_list); | |
489 | } | |
d38ceaf9 AD |
490 | drm_free_large(parser->vm_bos); |
491 | for (i = 0; i < parser->nchunks; i++) | |
492 | drm_free_large(parser->chunks[i].kdata); | |
493 | kfree(parser->chunks); | |
049fc527 | 494 | if (!amdgpu_enable_scheduler) |
bb977d37 CZ |
495 | { |
496 | if (parser->ibs) | |
497 | for (i = 0; i < parser->num_ibs; i++) | |
498 | amdgpu_ib_free(parser->adev, &parser->ibs[i]); | |
499 | kfree(parser->ibs); | |
500 | if (parser->uf.bo) | |
501 | drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); | |
502 | } | |
503 | ||
504 | kfree(parser); | |
d38ceaf9 AD |
505 | } |
506 | ||
351dba73 CK |
507 | /** |
508 | * cs_parser_fini() - clean parser states | |
509 | * @parser: parser structure holding parsing context. | |
510 | * @error: error number | |
511 | * | |
512 | * If error is set than unvalidate buffer, otherwise just free memory | |
513 | * used by parsing context. | |
514 | **/ | |
515 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
516 | { | |
517 | amdgpu_cs_parser_fini_early(parser, error, backoff); | |
518 | amdgpu_cs_parser_fini_late(parser); | |
519 | } | |
520 | ||
d38ceaf9 AD |
521 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, |
522 | struct amdgpu_vm *vm) | |
523 | { | |
524 | struct amdgpu_device *adev = p->adev; | |
525 | struct amdgpu_bo_va *bo_va; | |
526 | struct amdgpu_bo *bo; | |
527 | int i, r; | |
528 | ||
529 | r = amdgpu_vm_update_page_directory(adev, vm); | |
530 | if (r) | |
531 | return r; | |
532 | ||
05906dec BN |
533 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence); |
534 | if (r) | |
535 | return r; | |
536 | ||
d38ceaf9 AD |
537 | r = amdgpu_vm_clear_freed(adev, vm); |
538 | if (r) | |
539 | return r; | |
540 | ||
541 | if (p->bo_list) { | |
542 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
543 | struct fence *f; |
544 | ||
d38ceaf9 AD |
545 | /* ignore duplicates */ |
546 | bo = p->bo_list->array[i].robj; | |
547 | if (!bo) | |
548 | continue; | |
549 | ||
550 | bo_va = p->bo_list->array[i].bo_va; | |
551 | if (bo_va == NULL) | |
552 | continue; | |
553 | ||
554 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
555 | if (r) | |
556 | return r; | |
557 | ||
bb1e38a4 | 558 | f = bo_va->last_pt_update; |
91e1a520 CK |
559 | r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f); |
560 | if (r) | |
561 | return r; | |
d38ceaf9 AD |
562 | } |
563 | } | |
564 | ||
cfe2c978 | 565 | return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); |
d38ceaf9 AD |
566 | } |
567 | ||
568 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
569 | struct amdgpu_cs_parser *parser) | |
570 | { | |
571 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
572 | struct amdgpu_vm *vm = &fpriv->vm; | |
573 | struct amdgpu_ring *ring; | |
574 | int i, r; | |
575 | ||
576 | if (parser->num_ibs == 0) | |
577 | return 0; | |
578 | ||
579 | /* Only for UVD/VCE VM emulation */ | |
580 | for (i = 0; i < parser->num_ibs; i++) { | |
581 | ring = parser->ibs[i].ring; | |
582 | if (ring->funcs->parse_cs) { | |
583 | r = amdgpu_ring_parse_cs(ring, parser, i); | |
584 | if (r) | |
585 | return r; | |
586 | } | |
587 | } | |
588 | ||
589 | mutex_lock(&vm->mutex); | |
590 | r = amdgpu_bo_vm_update_pte(parser, vm); | |
591 | if (r) { | |
592 | goto out; | |
593 | } | |
594 | amdgpu_cs_sync_rings(parser); | |
049fc527 CZ |
595 | if (!amdgpu_enable_scheduler) |
596 | r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs, | |
597 | parser->filp); | |
d38ceaf9 AD |
598 | |
599 | out: | |
600 | mutex_unlock(&vm->mutex); | |
601 | return r; | |
602 | } | |
603 | ||
604 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
605 | { | |
606 | if (r == -EDEADLK) { | |
607 | r = amdgpu_gpu_reset(adev); | |
608 | if (!r) | |
609 | r = -EAGAIN; | |
610 | } | |
611 | return r; | |
612 | } | |
613 | ||
614 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
615 | struct amdgpu_cs_parser *parser) | |
616 | { | |
617 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
618 | struct amdgpu_vm *vm = &fpriv->vm; | |
619 | int i, j; | |
620 | int r; | |
621 | ||
622 | for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) { | |
623 | struct amdgpu_cs_chunk *chunk; | |
624 | struct amdgpu_ib *ib; | |
625 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 626 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
627 | |
628 | chunk = &parser->chunks[i]; | |
629 | ib = &parser->ibs[j]; | |
630 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
631 | ||
632 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
633 | continue; | |
634 | ||
d38ceaf9 AD |
635 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
636 | chunk_ib->ip_instance, chunk_ib->ring, | |
637 | &ring); | |
3ccec53c | 638 | if (r) |
d38ceaf9 | 639 | return r; |
d38ceaf9 AD |
640 | |
641 | if (ring->funcs->parse_cs) { | |
4802ce11 | 642 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 643 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
644 | uint64_t offset; |
645 | uint8_t *kptr; | |
3ccec53c | 646 | |
4802ce11 CK |
647 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
648 | &aobj); | |
3ccec53c MO |
649 | if (!aobj) { |
650 | DRM_ERROR("IB va_start is invalid\n"); | |
651 | return -EINVAL; | |
d38ceaf9 AD |
652 | } |
653 | ||
4802ce11 CK |
654 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
655 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
656 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
657 | return -EINVAL; | |
658 | } | |
659 | ||
3ccec53c | 660 | /* the IB should be reserved at this point */ |
4802ce11 | 661 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 662 | if (r) { |
d38ceaf9 AD |
663 | return r; |
664 | } | |
665 | ||
4802ce11 CK |
666 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
667 | kptr += chunk_ib->va_start - offset; | |
668 | ||
d38ceaf9 AD |
669 | r = amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib); |
670 | if (r) { | |
671 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
672 | return r; |
673 | } | |
674 | ||
675 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
676 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 AD |
677 | } else { |
678 | r = amdgpu_ib_get(ring, vm, 0, ib); | |
679 | if (r) { | |
680 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
681 | return r; |
682 | } | |
683 | ||
684 | ib->gpu_addr = chunk_ib->va_start; | |
685 | } | |
d38ceaf9 | 686 | |
3ccec53c | 687 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 688 | ib->flags = chunk_ib->flags; |
3cb485f3 | 689 | ib->ctx = parser->ctx; |
d38ceaf9 AD |
690 | j++; |
691 | } | |
692 | ||
693 | if (!parser->num_ibs) | |
694 | return 0; | |
695 | ||
696 | /* add GDS resources to first IB */ | |
697 | if (parser->bo_list) { | |
698 | struct amdgpu_bo *gds = parser->bo_list->gds_obj; | |
699 | struct amdgpu_bo *gws = parser->bo_list->gws_obj; | |
700 | struct amdgpu_bo *oa = parser->bo_list->oa_obj; | |
701 | struct amdgpu_ib *ib = &parser->ibs[0]; | |
702 | ||
703 | if (gds) { | |
704 | ib->gds_base = amdgpu_bo_gpu_offset(gds); | |
705 | ib->gds_size = amdgpu_bo_size(gds); | |
706 | } | |
707 | if (gws) { | |
708 | ib->gws_base = amdgpu_bo_gpu_offset(gws); | |
709 | ib->gws_size = amdgpu_bo_size(gws); | |
710 | } | |
711 | if (oa) { | |
712 | ib->oa_base = amdgpu_bo_gpu_offset(oa); | |
713 | ib->oa_size = amdgpu_bo_size(oa); | |
714 | } | |
715 | } | |
d38ceaf9 AD |
716 | /* wrap the last IB with user fence */ |
717 | if (parser->uf.bo) { | |
718 | struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1]; | |
719 | ||
720 | /* UVD & VCE fw doesn't support user fences */ | |
721 | if (ib->ring->type == AMDGPU_RING_TYPE_UVD || | |
722 | ib->ring->type == AMDGPU_RING_TYPE_VCE) | |
723 | return -EINVAL; | |
724 | ||
725 | ib->user = &parser->uf; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
2b48d323 CK |
731 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
732 | struct amdgpu_cs_parser *p) | |
733 | { | |
76a1ea61 | 734 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
735 | struct amdgpu_ib *ib; |
736 | int i, j, r; | |
737 | ||
738 | if (!p->num_ibs) | |
739 | return 0; | |
740 | ||
741 | /* Add dependencies to first IB */ | |
742 | ib = &p->ibs[0]; | |
743 | for (i = 0; i < p->nchunks; ++i) { | |
744 | struct drm_amdgpu_cs_chunk_dep *deps; | |
745 | struct amdgpu_cs_chunk *chunk; | |
746 | unsigned num_deps; | |
747 | ||
748 | chunk = &p->chunks[i]; | |
749 | ||
750 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
751 | continue; | |
752 | ||
753 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
754 | num_deps = chunk->length_dw * 4 / | |
755 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
756 | ||
757 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 758 | struct amdgpu_ring *ring; |
76a1ea61 | 759 | struct amdgpu_ctx *ctx; |
21c16bf6 | 760 | struct fence *fence; |
2b48d323 CK |
761 | |
762 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
763 | deps[j].ip_instance, | |
764 | deps[j].ring, &ring); | |
765 | if (r) | |
766 | return r; | |
767 | ||
76a1ea61 CK |
768 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
769 | if (ctx == NULL) | |
770 | return -EINVAL; | |
771 | ||
21c16bf6 CK |
772 | fence = amdgpu_ctx_get_fence(ctx, ring, |
773 | deps[j].handle); | |
774 | if (IS_ERR(fence)) { | |
775 | r = PTR_ERR(fence); | |
76a1ea61 | 776 | amdgpu_ctx_put(ctx); |
2b48d323 | 777 | return r; |
91e1a520 | 778 | |
21c16bf6 CK |
779 | } else if (fence) { |
780 | r = amdgpu_sync_fence(adev, &ib->sync, fence); | |
781 | fence_put(fence); | |
782 | amdgpu_ctx_put(ctx); | |
783 | if (r) | |
784 | return r; | |
785 | } | |
2b48d323 CK |
786 | } |
787 | } | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
049fc527 | 792 | static int amdgpu_cs_parser_prepare_job(struct amdgpu_cs_parser *sched_job) |
d38ceaf9 | 793 | { |
dd01d071 | 794 | int r, i; |
049fc527 CZ |
795 | struct amdgpu_cs_parser *parser = sched_job; |
796 | struct amdgpu_device *adev = sched_job->adev; | |
dd01d071 | 797 | bool reserved_buffers = false; |
049fc527 | 798 | |
dd01d071 JZ |
799 | r = amdgpu_cs_parser_relocs(parser); |
800 | if (r) { | |
801 | if (r != -ERESTARTSYS) { | |
3ccec53c MO |
802 | if (r == -ENOMEM) |
803 | DRM_ERROR("Not enough memory for command submission!\n"); | |
804 | else | |
805 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
806 | } | |
2b48d323 CK |
807 | } |
808 | ||
809 | if (!r) { | |
3ccec53c | 810 | reserved_buffers = true; |
049fc527 | 811 | r = amdgpu_cs_ib_fill(adev, parser); |
d38ceaf9 | 812 | } |
21c16bf6 | 813 | if (!r) { |
049fc527 | 814 | r = amdgpu_cs_dependencies(adev, parser); |
21c16bf6 CK |
815 | if (r) |
816 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
817 | } | |
dd01d071 JZ |
818 | if (r) { |
819 | amdgpu_cs_parser_fini(parser, r, reserved_buffers); | |
820 | return r; | |
821 | } | |
049fc527 | 822 | |
dd01d071 JZ |
823 | for (i = 0; i < parser->num_ibs; i++) |
824 | trace_amdgpu_cs(parser, i); | |
049fc527 | 825 | |
dd01d071 JZ |
826 | r = amdgpu_cs_ib_vm_chunk(adev, parser); |
827 | return r; | |
049fc527 CZ |
828 | } |
829 | ||
830 | static struct amdgpu_ring *amdgpu_cs_parser_get_ring( | |
831 | struct amdgpu_device *adev, | |
832 | struct amdgpu_cs_parser *parser) | |
833 | { | |
834 | int i, r; | |
835 | ||
836 | struct amdgpu_cs_chunk *chunk; | |
837 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
838 | struct amdgpu_ring *ring; | |
839 | for (i = 0; i < parser->nchunks; i++) { | |
840 | chunk = &parser->chunks[i]; | |
841 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; | |
842 | ||
843 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
844 | continue; | |
845 | ||
846 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, | |
847 | chunk_ib->ip_instance, chunk_ib->ring, | |
848 | &ring); | |
849 | if (r) | |
850 | return NULL; | |
851 | break; | |
852 | } | |
853 | return ring; | |
854 | } | |
855 | ||
bb977d37 CZ |
856 | static int amdgpu_cs_free_job(struct amdgpu_job *sched_job) |
857 | { | |
858 | int i; | |
859 | amdgpu_ctx_put(sched_job->ctx); | |
860 | if (sched_job->ibs) | |
861 | for (i = 0; i < sched_job->num_ibs; i++) | |
862 | amdgpu_ib_free(sched_job->adev, &sched_job->ibs[i]); | |
863 | kfree(sched_job->ibs); | |
864 | if (sched_job->uf.bo) | |
865 | drm_gem_object_unreference_unlocked(&sched_job->uf.bo->gem_base); | |
866 | return 0; | |
867 | } | |
868 | ||
049fc527 CZ |
869 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
870 | { | |
871 | struct amdgpu_device *adev = dev->dev_private; | |
872 | union drm_amdgpu_cs *cs = data; | |
873 | struct amdgpu_cs_parser *parser; | |
874 | int r; | |
875 | ||
876 | down_read(&adev->exclusive_lock); | |
877 | if (!adev->accel_working) { | |
878 | up_read(&adev->exclusive_lock); | |
879 | return -EBUSY; | |
880 | } | |
2b48d323 | 881 | |
049fc527 CZ |
882 | parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); |
883 | if (!parser) | |
884 | return -ENOMEM; | |
885 | r = amdgpu_cs_parser_init(parser, data); | |
d38ceaf9 | 886 | if (r) { |
049fc527 CZ |
887 | DRM_ERROR("Failed to initialize parser !\n"); |
888 | amdgpu_cs_parser_fini(parser, r, false); | |
d38ceaf9 AD |
889 | up_read(&adev->exclusive_lock); |
890 | r = amdgpu_cs_handle_lockup(adev, r); | |
891 | return r; | |
892 | } | |
893 | ||
049fc527 | 894 | if (amdgpu_enable_scheduler && parser->num_ibs) { |
bb977d37 | 895 | struct amdgpu_job *job; |
049fc527 CZ |
896 | struct amdgpu_ring * ring = |
897 | amdgpu_cs_parser_get_ring(adev, parser); | |
c3b95d4f CZ |
898 | r = amdgpu_cs_parser_prepare_job(parser); |
899 | if (r) | |
900 | goto out; | |
bb977d37 CZ |
901 | job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); |
902 | if (!job) | |
903 | return -ENOMEM; | |
904 | job->base.sched = ring->scheduler; | |
905 | job->base.s_entity = &parser->ctx->rings[ring->idx].entity; | |
906 | job->adev = parser->adev; | |
907 | job->ibs = parser->ibs; | |
908 | job->num_ibs = parser->num_ibs; | |
909 | job->owner = parser->filp; | |
910 | job->ctx = amdgpu_ctx_get_ref(parser->ctx); | |
911 | mutex_init(&job->job_lock); | |
912 | if (job->ibs[job->num_ibs - 1].user) { | |
913 | memcpy(&job->uf, &parser->uf, | |
914 | sizeof(struct amdgpu_user_fence)); | |
915 | job->ibs[job->num_ibs - 1].user = &job->uf; | |
916 | } | |
917 | ||
918 | job->free_job = amdgpu_cs_free_job; | |
919 | mutex_lock(&job->job_lock); | |
920 | r = amd_sched_push_job((struct amd_sched_job *)job); | |
f556cb0c | 921 | if (r) { |
bb977d37 CZ |
922 | mutex_unlock(&job->job_lock); |
923 | amdgpu_cs_free_job(job); | |
924 | kfree(job); | |
f556cb0c CZ |
925 | goto out; |
926 | } | |
bb977d37 CZ |
927 | job->ibs[parser->num_ibs - 1].sequence = |
928 | amdgpu_ctx_add_fence(job->ctx, ring, | |
929 | &job->base.s_fence->base, | |
930 | job->base.s_fence->v_seq); | |
931 | cs->out.handle = job->base.s_fence->v_seq; | |
c3b95d4f CZ |
932 | list_sort(NULL, &parser->validated, cmp_size_smaller_first); |
933 | ttm_eu_fence_buffer_objects(&parser->ticket, | |
934 | &parser->validated, | |
bb977d37 | 935 | &job->base.s_fence->base); |
c3b95d4f | 936 | |
bb977d37 CZ |
937 | mutex_unlock(&job->job_lock); |
938 | amdgpu_cs_parser_fini_late(parser); | |
049fc527 CZ |
939 | up_read(&adev->exclusive_lock); |
940 | return 0; | |
d38ceaf9 | 941 | } |
049fc527 CZ |
942 | r = amdgpu_cs_parser_prepare_job(parser); |
943 | if (r) | |
944 | goto out; | |
d38ceaf9 | 945 | |
049fc527 | 946 | cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; |
d38ceaf9 | 947 | out: |
049fc527 | 948 | amdgpu_cs_parser_fini(parser, r, true); |
d38ceaf9 AD |
949 | up_read(&adev->exclusive_lock); |
950 | r = amdgpu_cs_handle_lockup(adev, r); | |
951 | return r; | |
952 | } | |
953 | ||
954 | /** | |
955 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
956 | * | |
957 | * @dev: drm device | |
958 | * @data: data from userspace | |
959 | * @filp: file private | |
960 | * | |
961 | * Wait for the command submission identified by handle to finish. | |
962 | */ | |
963 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
964 | struct drm_file *filp) | |
965 | { | |
966 | union drm_amdgpu_wait_cs *wait = data; | |
967 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 968 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 969 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 970 | struct amdgpu_ctx *ctx; |
21c16bf6 | 971 | struct fence *fence; |
d38ceaf9 AD |
972 | long r; |
973 | ||
21c16bf6 CK |
974 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
975 | wait->in.ring, &ring); | |
976 | if (r) | |
977 | return r; | |
978 | ||
66b3cf2a JZ |
979 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
980 | if (ctx == NULL) | |
981 | return -EINVAL; | |
d38ceaf9 | 982 | |
4b559c90 CZ |
983 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
984 | if (IS_ERR(fence)) | |
985 | r = PTR_ERR(fence); | |
986 | else if (fence) { | |
987 | r = fence_wait_timeout(fence, true, timeout); | |
988 | fence_put(fence); | |
989 | } else | |
990 | r = 1; | |
049fc527 | 991 | |
66b3cf2a | 992 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
993 | if (r < 0) |
994 | return r; | |
995 | ||
996 | memset(wait, 0, sizeof(*wait)); | |
997 | wait->out.status = (r == 0); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | /** | |
1003 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
1004 | * | |
1005 | * @parser: command submission parser context | |
1006 | * @addr: VM address | |
1007 | * @bo: resulting BO of the mapping found | |
1008 | * | |
1009 | * Search the buffer objects in the command submission context for a certain | |
1010 | * virtual memory address. Returns allocation structure when found, NULL | |
1011 | * otherwise. | |
1012 | */ | |
1013 | struct amdgpu_bo_va_mapping * | |
1014 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
1015 | uint64_t addr, struct amdgpu_bo **bo) | |
1016 | { | |
1017 | struct amdgpu_bo_list_entry *reloc; | |
1018 | struct amdgpu_bo_va_mapping *mapping; | |
1019 | ||
1020 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
1021 | ||
1022 | list_for_each_entry(reloc, &parser->validated, tv.head) { | |
1023 | if (!reloc->bo_va) | |
1024 | continue; | |
1025 | ||
7fc11959 CK |
1026 | list_for_each_entry(mapping, &reloc->bo_va->valids, list) { |
1027 | if (mapping->it.start > addr || | |
1028 | addr > mapping->it.last) | |
1029 | continue; | |
1030 | ||
1031 | *bo = reloc->bo_va->bo; | |
1032 | return mapping; | |
1033 | } | |
1034 | ||
1035 | list_for_each_entry(mapping, &reloc->bo_va->invalids, list) { | |
d38ceaf9 AD |
1036 | if (mapping->it.start > addr || |
1037 | addr > mapping->it.last) | |
1038 | continue; | |
1039 | ||
1040 | *bo = reloc->bo_va->bo; | |
1041 | return mapping; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | return NULL; | |
1046 | } |