[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: monk liu <monk.liu@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"

static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
{
	unsigned i, j;
	int r;

	memset(ctx, 0, sizeof(*ctx));
	ctx->adev = adev;
	kref_init(&ctx->refcount);
	spin_lock_init(&ctx->ring_lock);
	ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
			      sizeof(struct fence*), GFP_KERNEL);
	if (!ctx->fences)
		return -ENOMEM;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		ctx->rings[i].sequence = 1;
		ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
	}
	/* create context entity for each ring */
	for (i = 0; i < adev->num_rings; i++) {
		struct amdgpu_ring *ring = adev->rings[i];
		struct amd_sched_rq *rq;

		rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
		r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
					  rq, amdgpu_sched_jobs);
		if (r)
			break;
	}

	if (i < adev->num_rings) {
		for (j = 0; j < i; j++)
			amd_sched_entity_fini(&adev->rings[j]->sched,
					      &ctx->rings[j].entity);
		kfree(ctx->fences);
		return r;
	}
	return 0;
}

static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
{
	struct amdgpu_device *adev = ctx->adev;
	unsigned i, j;

	if (!adev)
		return;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		for (j = 0; j < amdgpu_sched_jobs; ++j)
			fence_put(ctx->rings[i].fences[j]);
	kfree(ctx->fences);

	for (i = 0; i < adev->num_rings; i++)
		amd_sched_entity_fini(&adev->rings[i]->sched,
				      &ctx->rings[i].entity);
}

static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv,
			    uint32_t *id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;
	int r;

	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;

	mutex_lock(&mgr->lock);
	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	if (r < 0) {
		mutex_unlock(&mgr->lock);
		kfree(ctx);
		return r;
	}
	*id = (uint32_t)r;
	r = amdgpu_ctx_init(adev, ctx);
	if (r) {
		idr_remove(&mgr->ctx_handles, *id);
		*id = 0;
		kfree(ctx);
	}
	mutex_unlock(&mgr->lock);
	return r;
}

static void amdgpu_ctx_do_release(struct kref *ref)
{
	struct amdgpu_ctx *ctx;

	ctx = container_of(ref, struct amdgpu_ctx, refcount);

	amdgpu_ctx_fini(ctx);

	kfree(ctx);
}

static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx) {
		idr_remove(&mgr->ctx_handles, id);
		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
		mutex_unlock(&mgr->lock);
		return 0;
	}
	mutex_unlock(&mgr->lock);
	return -EINVAL;
}

static int amdgpu_ctx_query(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv, uint32_t id,
			    union drm_amdgpu_ctx_out *out)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;
	unsigned reset_counter;

	if (!fpriv)
		return -EINVAL;

	mgr = &fpriv->ctx_mgr;
	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (!ctx) {
		mutex_unlock(&mgr->lock);
		return -EINVAL;
	}

	/* TODO: these two are always zero */
	out->state.flags = 0x0;
	out->state.hangs = 0x0;

	/* determine if a GPU reset has occured since the last call */
	reset_counter = atomic_read(&adev->gpu_reset_counter);
	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	if (ctx->reset_counter == reset_counter)
		out->state.reset_status = AMDGPU_CTX_NO_RESET;
	else
		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	ctx->reset_counter = reset_counter;

	mutex_unlock(&mgr->lock);
	return 0;
}

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp)
{
	int r;
	uint32_t id;

	union drm_amdgpu_ctx *args = data;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	r = 0;
	id = args->in.ctx_id;

	switch (args->in.op) {
	case AMDGPU_CTX_OP_ALLOC_CTX:
		r = amdgpu_ctx_alloc(adev, fpriv, &id);
		args->out.alloc.ctx_id = id;
		break;
	case AMDGPU_CTX_OP_FREE_CTX:
		r = amdgpu_ctx_free(fpriv, id);
		break;
	case AMDGPU_CTX_OP_QUERY_STATE:
		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
		break;
	default:
		return -EINVAL;
	}

	return r;
}

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;

	if (!fpriv)
		return NULL;

	mgr = &fpriv->ctx_mgr;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx)
		kref_get(&ctx->refcount);
	mutex_unlock(&mgr->lock);
	return ctx;
}

int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
{
	if (ctx == NULL)
		return -EINVAL;

	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	return 0;
}

uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
			      struct fence *fence)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	uint64_t seq = cring->sequence;
	unsigned idx = 0;
	struct fence *other = NULL;

	idx = seq & (amdgpu_sched_jobs - 1);
	other = cring->fences[idx];
	if (other) {
		signed long r;
		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
		if (r < 0)
			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	}

	fence_get(fence);

	spin_lock(&ctx->ring_lock);
	cring->fences[idx] = fence;
	cring->sequence++;
	spin_unlock(&ctx->ring_lock);

	fence_put(other);

	return seq;
}

struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				   struct amdgpu_ring *ring, uint64_t seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;

	spin_lock(&ctx->ring_lock);

	if (seq >= cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return ERR_PTR(-EINVAL);
	}


	if (seq + amdgpu_sched_jobs < cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return NULL;
	}

	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
	spin_unlock(&ctx->ring_lock);

	return fence;
}

void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
	mutex_init(&mgr->lock);
	idr_init(&mgr->ctx_handles);
}

void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
{
	struct amdgpu_ctx *ctx;
	struct idr *idp;
	uint32_t id;

	idp = &mgr->ctx_handles;

	idr_for_each_entry(idp, ctx, id) {
		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
			DRM_ERROR("ctx %p is still alive\n", ctx);
	}

	idr_destroy(&mgr->ctx_handles);
	mutex_destroy(&mgr->lock);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: monk liu <monk.liu@amd.com>
	23	*/
	24
	25	#include <drm/drmP.h>
	26	#include "amdgpu.h"
	27
20874179	28	static int amdgpu_ctx_init(struct amdgpu_device adev, struct amdgpu_ctx ctx)
d38ceaf9	29	{
21c16bf6	30	unsigned i, j;
47f38501	31	int r;
d38ceaf9	32
23ca0e4e CZ	33	memset(ctx, 0, sizeof(*ctx));
	34	ctx->adev = adev;
	35	kref_init(&ctx->refcount);
	36	spin_lock_init(&ctx->ring_lock);
a750b47e CK	37	ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS,
a750b47e CK	38	sizeof(struct fence*), GFP_KERNEL);
37cd0ca2 CZ	39	if (!ctx->fences)
37cd0ca2 CZ	40	return -ENOMEM;
d38ceaf9	41
37cd0ca2 CZ	42	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
37cd0ca2 CZ	43	ctx->rings[i].sequence = 1;
a750b47e	44	ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
37cd0ca2	45	}
cadf97b1 CZ	46	/* create context entity for each ring */
cadf97b1 CZ	47	for (i = 0; i < adev->num_rings; i++) {
20874179	48	struct amdgpu_ring *ring = adev->rings[i];
cadf97b1	49	struct amd_sched_rq *rq;
20874179 CK	50
	51	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
	52	r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
cadf97b1 CZ	53	rq, amdgpu_sched_jobs);
	54	if (r)
	55	break;
	56	}
	57
	58	if (i < adev->num_rings) {
	59	for (j = 0; j < i; j++)
	60	amd_sched_entity_fini(&adev->rings[j]->sched,
	61	&ctx->rings[j].entity);
	62	kfree(ctx->fences);
	63	return r;
9cb7e5a9	64	}
d38ceaf9 AD	65	return 0;
	66	}
	67
20874179	68	static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
d38ceaf9	69	{
47f38501 CK	70	struct amdgpu_device *adev = ctx->adev;
	71	unsigned i, j;
	72
fe295b27 DA	73	if (!adev)
	74	return;
	75
47f38501	76	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
37cd0ca2	77	for (j = 0; j < amdgpu_sched_jobs; ++j)
47f38501	78	fence_put(ctx->rings[i].fences[j]);
37cd0ca2	79	kfree(ctx->fences);
47f38501	80
cadf97b1 CZ	81	for (i = 0; i < adev->num_rings; i++)
	82	amd_sched_entity_fini(&adev->rings[i]->sched,
	83	&ctx->rings[i].entity);
47f38501 CK	84	}
	85
	86	static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
	87	struct amdgpu_fpriv *fpriv,
	88	uint32_t *id)
	89	{
	90	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
d38ceaf9	91	struct amdgpu_ctx *ctx;
47f38501	92	int r;
d38ceaf9	93
47f38501 CK	94	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	95	if (!ctx)
	96	return -ENOMEM;
	97
	98	mutex_lock(&mgr->lock);
	99	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	100	if (r < 0) {
0147ee0f	101	mutex_unlock(&mgr->lock);
47f38501 CK	102	kfree(ctx);
	103	return r;
	104	}
	105	*id = (uint32_t)r;
20874179	106	r = amdgpu_ctx_init(adev, ctx);
c648ed7c CZ	107	if (r) {
	108	idr_remove(&mgr->ctx_handles, *id);
	109	*id = 0;
	110	kfree(ctx);
	111	}
47f38501	112	mutex_unlock(&mgr->lock);
47f38501 CK	113	return r;
	114	}
	115
	116	static void amdgpu_ctx_do_release(struct kref *ref)
	117	{
	118	struct amdgpu_ctx *ctx;
	119
	120	ctx = container_of(ref, struct amdgpu_ctx, refcount);
	121
	122	amdgpu_ctx_fini(ctx);
	123
	124	kfree(ctx);
	125	}
	126
	127	static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
	128	{
	129	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	130	struct amdgpu_ctx *ctx;
	131
	132	mutex_lock(&mgr->lock);
	133	ctx = idr_find(&mgr->ctx_handles, id);
	134	if (ctx) {
	135	idr_remove(&mgr->ctx_handles, id);
23ca0e4e	136	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
47f38501	137	mutex_unlock(&mgr->lock);
f11358da	138	return 0;
d38ceaf9	139	}
47f38501	140	mutex_unlock(&mgr->lock);
d38ceaf9 AD	141	return -EINVAL;
	142	}
	143
d94aed5a MO	144	static int amdgpu_ctx_query(struct amdgpu_device *adev,
	145	struct amdgpu_fpriv *fpriv, uint32_t id,
	146	union drm_amdgpu_ctx_out *out)
d38ceaf9 AD	147	{
d38ceaf9 AD	148	struct amdgpu_ctx *ctx;
23ca0e4e	149	struct amdgpu_ctx_mgr *mgr;
d94aed5a	150	unsigned reset_counter;
d38ceaf9	151
23ca0e4e CZ	152	if (!fpriv)
	153	return -EINVAL;
	154
	155	mgr = &fpriv->ctx_mgr;
0147ee0f	156	mutex_lock(&mgr->lock);
d38ceaf9	157	ctx = idr_find(&mgr->ctx_handles, id);
d94aed5a	158	if (!ctx) {
0147ee0f	159	mutex_unlock(&mgr->lock);
d94aed5a	160	return -EINVAL;
d38ceaf9	161	}
d94aed5a MO	162
d94aed5a MO	163	/* TODO: these two are always zero */
0b492a4c AD	164	out->state.flags = 0x0;
0b492a4c AD	165	out->state.hangs = 0x0;
d94aed5a MO	166
	167	/* determine if a GPU reset has occured since the last call */
	168	reset_counter = atomic_read(&adev->gpu_reset_counter);
	169	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	170	if (ctx->reset_counter == reset_counter)
	171	out->state.reset_status = AMDGPU_CTX_NO_RESET;
	172	else
	173	out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	174	ctx->reset_counter = reset_counter;
	175
0147ee0f	176	mutex_unlock(&mgr->lock);
d94aed5a	177	return 0;
d38ceaf9 AD	178	}
d38ceaf9 AD	179
d38ceaf9	180	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
d94aed5a	181	struct drm_file *filp)
d38ceaf9 AD	182	{
	183	int r;
	184	uint32_t id;
d38ceaf9 AD	185
	186	union drm_amdgpu_ctx *args = data;
	187	struct amdgpu_device *adev = dev->dev_private;
	188	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	189
	190	r = 0;
	191	id = args->in.ctx_id;
d38ceaf9 AD	192
d38ceaf9 AD	193	switch (args->in.op) {
a750b47e CK	194	case AMDGPU_CTX_OP_ALLOC_CTX:
	195	r = amdgpu_ctx_alloc(adev, fpriv, &id);
	196	args->out.alloc.ctx_id = id;
	197	break;
	198	case AMDGPU_CTX_OP_FREE_CTX:
	199	r = amdgpu_ctx_free(fpriv, id);
	200	break;
	201	case AMDGPU_CTX_OP_QUERY_STATE:
	202	r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
	203	break;
	204	default:
	205	return -EINVAL;
d38ceaf9 AD	206	}
	207
	208	return r;
	209	}
66b3cf2a JZ	210
	211	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id)
	212	{
	213	struct amdgpu_ctx *ctx;
23ca0e4e CZ	214	struct amdgpu_ctx_mgr *mgr;
	215
	216	if (!fpriv)
	217	return NULL;
	218
	219	mgr = &fpriv->ctx_mgr;
66b3cf2a JZ	220
	221	mutex_lock(&mgr->lock);
	222	ctx = idr_find(&mgr->ctx_handles, id);
	223	if (ctx)
	224	kref_get(&ctx->refcount);
	225	mutex_unlock(&mgr->lock);
	226	return ctx;
	227	}
	228
	229	int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
	230	{
66b3cf2a JZ	231	if (ctx == NULL)
	232	return -EINVAL;
	233
66b3cf2a	234	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
66b3cf2a JZ	235	return 0;
66b3cf2a JZ	236	}
21c16bf6 CK	237
21c16bf6 CK	238	uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx ctx, struct amdgpu_ring ring,
ce882e6d	239	struct fence *fence)
21c16bf6 CK	240	{
21c16bf6 CK	241	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
ce882e6d	242	uint64_t seq = cring->sequence;
b43a9a7e CZ	243	unsigned idx = 0;
b43a9a7e CZ	244	struct fence *other = NULL;
21c16bf6	245
5b011235	246	idx = seq & (amdgpu_sched_jobs - 1);
b43a9a7e	247	other = cring->fences[idx];
21c16bf6 CK	248	if (other) {
	249	signed long r;
	250	r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
	251	if (r < 0)
	252	DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	253	}
	254
	255	fence_get(fence);
	256
	257	spin_lock(&ctx->ring_lock);
	258	cring->fences[idx] = fence;
ce882e6d	259	cring->sequence++;
21c16bf6 CK	260	spin_unlock(&ctx->ring_lock);
	261
	262	fence_put(other);
	263
	264	return seq;
	265	}
	266
	267	struct fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
	268	struct amdgpu_ring *ring, uint64_t seq)
	269	{
	270	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	271	struct fence *fence;
	272
	273	spin_lock(&ctx->ring_lock);
b43a9a7e	274
ce882e6d	275	if (seq >= cring->sequence) {
21c16bf6 CK	276	spin_unlock(&ctx->ring_lock);
	277	return ERR_PTR(-EINVAL);
	278	}
	279
b43a9a7e	280
37cd0ca2	281	if (seq + amdgpu_sched_jobs < cring->sequence) {
21c16bf6 CK	282	spin_unlock(&ctx->ring_lock);
	283	return NULL;
	284	}
	285
5b011235	286	fence = fence_get(cring->fences[seq & (amdgpu_sched_jobs - 1)]);
21c16bf6 CK	287	spin_unlock(&ctx->ring_lock);
	288
	289	return fence;
	290	}
efd4ccb5 CK	291
	292	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
	293	{
	294	mutex_init(&mgr->lock);
	295	idr_init(&mgr->ctx_handles);
	296	}
	297
	298	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
	299	{
	300	struct amdgpu_ctx *ctx;
	301	struct idr *idp;
	302	uint32_t id;
	303
	304	idp = &mgr->ctx_handles;
	305
	306	idr_for_each_entry(idp, ctx, id) {
	307	if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
	308	DRM_ERROR("ctx %p is still alive\n", ctx);
	309	}
	310
	311	idr_destroy(&mgr->ctx_handles);
	312	mutex_destroy(&mgr->lock);
	313	}