[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: monk liu <monk.liu@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"

int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
		    struct amdgpu_ctx *ctx)
{
	unsigned i, j;
	int r;

	memset(ctx, 0, sizeof(*ctx));
	ctx->adev = adev;
	kref_init(&ctx->refcount);
	spin_lock_init(&ctx->ring_lock);
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		ctx->rings[i].sequence = 1;

	if (amdgpu_enable_scheduler) {
		/* create context entity for each ring */
		for (i = 0; i < adev->num_rings; i++) {
			struct amd_sched_rq *rq;
			if (kernel)
				rq = &adev->rings[i]->sched.kernel_rq;
			else
				rq = &adev->rings[i]->sched.sched_rq;
			r = amd_sched_entity_init(&adev->rings[i]->sched,
						  &ctx->rings[i].entity,
						  rq, amdgpu_sched_jobs);
			if (r)
				break;
		}

		if (i < adev->num_rings) {
			for (j = 0; j < i; j++)
				amd_sched_entity_fini(&adev->rings[j]->sched,
						      &ctx->rings[j].entity);
			kfree(ctx);
			return r;
		}
	}
	return 0;
}

void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
{
	struct amdgpu_device *adev = ctx->adev;
	unsigned i, j;

	if (!adev)
		return;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
			fence_put(ctx->rings[i].fences[j]);

	if (amdgpu_enable_scheduler) {
		for (i = 0; i < adev->num_rings; i++)
			amd_sched_entity_fini(&adev->rings[i]->sched,
					      &ctx->rings[i].entity);
	}
}

static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv,
			    uint32_t *id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;
	int r;

	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;

	mutex_lock(&mgr->lock);
	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	if (r < 0) {
		mutex_unlock(&mgr->lock);
		kfree(ctx);
		return r;
	}
	*id = (uint32_t)r;
	r = amdgpu_ctx_init(adev, false, ctx);
	mutex_unlock(&mgr->lock);

	return r;
}

static void amdgpu_ctx_do_release(struct kref *ref)
{
	struct amdgpu_ctx *ctx;

	ctx = container_of(ref, struct amdgpu_ctx, refcount);

	amdgpu_ctx_fini(ctx);

	kfree(ctx);
}

static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	struct amdgpu_ctx *ctx;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx) {
		idr_remove(&mgr->ctx_handles, id);
		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
		mutex_unlock(&mgr->lock);
		return 0;
	}
	mutex_unlock(&mgr->lock);
	return -EINVAL;
}

static int amdgpu_ctx_query(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv, uint32_t id,
			    union drm_amdgpu_ctx_out *out)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;
	unsigned reset_counter;

	if (!fpriv)
		return -EINVAL;

	mgr = &fpriv->ctx_mgr;
	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (!ctx) {
		mutex_unlock(&mgr->lock);
		return -EINVAL;
	}

	/* TODO: these two are always zero */
	out->state.flags = 0x0;
	out->state.hangs = 0x0;

	/* determine if a GPU reset has occured since the last call */
	reset_counter = atomic_read(&adev->gpu_reset_counter);
	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	if (ctx->reset_counter == reset_counter)
		out->state.reset_status = AMDGPU_CTX_NO_RESET;
	else
		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	ctx->reset_counter = reset_counter;

	mutex_unlock(&mgr->lock);
	return 0;
}

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp)
{
	int r;
	uint32_t id;

	union drm_amdgpu_ctx *args = data;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	r = 0;
	id = args->in.ctx_id;

	switch (args->in.op) {
		case AMDGPU_CTX_OP_ALLOC_CTX:
			r = amdgpu_ctx_alloc(adev, fpriv, &id);
			args->out.alloc.ctx_id = id;
			break;
		case AMDGPU_CTX_OP_FREE_CTX:
			r = amdgpu_ctx_free(fpriv, id);
			break;
		case AMDGPU_CTX_OP_QUERY_STATE:
			r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
			break;
		default:
			return -EINVAL;
	}

	return r;
}

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;

	if (!fpriv)
		return NULL;

	mgr = &fpriv->ctx_mgr;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx)
		kref_get(&ctx->refcount);
	mutex_unlock(&mgr->lock);
	return ctx;
}

int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
{
	if (ctx == NULL)
		return -EINVAL;

	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	return 0;
}

uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
			      struct fence *fence)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	uint64_t seq = cring->sequence;
	unsigned idx = 0;
	struct fence *other = NULL;

	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
	other = cring->fences[idx];
	if (other) {
		signed long r;
		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
		if (r < 0)
			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	}

	fence_get(fence);

	spin_lock(&ctx->ring_lock);
	cring->fences[idx] = fence;
	cring->sequence++;
	spin_unlock(&ctx->ring_lock);

	fence_put(other);

	return seq;
}

struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				   struct amdgpu_ring *ring, uint64_t seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;

	spin_lock(&ctx->ring_lock);

	if (seq >= cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return ERR_PTR(-EINVAL);
	}


	if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) {
		spin_unlock(&ctx->ring_lock);
		return NULL;
	}

	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	spin_unlock(&ctx->ring_lock);

	return fence;
}

void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
	mutex_init(&mgr->lock);
	idr_init(&mgr->ctx_handles);
}

void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
{
	struct amdgpu_ctx *ctx;
	struct idr *idp;
	uint32_t id;

	idp = &mgr->ctx_handles;

	idr_for_each_entry(idp, ctx, id) {
		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
			DRM_ERROR("ctx %p is still alive\n", ctx);
	}

	idr_destroy(&mgr->ctx_handles);
	mutex_destroy(&mgr->lock);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: monk liu <monk.liu@amd.com>
	23	*/
	24
	25	#include <drm/drmP.h>
	26	#include "amdgpu.h"
	27
47f38501 CK	28	int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
47f38501 CK	29	struct amdgpu_ctx *ctx)
d38ceaf9	30	{
21c16bf6	31	unsigned i, j;
47f38501	32	int r;
d38ceaf9	33
23ca0e4e CZ	34	memset(ctx, 0, sizeof(*ctx));
	35	ctx->adev = adev;
	36	kref_init(&ctx->refcount);
	37	spin_lock_init(&ctx->ring_lock);
	38	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	39	ctx->rings[i].sequence = 1;
d38ceaf9	40
9cb7e5a9 CZ	41	if (amdgpu_enable_scheduler) {
	42	/* create context entity for each ring */
	43	for (i = 0; i < adev->num_rings; i++) {
432a4ff8	44	struct amd_sched_rq *rq;
47f38501	45	if (kernel)
4f839a24	46	rq = &adev->rings[i]->sched.kernel_rq;
47f38501	47	else
4f839a24 CK	48	rq = &adev->rings[i]->sched.sched_rq;
4f839a24 CK	49	r = amd_sched_entity_init(&adev->rings[i]->sched,
91404fb2 CK	50	&ctx->rings[i].entity,
91404fb2 CK	51	rq, amdgpu_sched_jobs);
9cb7e5a9 CZ	52	if (r)
	53	break;
	54	}
	55
	56	if (i < adev->num_rings) {
	57	for (j = 0; j < i; j++)
4f839a24	58	amd_sched_entity_fini(&adev->rings[j]->sched,
91404fb2	59	&ctx->rings[j].entity);
9cb7e5a9	60	kfree(ctx);
47f38501	61	return r;
9cb7e5a9 CZ	62	}
9cb7e5a9 CZ	63	}
d38ceaf9 AD	64	return 0;
	65	}
	66
47f38501	67	void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
d38ceaf9	68	{
47f38501 CK	69	struct amdgpu_device *adev = ctx->adev;
	70	unsigned i, j;
	71
fe295b27 DA	72	if (!adev)
	73	return;
	74
47f38501 CK	75	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	76	for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
	77	fence_put(ctx->rings[i].fences[j]);
	78
	79	if (amdgpu_enable_scheduler) {
	80	for (i = 0; i < adev->num_rings; i++)
4f839a24	81	amd_sched_entity_fini(&adev->rings[i]->sched,
91404fb2	82	&ctx->rings[i].entity);
47f38501 CK	83	}
	84	}
	85
	86	static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
	87	struct amdgpu_fpriv *fpriv,
	88	uint32_t *id)
	89	{
	90	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
d38ceaf9	91	struct amdgpu_ctx *ctx;
47f38501	92	int r;
d38ceaf9	93
47f38501 CK	94	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	95	if (!ctx)
	96	return -ENOMEM;
	97
	98	mutex_lock(&mgr->lock);
	99	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	100	if (r < 0) {
0147ee0f	101	mutex_unlock(&mgr->lock);
47f38501 CK	102	kfree(ctx);
	103	return r;
	104	}
	105	*id = (uint32_t)r;
	106	r = amdgpu_ctx_init(adev, false, ctx);
	107	mutex_unlock(&mgr->lock);
	108
	109	return r;
	110	}
	111
	112	static void amdgpu_ctx_do_release(struct kref *ref)
	113	{
	114	struct amdgpu_ctx *ctx;
	115
	116	ctx = container_of(ref, struct amdgpu_ctx, refcount);
	117
	118	amdgpu_ctx_fini(ctx);
	119
	120	kfree(ctx);
	121	}
	122
	123	static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id)
	124	{
	125	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	126	struct amdgpu_ctx *ctx;
	127
	128	mutex_lock(&mgr->lock);
	129	ctx = idr_find(&mgr->ctx_handles, id);
	130	if (ctx) {
	131	idr_remove(&mgr->ctx_handles, id);
23ca0e4e	132	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
47f38501	133	mutex_unlock(&mgr->lock);
f11358da	134	return 0;
d38ceaf9	135	}
47f38501	136	mutex_unlock(&mgr->lock);
d38ceaf9 AD	137	return -EINVAL;
	138	}
	139
d94aed5a MO	140	static int amdgpu_ctx_query(struct amdgpu_device *adev,
	141	struct amdgpu_fpriv *fpriv, uint32_t id,
	142	union drm_amdgpu_ctx_out *out)
d38ceaf9 AD	143	{
d38ceaf9 AD	144	struct amdgpu_ctx *ctx;
23ca0e4e	145	struct amdgpu_ctx_mgr *mgr;
d94aed5a	146	unsigned reset_counter;
d38ceaf9	147
23ca0e4e CZ	148	if (!fpriv)
	149	return -EINVAL;
	150
	151	mgr = &fpriv->ctx_mgr;
0147ee0f	152	mutex_lock(&mgr->lock);
d38ceaf9	153	ctx = idr_find(&mgr->ctx_handles, id);
d94aed5a	154	if (!ctx) {
0147ee0f	155	mutex_unlock(&mgr->lock);
d94aed5a	156	return -EINVAL;
d38ceaf9	157	}
d94aed5a MO	158
d94aed5a MO	159	/* TODO: these two are always zero */
0b492a4c AD	160	out->state.flags = 0x0;
0b492a4c AD	161	out->state.hangs = 0x0;
d94aed5a MO	162
	163	/* determine if a GPU reset has occured since the last call */
	164	reset_counter = atomic_read(&adev->gpu_reset_counter);
	165	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	166	if (ctx->reset_counter == reset_counter)
	167	out->state.reset_status = AMDGPU_CTX_NO_RESET;
	168	else
	169	out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	170	ctx->reset_counter = reset_counter;
	171
0147ee0f	172	mutex_unlock(&mgr->lock);
d94aed5a	173	return 0;
d38ceaf9 AD	174	}
d38ceaf9 AD	175
d38ceaf9	176	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
d94aed5a	177	struct drm_file *filp)
d38ceaf9 AD	178	{
	179	int r;
	180	uint32_t id;
d38ceaf9 AD	181
	182	union drm_amdgpu_ctx *args = data;
	183	struct amdgpu_device *adev = dev->dev_private;
	184	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	185
	186	r = 0;
	187	id = args->in.ctx_id;
d38ceaf9 AD	188
	189	switch (args->in.op) {
	190	case AMDGPU_CTX_OP_ALLOC_CTX:
0b492a4c	191	r = amdgpu_ctx_alloc(adev, fpriv, &id);
d38ceaf9 AD	192	args->out.alloc.ctx_id = id;
	193	break;
	194	case AMDGPU_CTX_OP_FREE_CTX:
47f38501	195	r = amdgpu_ctx_free(fpriv, id);
d38ceaf9 AD	196	break;
d38ceaf9 AD	197	case AMDGPU_CTX_OP_QUERY_STATE:
d94aed5a	198	r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
d38ceaf9 AD	199	break;
	200	default:
	201	return -EINVAL;
	202	}
	203
	204	return r;
	205	}
66b3cf2a JZ	206
	207	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id)
	208	{
	209	struct amdgpu_ctx *ctx;
23ca0e4e CZ	210	struct amdgpu_ctx_mgr *mgr;
	211
	212	if (!fpriv)
	213	return NULL;
	214
	215	mgr = &fpriv->ctx_mgr;
66b3cf2a JZ	216
	217	mutex_lock(&mgr->lock);
	218	ctx = idr_find(&mgr->ctx_handles, id);
	219	if (ctx)
	220	kref_get(&ctx->refcount);
	221	mutex_unlock(&mgr->lock);
	222	return ctx;
	223	}
	224
	225	int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
	226	{
66b3cf2a JZ	227	if (ctx == NULL)
	228	return -EINVAL;
	229
66b3cf2a	230	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
66b3cf2a JZ	231	return 0;
66b3cf2a JZ	232	}
21c16bf6 CK	233
21c16bf6 CK	234	uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx ctx, struct amdgpu_ring ring,
ce882e6d	235	struct fence *fence)
21c16bf6 CK	236	{
21c16bf6 CK	237	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
ce882e6d	238	uint64_t seq = cring->sequence;
b43a9a7e CZ	239	unsigned idx = 0;
b43a9a7e CZ	240	struct fence *other = NULL;
21c16bf6	241
b43a9a7e CZ	242	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
b43a9a7e CZ	243	other = cring->fences[idx];
21c16bf6 CK	244	if (other) {
	245	signed long r;
	246	r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
	247	if (r < 0)
	248	DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	249	}
	250
	251	fence_get(fence);
	252
	253	spin_lock(&ctx->ring_lock);
	254	cring->fences[idx] = fence;
ce882e6d	255	cring->sequence++;
21c16bf6 CK	256	spin_unlock(&ctx->ring_lock);
	257
	258	fence_put(other);
	259
	260	return seq;
	261	}
	262
	263	struct fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
	264	struct amdgpu_ring *ring, uint64_t seq)
	265	{
	266	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	267	struct fence *fence;
	268
	269	spin_lock(&ctx->ring_lock);
b43a9a7e	270
ce882e6d	271	if (seq >= cring->sequence) {
21c16bf6 CK	272	spin_unlock(&ctx->ring_lock);
	273	return ERR_PTR(-EINVAL);
	274	}
	275
b43a9a7e	276
ce882e6d	277	if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) {
21c16bf6 CK	278	spin_unlock(&ctx->ring_lock);
	279	return NULL;
	280	}
	281
	282	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	283	spin_unlock(&ctx->ring_lock);
	284
	285	return fence;
	286	}
efd4ccb5 CK	287
	288	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
	289	{
	290	mutex_init(&mgr->lock);
	291	idr_init(&mgr->ctx_handles);
	292	}
	293
	294	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
	295	{
	296	struct amdgpu_ctx *ctx;
	297	struct idr *idp;
	298	uint32_t id;
	299
	300	idp = &mgr->ctx_handles;
	301
	302	idr_for_each_entry(idp, ctx, id) {
	303	if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
	304	DRM_ERROR("ctx %p is still alive\n", ctx);
	305	}
	306
	307	idr_destroy(&mgr->ctx_handles);
	308	mutex_destroy(&mgr->lock);
	309	}