[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: monk liu <monk.liu@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"

static void amdgpu_ctx_do_release(struct kref *ref)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_device *adev;
	unsigned i, j;

	ctx = container_of(ref, struct amdgpu_ctx, refcount);
	adev = ctx->adev;


	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
			fence_put(ctx->rings[i].fences[j]);

	if (amdgpu_enable_scheduler) {
		for (i = 0; i < adev->num_rings; i++)
			amd_context_entity_fini(adev->rings[i]->scheduler,
						&ctx->rings[i].c_entity);
	}

	kfree(ctx);
}

static void amdgpu_ctx_init(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv,
			    struct amdgpu_ctx *ctx)
{
	int i;
	memset(ctx, 0, sizeof(*ctx));
	ctx->adev = adev;
	kref_init(&ctx->refcount);
	spin_lock_init(&ctx->ring_lock);
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		ctx->rings[i].sequence = 1;
}

int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
		     uint32_t *id)
{
	struct amdgpu_ctx *ctx;
	int i, j, r;

	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;
	if (fpriv) {
		struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
		mutex_lock(&mgr->lock);
		r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
		if (r < 0) {
			mutex_unlock(&mgr->lock);
			kfree(ctx);
			return r;
		}
		*id = (uint32_t)r;
		amdgpu_ctx_init(adev, fpriv, ctx);
		mutex_unlock(&mgr->lock);
	} else {
		if (adev->kernel_ctx) {
			DRM_ERROR("kernel cnotext has been created.\n");
			kfree(ctx);
			return 0;
		}
		amdgpu_ctx_init(adev, fpriv, ctx);

		adev->kernel_ctx = ctx;
	}

	if (amdgpu_enable_scheduler) {
		/* create context entity for each ring */
		for (i = 0; i < adev->num_rings; i++) {
			struct amd_run_queue *rq;
			if (fpriv)
				rq = &adev->rings[i]->scheduler->sched_rq;
			else
				rq = &adev->rings[i]->scheduler->kernel_rq;
			r = amd_context_entity_init(adev->rings[i]->scheduler,
						    &ctx->rings[i].c_entity,
						    NULL, rq, amdgpu_sched_jobs);
			if (r)
				break;
		}

		if (i < adev->num_rings) {
			for (j = 0; j < i; j++)
				amd_context_entity_fini(adev->rings[j]->scheduler,
							&ctx->rings[j].c_entity);
			kfree(ctx);
			return -EINVAL;
		}
	}

	return 0;
}

int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;

	if (fpriv) {
		struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
		mutex_lock(&mgr->lock);
		ctx = idr_find(&mgr->ctx_handles, id);
		if (ctx) {
			idr_remove(&mgr->ctx_handles, id);
			kref_put(&ctx->refcount, amdgpu_ctx_do_release);
			mutex_unlock(&mgr->lock);
			return 0;
		}
		mutex_unlock(&mgr->lock);
	} else {
		ctx = adev->kernel_ctx;
		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
		return 0;
	}
	return -EINVAL;
}

static int amdgpu_ctx_query(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv, uint32_t id,
			    union drm_amdgpu_ctx_out *out)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;
	unsigned reset_counter;

	if (!fpriv)
		return -EINVAL;

	mgr = &fpriv->ctx_mgr;
	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (!ctx) {
		mutex_unlock(&mgr->lock);
		return -EINVAL;
	}

	/* TODO: these two are always zero */
	out->state.flags = 0x0;
	out->state.hangs = 0x0;

	/* determine if a GPU reset has occured since the last call */
	reset_counter = atomic_read(&adev->gpu_reset_counter);
	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	if (ctx->reset_counter == reset_counter)
		out->state.reset_status = AMDGPU_CTX_NO_RESET;
	else
		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	ctx->reset_counter = reset_counter;

	mutex_unlock(&mgr->lock);
	return 0;
}

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp)
{
	int r;
	uint32_t id;

	union drm_amdgpu_ctx *args = data;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	r = 0;
	id = args->in.ctx_id;

	switch (args->in.op) {
		case AMDGPU_CTX_OP_ALLOC_CTX:
			r = amdgpu_ctx_alloc(adev, fpriv, &id);
			args->out.alloc.ctx_id = id;
			break;
		case AMDGPU_CTX_OP_FREE_CTX:
			r = amdgpu_ctx_free(adev, fpriv, id);
			break;
		case AMDGPU_CTX_OP_QUERY_STATE:
			r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
			break;
		default:
			return -EINVAL;
	}

	return r;
}

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;

	if (!fpriv)
		return NULL;

	mgr = &fpriv->ctx_mgr;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx)
		kref_get(&ctx->refcount);
	mutex_unlock(&mgr->lock);
	return ctx;
}

int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
{
	if (ctx == NULL)
		return -EINVAL;

	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	return 0;
}

uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
			      struct fence *fence, uint64_t queued_seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	uint64_t seq = 0;
	unsigned idx = 0;
	struct fence *other = NULL;

	if (amdgpu_enable_scheduler)
		seq = queued_seq;
	else
		seq = cring->sequence;
	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
	other = cring->fences[idx];
	if (other) {
		signed long r;
		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
		if (r < 0)
			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	}

	fence_get(fence);

	spin_lock(&ctx->ring_lock);
	cring->fences[idx] = fence;
	if (!amdgpu_enable_scheduler)
		cring->sequence++;
	spin_unlock(&ctx->ring_lock);

	fence_put(other);

	return seq;
}

struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				   struct amdgpu_ring *ring, uint64_t seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;
	uint64_t queued_seq;
	int r;

	if (amdgpu_enable_scheduler) {
		r = amd_sched_wait_emit(&cring->c_entity,
					seq,
					false,
					-1);
		if (r)
			return NULL;
	}

	spin_lock(&ctx->ring_lock);
	if (amdgpu_enable_scheduler)
		queued_seq = amd_sched_next_queued_seq(&cring->c_entity);
	else
		queued_seq = cring->sequence;

	if (seq >= queued_seq) {
		spin_unlock(&ctx->ring_lock);
		return ERR_PTR(-EINVAL);
	}


	if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) {
		spin_unlock(&ctx->ring_lock);
		return NULL;
	}

	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	spin_unlock(&ctx->ring_lock);

	return fence;
}

void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
{
	mutex_init(&mgr->lock);
	idr_init(&mgr->ctx_handles);
}

void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
{
	struct amdgpu_ctx *ctx;
	struct idr *idp;
	uint32_t id;

	idp = &mgr->ctx_handles;

	idr_for_each_entry(idp, ctx, id) {
		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
			DRM_ERROR("ctx %p is still alive\n", ctx);
	}

	idr_destroy(&mgr->ctx_handles);
	mutex_destroy(&mgr->lock);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: monk liu <monk.liu@amd.com>
	23	*/
	24
	25	#include <drm/drmP.h>
	26	#include "amdgpu.h"
	27
	28	static void amdgpu_ctx_do_release(struct kref *ref)
	29	{
	30	struct amdgpu_ctx *ctx;
9cb7e5a9	31	struct amdgpu_device *adev;
21c16bf6	32	unsigned i, j;
d38ceaf9 AD	33
d38ceaf9 AD	34	ctx = container_of(ref, struct amdgpu_ctx, refcount);
9cb7e5a9 CZ	35	adev = ctx->adev;
9cb7e5a9 CZ	36
21c16bf6 CK	37
	38	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	39	for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
	40	fence_put(ctx->rings[i].fences[j]);
9cb7e5a9 CZ	41
	42	if (amdgpu_enable_scheduler) {
	43	for (i = 0; i < adev->num_rings; i++)
	44	amd_context_entity_fini(adev->rings[i]->scheduler,
	45	&ctx->rings[i].c_entity);
	46	}
	47
d38ceaf9 AD	48	kfree(ctx);
	49	}
	50
23ca0e4e CZ	51	static void amdgpu_ctx_init(struct amdgpu_device *adev,
23ca0e4e CZ	52	struct amdgpu_fpriv *fpriv,
0e89d0c1	53	struct amdgpu_ctx *ctx)
23ca0e4e CZ	54	{
	55	int i;
	56	memset(ctx, 0, sizeof(*ctx));
	57	ctx->adev = adev;
	58	kref_init(&ctx->refcount);
	59	spin_lock_init(&ctx->ring_lock);
	60	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	61	ctx->rings[i].sequence = 1;
	62	}
	63
0b492a4c AD	64	int amdgpu_ctx_alloc(struct amdgpu_device adev, struct amdgpu_fpriv fpriv,
0b492a4c AD	65	uint32_t *id)
d38ceaf9	66	{
d38ceaf9	67	struct amdgpu_ctx *ctx;
9cb7e5a9	68	int i, j, r;
d38ceaf9 AD	69
	70	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	71	if (!ctx)
	72	return -ENOMEM;
23ca0e4e CZ	73	if (fpriv) {
	74	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	75	mutex_lock(&mgr->lock);
	76	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	77	if (r < 0) {
	78	mutex_unlock(&mgr->lock);
	79	kfree(ctx);
	80	return r;
	81	}
	82	*id = (uint32_t)r;
0e89d0c1	83	amdgpu_ctx_init(adev, fpriv, ctx);
0147ee0f	84	mutex_unlock(&mgr->lock);
23ca0e4e CZ	85	} else {
	86	if (adev->kernel_ctx) {
	87	DRM_ERROR("kernel cnotext has been created.\n");
	88	kfree(ctx);
	89	return 0;
	90	}
0e89d0c1	91	amdgpu_ctx_init(adev, fpriv, ctx);
23ca0e4e CZ	92
23ca0e4e CZ	93	adev->kernel_ctx = ctx;
d38ceaf9	94	}
d38ceaf9	95
9cb7e5a9 CZ	96	if (amdgpu_enable_scheduler) {
	97	/* create context entity for each ring */
	98	for (i = 0; i < adev->num_rings; i++) {
	99	struct amd_run_queue *rq;
	100	if (fpriv)
	101	rq = &adev->rings[i]->scheduler->sched_rq;
	102	else
	103	rq = &adev->rings[i]->scheduler->kernel_rq;
	104	r = amd_context_entity_init(adev->rings[i]->scheduler,
	105	&ctx->rings[i].c_entity,
0e89d0c1	106	NULL, rq, amdgpu_sched_jobs);
9cb7e5a9 CZ	107	if (r)
	108	break;
	109	}
	110
	111	if (i < adev->num_rings) {
	112	for (j = 0; j < i; j++)
	113	amd_context_entity_fini(adev->rings[j]->scheduler,
	114	&ctx->rings[j].c_entity);
	115	kfree(ctx);
	116	return -EINVAL;
	117	}
	118	}
d38ceaf9 AD	119
	120	return 0;
	121	}
	122
	123	int amdgpu_ctx_free(struct amdgpu_device adev, struct amdgpu_fpriv fpriv, uint32_t id)
	124	{
d38ceaf9	125	struct amdgpu_ctx *ctx;
d38ceaf9	126
23ca0e4e CZ	127	if (fpriv) {
	128	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	129	mutex_lock(&mgr->lock);
	130	ctx = idr_find(&mgr->ctx_handles, id);
	131	if (ctx) {
	132	idr_remove(&mgr->ctx_handles, id);
	133	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	134	mutex_unlock(&mgr->lock);
	135	return 0;
	136	}
0147ee0f	137	mutex_unlock(&mgr->lock);
23ca0e4e CZ	138	} else {
	139	ctx = adev->kernel_ctx;
	140	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
f11358da	141	return 0;
d38ceaf9 AD	142	}
	143	return -EINVAL;
	144	}
	145
d94aed5a MO	146	static int amdgpu_ctx_query(struct amdgpu_device *adev,
	147	struct amdgpu_fpriv *fpriv, uint32_t id,
	148	union drm_amdgpu_ctx_out *out)
d38ceaf9 AD	149	{
d38ceaf9 AD	150	struct amdgpu_ctx *ctx;
23ca0e4e	151	struct amdgpu_ctx_mgr *mgr;
d94aed5a	152	unsigned reset_counter;
d38ceaf9	153
23ca0e4e CZ	154	if (!fpriv)
	155	return -EINVAL;
	156
	157	mgr = &fpriv->ctx_mgr;
0147ee0f	158	mutex_lock(&mgr->lock);
d38ceaf9	159	ctx = idr_find(&mgr->ctx_handles, id);
d94aed5a	160	if (!ctx) {
0147ee0f	161	mutex_unlock(&mgr->lock);
d94aed5a	162	return -EINVAL;
d38ceaf9	163	}
d94aed5a MO	164
d94aed5a MO	165	/* TODO: these two are always zero */
0b492a4c AD	166	out->state.flags = 0x0;
0b492a4c AD	167	out->state.hangs = 0x0;
d94aed5a MO	168
	169	/* determine if a GPU reset has occured since the last call */
	170	reset_counter = atomic_read(&adev->gpu_reset_counter);
	171	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	172	if (ctx->reset_counter == reset_counter)
	173	out->state.reset_status = AMDGPU_CTX_NO_RESET;
	174	else
	175	out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	176	ctx->reset_counter = reset_counter;
	177
0147ee0f	178	mutex_unlock(&mgr->lock);
d94aed5a	179	return 0;
d38ceaf9 AD	180	}
d38ceaf9 AD	181
d38ceaf9	182	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
d94aed5a	183	struct drm_file *filp)
d38ceaf9 AD	184	{
	185	int r;
	186	uint32_t id;
d38ceaf9 AD	187
	188	union drm_amdgpu_ctx *args = data;
	189	struct amdgpu_device *adev = dev->dev_private;
	190	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	191
	192	r = 0;
	193	id = args->in.ctx_id;
d38ceaf9 AD	194
	195	switch (args->in.op) {
	196	case AMDGPU_CTX_OP_ALLOC_CTX:
0b492a4c	197	r = amdgpu_ctx_alloc(adev, fpriv, &id);
d38ceaf9 AD	198	args->out.alloc.ctx_id = id;
	199	break;
	200	case AMDGPU_CTX_OP_FREE_CTX:
	201	r = amdgpu_ctx_free(adev, fpriv, id);
	202	break;
	203	case AMDGPU_CTX_OP_QUERY_STATE:
d94aed5a	204	r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
d38ceaf9 AD	205	break;
	206	default:
	207	return -EINVAL;
	208	}
	209
	210	return r;
	211	}
66b3cf2a JZ	212
	213	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id)
	214	{
	215	struct amdgpu_ctx *ctx;
23ca0e4e CZ	216	struct amdgpu_ctx_mgr *mgr;
	217
	218	if (!fpriv)
	219	return NULL;
	220
	221	mgr = &fpriv->ctx_mgr;
66b3cf2a JZ	222
	223	mutex_lock(&mgr->lock);
	224	ctx = idr_find(&mgr->ctx_handles, id);
	225	if (ctx)
	226	kref_get(&ctx->refcount);
	227	mutex_unlock(&mgr->lock);
	228	return ctx;
	229	}
	230
	231	int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
	232	{
66b3cf2a JZ	233	if (ctx == NULL)
	234	return -EINVAL;
	235
66b3cf2a	236	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
66b3cf2a JZ	237	return 0;
66b3cf2a JZ	238	}
21c16bf6 CK	239
21c16bf6 CK	240	uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx ctx, struct amdgpu_ring ring,
d1ff9086	241	struct fence *fence, uint64_t queued_seq)
21c16bf6 CK	242	{
21c16bf6 CK	243	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
b43a9a7e CZ	244	uint64_t seq = 0;
	245	unsigned idx = 0;
	246	struct fence *other = NULL;
21c16bf6	247
b43a9a7e	248	if (amdgpu_enable_scheduler)
d1ff9086	249	seq = queued_seq;
b43a9a7e CZ	250	else
	251	seq = cring->sequence;
	252	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
	253	other = cring->fences[idx];
21c16bf6 CK	254	if (other) {
	255	signed long r;
	256	r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
	257	if (r < 0)
	258	DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	259	}
	260
	261	fence_get(fence);
	262
	263	spin_lock(&ctx->ring_lock);
	264	cring->fences[idx] = fence;
b43a9a7e CZ	265	if (!amdgpu_enable_scheduler)
b43a9a7e CZ	266	cring->sequence++;
21c16bf6 CK	267	spin_unlock(&ctx->ring_lock);
	268
	269	fence_put(other);
	270
	271	return seq;
	272	}
	273
	274	struct fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
	275	struct amdgpu_ring *ring, uint64_t seq)
	276	{
	277	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	278	struct fence *fence;
b43a9a7e	279	uint64_t queued_seq;
4b559c90 CZ	280	int r;
	281
	282	if (amdgpu_enable_scheduler) {
	283	r = amd_sched_wait_emit(&cring->c_entity,
	284	seq,
51b9db27 CZ	285	false,
51b9db27 CZ	286	-1);
4b559c90 CZ	287	if (r)
	288	return NULL;
	289	}
21c16bf6 CK	290
21c16bf6 CK	291	spin_lock(&ctx->ring_lock);
b43a9a7e	292	if (amdgpu_enable_scheduler)
27f6642d	293	queued_seq = amd_sched_next_queued_seq(&cring->c_entity);
b43a9a7e CZ	294	else
	295	queued_seq = cring->sequence;
	296
	297	if (seq >= queued_seq) {
21c16bf6 CK	298	spin_unlock(&ctx->ring_lock);
	299	return ERR_PTR(-EINVAL);
	300	}
	301
b43a9a7e CZ	302
b43a9a7e CZ	303	if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) {
21c16bf6 CK	304	spin_unlock(&ctx->ring_lock);
	305	return NULL;
	306	}
	307
	308	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	309	spin_unlock(&ctx->ring_lock);
	310
	311	return fence;
	312	}
efd4ccb5 CK	313
	314	void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
	315	{
	316	mutex_init(&mgr->lock);
	317	idr_init(&mgr->ctx_handles);
	318	}
	319
	320	void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
	321	{
	322	struct amdgpu_ctx *ctx;
	323	struct idr *idp;
	324	uint32_t id;
	325
	326	idp = &mgr->ctx_handles;
	327
	328	idr_for_each_entry(idp, ctx, id) {
	329	if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
	330	DRM_ERROR("ctx %p is still alive\n", ctx);
	331	}
	332
	333	idr_destroy(&mgr->ctx_handles);
	334	mutex_destroy(&mgr->lock);
	335	}