[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: monk liu <monk.liu@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"

static void amdgpu_ctx_do_release(struct kref *ref)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_device *adev;
	unsigned i, j;

	ctx = container_of(ref, struct amdgpu_ctx, refcount);
	adev = ctx->adev;


	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
			fence_put(ctx->rings[i].fences[j]);

	if (amdgpu_enable_scheduler) {
		for (i = 0; i < adev->num_rings; i++)
			amd_context_entity_fini(adev->rings[i]->scheduler,
						&ctx->rings[i].c_entity);
	}

	kfree(ctx);
}

static void amdgpu_ctx_init(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv,
			    struct amdgpu_ctx *ctx,
			    uint32_t id)
{
	int i;
	memset(ctx, 0, sizeof(*ctx));
	ctx->adev = adev;
	kref_init(&ctx->refcount);
	spin_lock_init(&ctx->ring_lock);
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		ctx->rings[i].sequence = 1;
}

int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
		     uint32_t *id)
{
	struct amdgpu_ctx *ctx;
	int i, j, r;

	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;
	if (fpriv) {
		struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
		mutex_lock(&mgr->lock);
		r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
		if (r < 0) {
			mutex_unlock(&mgr->lock);
			kfree(ctx);
			return r;
		}
		*id = (uint32_t)r;
		amdgpu_ctx_init(adev, fpriv, ctx, *id);
		mutex_unlock(&mgr->lock);
	} else {
		if (adev->kernel_ctx) {
			DRM_ERROR("kernel cnotext has been created.\n");
			kfree(ctx);
			return 0;
		}
		*id = AMD_KERNEL_CONTEXT_ID;
		amdgpu_ctx_init(adev, fpriv, ctx, *id);

		adev->kernel_ctx = ctx;
	}

	if (amdgpu_enable_scheduler) {
		/* create context entity for each ring */
		for (i = 0; i < adev->num_rings; i++) {
			struct amd_run_queue *rq;
			if (fpriv)
				rq = &adev->rings[i]->scheduler->sched_rq;
			else
				rq = &adev->rings[i]->scheduler->kernel_rq;
			r = amd_context_entity_init(adev->rings[i]->scheduler,
						    &ctx->rings[i].c_entity,
						    NULL, rq, *id,
						    amdgpu_sched_jobs);
			if (r)
				break;
		}

		if (i < adev->num_rings) {
			for (j = 0; j < i; j++)
				amd_context_entity_fini(adev->rings[j]->scheduler,
							&ctx->rings[j].c_entity);
			kfree(ctx);
			return -EINVAL;
		}
	}

	return 0;
}

int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;

	if (fpriv) {
		struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
		mutex_lock(&mgr->lock);
		ctx = idr_find(&mgr->ctx_handles, id);
		if (ctx) {
			idr_remove(&mgr->ctx_handles, id);
			kref_put(&ctx->refcount, amdgpu_ctx_do_release);
			mutex_unlock(&mgr->lock);
			return 0;
		}
		mutex_unlock(&mgr->lock);
	} else {
		ctx = adev->kernel_ctx;
		kref_put(&ctx->refcount, amdgpu_ctx_do_release);
		return 0;
	}
	return -EINVAL;
}

static int amdgpu_ctx_query(struct amdgpu_device *adev,
			    struct amdgpu_fpriv *fpriv, uint32_t id,
			    union drm_amdgpu_ctx_out *out)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;
	unsigned reset_counter;

	if (!fpriv)
		return -EINVAL;

	mgr = &fpriv->ctx_mgr;
	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (!ctx) {
		mutex_unlock(&mgr->lock);
		return -EINVAL;
	}

	/* TODO: these two are always zero */
	out->state.flags = 0x0;
	out->state.hangs = 0x0;

	/* determine if a GPU reset has occured since the last call */
	reset_counter = atomic_read(&adev->gpu_reset_counter);
	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	if (ctx->reset_counter == reset_counter)
		out->state.reset_status = AMDGPU_CTX_NO_RESET;
	else
		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	ctx->reset_counter = reset_counter;

	mutex_unlock(&mgr->lock);
	return 0;
}

void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
{
	struct idr *idp;
	struct amdgpu_ctx *ctx;
	uint32_t id;
	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	idp = &mgr->ctx_handles;

	idr_for_each_entry(idp,ctx,id) {
		if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
			DRM_ERROR("ctx %p is still alive\n", ctx);
	}

	idr_destroy(&mgr->ctx_handles);
	mutex_destroy(&mgr->lock);
}

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
		     struct drm_file *filp)
{
	int r;
	uint32_t id;

	union drm_amdgpu_ctx *args = data;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;

	r = 0;
	id = args->in.ctx_id;

	switch (args->in.op) {
		case AMDGPU_CTX_OP_ALLOC_CTX:
			r = amdgpu_ctx_alloc(adev, fpriv, &id);
			args->out.alloc.ctx_id = id;
			break;
		case AMDGPU_CTX_OP_FREE_CTX:
			r = amdgpu_ctx_free(adev, fpriv, id);
			break;
		case AMDGPU_CTX_OP_QUERY_STATE:
			r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
			break;
		default:
			return -EINVAL;
	}

	return r;
}

struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
{
	struct amdgpu_ctx *ctx;
	struct amdgpu_ctx_mgr *mgr;

	if (!fpriv)
		return NULL;

	mgr = &fpriv->ctx_mgr;

	mutex_lock(&mgr->lock);
	ctx = idr_find(&mgr->ctx_handles, id);
	if (ctx)
		kref_get(&ctx->refcount);
	mutex_unlock(&mgr->lock);
	return ctx;
}

int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
{
	if (ctx == NULL)
		return -EINVAL;

	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	return 0;
}

uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
			      struct fence *fence)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	uint64_t seq = 0;
	unsigned idx = 0;
	struct fence *other = NULL;

	if (amdgpu_enable_scheduler)
		seq = atomic64_read(&cring->c_entity.last_queued_v_seq);
	else
		seq = cring->sequence;
	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
	other = cring->fences[idx];
	if (other) {
		signed long r;
		r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
		if (r < 0)
			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	}

	fence_get(fence);

	spin_lock(&ctx->ring_lock);
	cring->fences[idx] = fence;
	if (!amdgpu_enable_scheduler)
		cring->sequence++;
	spin_unlock(&ctx->ring_lock);

	fence_put(other);

	return seq;
}

struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
				   struct amdgpu_ring *ring, uint64_t seq)
{
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;
	uint64_t queued_seq;
	int r;

	if (amdgpu_enable_scheduler) {
		r = amd_sched_wait_emit(&cring->c_entity,
					seq,
					false,
					-1);
		if (r)
			return NULL;
	}

	spin_lock(&ctx->ring_lock);
	if (amdgpu_enable_scheduler)
		queued_seq = atomic64_read(&cring->c_entity.last_queued_v_seq) + 1;
	else
		queued_seq = cring->sequence;

	if (seq >= queued_seq) {
		spin_unlock(&ctx->ring_lock);
		return ERR_PTR(-EINVAL);
	}


	if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) {
		spin_unlock(&ctx->ring_lock);
		return NULL;
	}

	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	spin_unlock(&ctx->ring_lock);

	return fence;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: monk liu <monk.liu@amd.com>
	23	*/
	24
	25	#include <drm/drmP.h>
	26	#include "amdgpu.h"
	27
	28	static void amdgpu_ctx_do_release(struct kref *ref)
	29	{
	30	struct amdgpu_ctx *ctx;
9cb7e5a9	31	struct amdgpu_device *adev;
21c16bf6	32	unsigned i, j;
d38ceaf9 AD	33
d38ceaf9 AD	34	ctx = container_of(ref, struct amdgpu_ctx, refcount);
9cb7e5a9 CZ	35	adev = ctx->adev;
9cb7e5a9 CZ	36
21c16bf6 CK	37
	38	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	39	for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
	40	fence_put(ctx->rings[i].fences[j]);
9cb7e5a9 CZ	41
	42	if (amdgpu_enable_scheduler) {
	43	for (i = 0; i < adev->num_rings; i++)
	44	amd_context_entity_fini(adev->rings[i]->scheduler,
	45	&ctx->rings[i].c_entity);
	46	}
	47
d38ceaf9 AD	48	kfree(ctx);
	49	}
	50
23ca0e4e CZ	51	static void amdgpu_ctx_init(struct amdgpu_device *adev,
	52	struct amdgpu_fpriv *fpriv,
	53	struct amdgpu_ctx *ctx,
	54	uint32_t id)
	55	{
	56	int i;
	57	memset(ctx, 0, sizeof(*ctx));
	58	ctx->adev = adev;
	59	kref_init(&ctx->refcount);
	60	spin_lock_init(&ctx->ring_lock);
	61	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	62	ctx->rings[i].sequence = 1;
	63	}
	64
0b492a4c AD	65	int amdgpu_ctx_alloc(struct amdgpu_device adev, struct amdgpu_fpriv fpriv,
0b492a4c AD	66	uint32_t *id)
d38ceaf9	67	{
d38ceaf9	68	struct amdgpu_ctx *ctx;
9cb7e5a9	69	int i, j, r;
d38ceaf9 AD	70
	71	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
	72	if (!ctx)
	73	return -ENOMEM;
23ca0e4e CZ	74	if (fpriv) {
	75	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	76	mutex_lock(&mgr->lock);
	77	r = idr_alloc(&mgr->ctx_handles, ctx, 1, 0, GFP_KERNEL);
	78	if (r < 0) {
	79	mutex_unlock(&mgr->lock);
	80	kfree(ctx);
	81	return r;
	82	}
	83	*id = (uint32_t)r;
	84	amdgpu_ctx_init(adev, fpriv, ctx, *id);
0147ee0f	85	mutex_unlock(&mgr->lock);
23ca0e4e CZ	86	} else {
	87	if (adev->kernel_ctx) {
	88	DRM_ERROR("kernel cnotext has been created.\n");
	89	kfree(ctx);
	90	return 0;
	91	}
	92	*id = AMD_KERNEL_CONTEXT_ID;
	93	amdgpu_ctx_init(adev, fpriv, ctx, *id);
	94
	95	adev->kernel_ctx = ctx;
d38ceaf9	96	}
d38ceaf9	97
9cb7e5a9 CZ	98	if (amdgpu_enable_scheduler) {
	99	/* create context entity for each ring */
	100	for (i = 0; i < adev->num_rings; i++) {
	101	struct amd_run_queue *rq;
	102	if (fpriv)
	103	rq = &adev->rings[i]->scheduler->sched_rq;
	104	else
	105	rq = &adev->rings[i]->scheduler->kernel_rq;
	106	r = amd_context_entity_init(adev->rings[i]->scheduler,
	107	&ctx->rings[i].c_entity,
1333f723 JZ	108	NULL, rq, *id,
1333f723 JZ	109	amdgpu_sched_jobs);
9cb7e5a9 CZ	110	if (r)
	111	break;
	112	}
	113
	114	if (i < adev->num_rings) {
	115	for (j = 0; j < i; j++)
	116	amd_context_entity_fini(adev->rings[j]->scheduler,
	117	&ctx->rings[j].c_entity);
	118	kfree(ctx);
	119	return -EINVAL;
	120	}
	121	}
d38ceaf9 AD	122
	123	return 0;
	124	}
	125
	126	int amdgpu_ctx_free(struct amdgpu_device adev, struct amdgpu_fpriv fpriv, uint32_t id)
	127	{
d38ceaf9	128	struct amdgpu_ctx *ctx;
d38ceaf9	129
23ca0e4e CZ	130	if (fpriv) {
	131	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	132	mutex_lock(&mgr->lock);
	133	ctx = idr_find(&mgr->ctx_handles, id);
	134	if (ctx) {
	135	idr_remove(&mgr->ctx_handles, id);
	136	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
	137	mutex_unlock(&mgr->lock);
	138	return 0;
	139	}
0147ee0f	140	mutex_unlock(&mgr->lock);
23ca0e4e CZ	141	} else {
	142	ctx = adev->kernel_ctx;
	143	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
f11358da	144	return 0;
d38ceaf9 AD	145	}
	146	return -EINVAL;
	147	}
	148
d94aed5a MO	149	static int amdgpu_ctx_query(struct amdgpu_device *adev,
	150	struct amdgpu_fpriv *fpriv, uint32_t id,
	151	union drm_amdgpu_ctx_out *out)
d38ceaf9 AD	152	{
d38ceaf9 AD	153	struct amdgpu_ctx *ctx;
23ca0e4e	154	struct amdgpu_ctx_mgr *mgr;
d94aed5a	155	unsigned reset_counter;
d38ceaf9	156
23ca0e4e CZ	157	if (!fpriv)
	158	return -EINVAL;
	159
	160	mgr = &fpriv->ctx_mgr;
0147ee0f	161	mutex_lock(&mgr->lock);
d38ceaf9	162	ctx = idr_find(&mgr->ctx_handles, id);
d94aed5a	163	if (!ctx) {
0147ee0f	164	mutex_unlock(&mgr->lock);
d94aed5a	165	return -EINVAL;
d38ceaf9	166	}
d94aed5a MO	167
d94aed5a MO	168	/* TODO: these two are always zero */
0b492a4c AD	169	out->state.flags = 0x0;
0b492a4c AD	170	out->state.hangs = 0x0;
d94aed5a MO	171
	172	/* determine if a GPU reset has occured since the last call */
	173	reset_counter = atomic_read(&adev->gpu_reset_counter);
	174	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
	175	if (ctx->reset_counter == reset_counter)
	176	out->state.reset_status = AMDGPU_CTX_NO_RESET;
	177	else
	178	out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
	179	ctx->reset_counter = reset_counter;
	180
0147ee0f	181	mutex_unlock(&mgr->lock);
d94aed5a	182	return 0;
d38ceaf9 AD	183	}
	184
	185	void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
	186	{
	187	struct idr *idp;
	188	struct amdgpu_ctx *ctx;
	189	uint32_t id;
	190	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
	191	idp = &mgr->ctx_handles;
	192
	193	idr_for_each_entry(idp,ctx,id) {
	194	if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
0b492a4c	195	DRM_ERROR("ctx %p is still alive\n", ctx);
d38ceaf9 AD	196	}
d38ceaf9 AD	197
cdecb65b	198	idr_destroy(&mgr->ctx_handles);
0147ee0f	199	mutex_destroy(&mgr->lock);
d38ceaf9 AD	200	}
	201
	202	int amdgpu_ctx_ioctl(struct drm_device dev, void data,
d94aed5a	203	struct drm_file *filp)
d38ceaf9 AD	204	{
	205	int r;
	206	uint32_t id;
d38ceaf9 AD	207
	208	union drm_amdgpu_ctx *args = data;
	209	struct amdgpu_device *adev = dev->dev_private;
	210	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	211
	212	r = 0;
	213	id = args->in.ctx_id;
d38ceaf9 AD	214
	215	switch (args->in.op) {
	216	case AMDGPU_CTX_OP_ALLOC_CTX:
0b492a4c	217	r = amdgpu_ctx_alloc(adev, fpriv, &id);
d38ceaf9 AD	218	args->out.alloc.ctx_id = id;
	219	break;
	220	case AMDGPU_CTX_OP_FREE_CTX:
	221	r = amdgpu_ctx_free(adev, fpriv, id);
	222	break;
	223	case AMDGPU_CTX_OP_QUERY_STATE:
d94aed5a	224	r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
d38ceaf9 AD	225	break;
	226	default:
	227	return -EINVAL;
	228	}
	229
	230	return r;
	231	}
66b3cf2a JZ	232
	233	struct amdgpu_ctx amdgpu_ctx_get(struct amdgpu_fpriv fpriv, uint32_t id)
	234	{
	235	struct amdgpu_ctx *ctx;
23ca0e4e CZ	236	struct amdgpu_ctx_mgr *mgr;
	237
	238	if (!fpriv)
	239	return NULL;
	240
	241	mgr = &fpriv->ctx_mgr;
66b3cf2a JZ	242
	243	mutex_lock(&mgr->lock);
	244	ctx = idr_find(&mgr->ctx_handles, id);
	245	if (ctx)
	246	kref_get(&ctx->refcount);
	247	mutex_unlock(&mgr->lock);
	248	return ctx;
	249	}
	250
	251	int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
	252	{
66b3cf2a JZ	253	if (ctx == NULL)
	254	return -EINVAL;
	255
66b3cf2a	256	kref_put(&ctx->refcount, amdgpu_ctx_do_release);
66b3cf2a JZ	257	return 0;
66b3cf2a JZ	258	}
21c16bf6 CK	259
	260	uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx ctx, struct amdgpu_ring ring,
	261	struct fence *fence)
	262	{
	263	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
b43a9a7e CZ	264	uint64_t seq = 0;
	265	unsigned idx = 0;
	266	struct fence *other = NULL;
21c16bf6	267
b43a9a7e CZ	268	if (amdgpu_enable_scheduler)
	269	seq = atomic64_read(&cring->c_entity.last_queued_v_seq);
	270	else
	271	seq = cring->sequence;
	272	idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
	273	other = cring->fences[idx];
21c16bf6 CK	274	if (other) {
	275	signed long r;
	276	r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
	277	if (r < 0)
	278	DRM_ERROR("Error (%ld) waiting for fence!\n", r);
	279	}
	280
	281	fence_get(fence);
	282
	283	spin_lock(&ctx->ring_lock);
	284	cring->fences[idx] = fence;
b43a9a7e CZ	285	if (!amdgpu_enable_scheduler)
b43a9a7e CZ	286	cring->sequence++;
21c16bf6 CK	287	spin_unlock(&ctx->ring_lock);
	288
	289	fence_put(other);
	290
	291	return seq;
	292	}
	293
	294	struct fence amdgpu_ctx_get_fence(struct amdgpu_ctx ctx,
	295	struct amdgpu_ring *ring, uint64_t seq)
	296	{
	297	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	298	struct fence *fence;
b43a9a7e	299	uint64_t queued_seq;
4b559c90 CZ	300	int r;
	301
	302	if (amdgpu_enable_scheduler) {
	303	r = amd_sched_wait_emit(&cring->c_entity,
	304	seq,
51b9db27 CZ	305	false,
51b9db27 CZ	306	-1);
4b559c90 CZ	307	if (r)
	308	return NULL;
	309	}
21c16bf6 CK	310
21c16bf6 CK	311	spin_lock(&ctx->ring_lock);
b43a9a7e CZ	312	if (amdgpu_enable_scheduler)
	313	queued_seq = atomic64_read(&cring->c_entity.last_queued_v_seq) + 1;
	314	else
	315	queued_seq = cring->sequence;
	316
	317	if (seq >= queued_seq) {
21c16bf6 CK	318	spin_unlock(&ctx->ring_lock);
	319	return ERR_PTR(-EINVAL);
	320	}
	321
b43a9a7e CZ	322
b43a9a7e CZ	323	if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) {
21c16bf6 CK	324	spin_unlock(&ctx->ring_lock);
	325	return NULL;
	326	}
	327
	328	fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
	329	spin_unlock(&ctx->ring_lock);
	330
	331	return fence;
	332	}