drm/amdgpu: allow unaligned memory access (v2)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ctx.c
CommitLineData
d38ceaf9
AD
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: monk liu <monk.liu@amd.com>
23 */
24
25#include <drm/drmP.h>
26#include "amdgpu.h"
27
28static void amdgpu_ctx_do_release(struct kref *ref)
29{
30 struct amdgpu_ctx *ctx;
31 struct amdgpu_ctx_mgr *mgr;
32
33 ctx = container_of(ref, struct amdgpu_ctx, refcount);
34 mgr = &ctx->fpriv->ctx_mgr;
35
d38ceaf9 36 idr_remove(&mgr->ctx_handles, ctx->id);
d38ceaf9
AD
37 kfree(ctx);
38}
39
40int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t *id, uint32_t flags)
41{
42 int r;
43 struct amdgpu_ctx *ctx;
44 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
45
46 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
47 if (!ctx)
48 return -ENOMEM;
49
0147ee0f 50 mutex_lock(&mgr->lock);
d38ceaf9
AD
51 r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL);
52 if (r < 0) {
0147ee0f 53 mutex_unlock(&mgr->lock);
d38ceaf9
AD
54 kfree(ctx);
55 return r;
56 }
d38ceaf9
AD
57 *id = (uint32_t)r;
58
59 memset(ctx, 0, sizeof(*ctx));
60 ctx->id = *id;
61 ctx->fpriv = fpriv;
62 kref_init(&ctx->refcount);
0147ee0f 63 mutex_unlock(&mgr->lock);
d38ceaf9
AD
64
65 return 0;
66}
67
68int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
69{
d38ceaf9
AD
70 struct amdgpu_ctx *ctx;
71 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
72
0147ee0f 73 mutex_lock(&mgr->lock);
d38ceaf9 74 ctx = idr_find(&mgr->ctx_handles, id);
d38ceaf9 75 if (ctx) {
f11358da 76 kref_put(&ctx->refcount, amdgpu_ctx_do_release);
0147ee0f 77 mutex_unlock(&mgr->lock);
f11358da 78 return 0;
d38ceaf9 79 }
0147ee0f 80 mutex_unlock(&mgr->lock);
d38ceaf9
AD
81 return -EINVAL;
82}
83
84int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id, struct amdgpu_ctx_state *state)
85{
86 struct amdgpu_ctx *ctx;
87 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
88
0147ee0f 89 mutex_lock(&mgr->lock);
d38ceaf9 90 ctx = idr_find(&mgr->ctx_handles, id);
d38ceaf9
AD
91 if (ctx) {
92 /* state should alter with CS activity */
93 *state = ctx->state;
0147ee0f 94 mutex_unlock(&mgr->lock);
d38ceaf9
AD
95 return 0;
96 }
0147ee0f 97 mutex_unlock(&mgr->lock);
d38ceaf9
AD
98 return -EINVAL;
99}
100
101void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
102{
103 struct idr *idp;
104 struct amdgpu_ctx *ctx;
105 uint32_t id;
106 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
107 idp = &mgr->ctx_handles;
108
109 idr_for_each_entry(idp,ctx,id) {
110 if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
111 DRM_ERROR("ctx (id=%ul) is still alive\n",ctx->id);
112 }
113
0147ee0f 114 mutex_destroy(&mgr->lock);
d38ceaf9
AD
115}
116
117int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
118 struct drm_file *filp)
119{
120 int r;
121 uint32_t id;
122 uint32_t flags;
123 struct amdgpu_ctx_state state;
124
125 union drm_amdgpu_ctx *args = data;
126 struct amdgpu_device *adev = dev->dev_private;
127 struct amdgpu_fpriv *fpriv = filp->driver_priv;
128
129 r = 0;
130 id = args->in.ctx_id;
131 flags = args->in.flags;
132
133 switch (args->in.op) {
134 case AMDGPU_CTX_OP_ALLOC_CTX:
135 r = amdgpu_ctx_alloc(adev, fpriv, &id, flags);
136 args->out.alloc.ctx_id = id;
137 break;
138 case AMDGPU_CTX_OP_FREE_CTX:
139 r = amdgpu_ctx_free(adev, fpriv, id);
140 break;
141 case AMDGPU_CTX_OP_QUERY_STATE:
142 r = amdgpu_ctx_query(adev, fpriv, id, &state);
143 if (r == 0) {
144 args->out.state.flags = state.flags;
145 args->out.state.hangs = state.hangs;
146 }
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 return r;
153}
This page took 0.033112 seconds and 5 git commands to generate.