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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: monk liu <monk.liu@amd.com> | |
23 | */ | |
24 | ||
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | ||
28 | static void amdgpu_ctx_do_release(struct kref *ref) | |
29 | { | |
30 | struct amdgpu_ctx *ctx; | |
d38ceaf9 AD |
31 | |
32 | ctx = container_of(ref, struct amdgpu_ctx, refcount); | |
d38ceaf9 AD |
33 | kfree(ctx); |
34 | } | |
35 | ||
0b492a4c AD |
36 | int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, |
37 | uint32_t *id) | |
d38ceaf9 AD |
38 | { |
39 | int r; | |
40 | struct amdgpu_ctx *ctx; | |
41 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
42 | ||
43 | ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); | |
44 | if (!ctx) | |
45 | return -ENOMEM; | |
46 | ||
0147ee0f | 47 | mutex_lock(&mgr->lock); |
d38ceaf9 AD |
48 | r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL); |
49 | if (r < 0) { | |
0147ee0f | 50 | mutex_unlock(&mgr->lock); |
d38ceaf9 AD |
51 | kfree(ctx); |
52 | return r; | |
53 | } | |
d38ceaf9 AD |
54 | *id = (uint32_t)r; |
55 | ||
56 | memset(ctx, 0, sizeof(*ctx)); | |
d38ceaf9 | 57 | kref_init(&ctx->refcount); |
0147ee0f | 58 | mutex_unlock(&mgr->lock); |
d38ceaf9 AD |
59 | |
60 | return 0; | |
61 | } | |
62 | ||
63 | int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id) | |
64 | { | |
d38ceaf9 AD |
65 | struct amdgpu_ctx *ctx; |
66 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
67 | ||
0147ee0f | 68 | mutex_lock(&mgr->lock); |
d38ceaf9 | 69 | ctx = idr_find(&mgr->ctx_handles, id); |
d38ceaf9 | 70 | if (ctx) { |
0b492a4c | 71 | idr_remove(&mgr->ctx_handles, id); |
f11358da | 72 | kref_put(&ctx->refcount, amdgpu_ctx_do_release); |
0147ee0f | 73 | mutex_unlock(&mgr->lock); |
f11358da | 74 | return 0; |
d38ceaf9 | 75 | } |
0147ee0f | 76 | mutex_unlock(&mgr->lock); |
d38ceaf9 AD |
77 | return -EINVAL; |
78 | } | |
79 | ||
d94aed5a MO |
80 | static int amdgpu_ctx_query(struct amdgpu_device *adev, |
81 | struct amdgpu_fpriv *fpriv, uint32_t id, | |
82 | union drm_amdgpu_ctx_out *out) | |
d38ceaf9 AD |
83 | { |
84 | struct amdgpu_ctx *ctx; | |
85 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
d94aed5a | 86 | unsigned reset_counter; |
d38ceaf9 | 87 | |
0147ee0f | 88 | mutex_lock(&mgr->lock); |
d38ceaf9 | 89 | ctx = idr_find(&mgr->ctx_handles, id); |
d94aed5a | 90 | if (!ctx) { |
0147ee0f | 91 | mutex_unlock(&mgr->lock); |
d94aed5a | 92 | return -EINVAL; |
d38ceaf9 | 93 | } |
d94aed5a MO |
94 | |
95 | /* TODO: these two are always zero */ | |
0b492a4c AD |
96 | out->state.flags = 0x0; |
97 | out->state.hangs = 0x0; | |
d94aed5a MO |
98 | |
99 | /* determine if a GPU reset has occured since the last call */ | |
100 | reset_counter = atomic_read(&adev->gpu_reset_counter); | |
101 | /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ | |
102 | if (ctx->reset_counter == reset_counter) | |
103 | out->state.reset_status = AMDGPU_CTX_NO_RESET; | |
104 | else | |
105 | out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; | |
106 | ctx->reset_counter = reset_counter; | |
107 | ||
0147ee0f | 108 | mutex_unlock(&mgr->lock); |
d94aed5a | 109 | return 0; |
d38ceaf9 AD |
110 | } |
111 | ||
112 | void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv) | |
113 | { | |
114 | struct idr *idp; | |
115 | struct amdgpu_ctx *ctx; | |
116 | uint32_t id; | |
117 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
118 | idp = &mgr->ctx_handles; | |
119 | ||
120 | idr_for_each_entry(idp,ctx,id) { | |
121 | if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1) | |
0b492a4c | 122 | DRM_ERROR("ctx %p is still alive\n", ctx); |
d38ceaf9 AD |
123 | } |
124 | ||
0147ee0f | 125 | mutex_destroy(&mgr->lock); |
d38ceaf9 AD |
126 | } |
127 | ||
128 | int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, | |
d94aed5a | 129 | struct drm_file *filp) |
d38ceaf9 AD |
130 | { |
131 | int r; | |
132 | uint32_t id; | |
d38ceaf9 AD |
133 | |
134 | union drm_amdgpu_ctx *args = data; | |
135 | struct amdgpu_device *adev = dev->dev_private; | |
136 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
137 | ||
138 | r = 0; | |
139 | id = args->in.ctx_id; | |
d38ceaf9 AD |
140 | |
141 | switch (args->in.op) { | |
142 | case AMDGPU_CTX_OP_ALLOC_CTX: | |
0b492a4c | 143 | r = amdgpu_ctx_alloc(adev, fpriv, &id); |
d38ceaf9 AD |
144 | args->out.alloc.ctx_id = id; |
145 | break; | |
146 | case AMDGPU_CTX_OP_FREE_CTX: | |
147 | r = amdgpu_ctx_free(adev, fpriv, id); | |
148 | break; | |
149 | case AMDGPU_CTX_OP_QUERY_STATE: | |
d94aed5a | 150 | r = amdgpu_ctx_query(adev, fpriv, id, &args->out); |
d38ceaf9 AD |
151 | break; |
152 | default: | |
153 | return -EINVAL; | |
154 | } | |
155 | ||
156 | return r; | |
157 | } | |
66b3cf2a JZ |
158 | |
159 | struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) | |
160 | { | |
161 | struct amdgpu_ctx *ctx; | |
162 | struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; | |
163 | ||
164 | mutex_lock(&mgr->lock); | |
165 | ctx = idr_find(&mgr->ctx_handles, id); | |
166 | if (ctx) | |
167 | kref_get(&ctx->refcount); | |
168 | mutex_unlock(&mgr->lock); | |
169 | return ctx; | |
170 | } | |
171 | ||
172 | int amdgpu_ctx_put(struct amdgpu_ctx *ctx) | |
173 | { | |
66b3cf2a JZ |
174 | if (ctx == NULL) |
175 | return -EINVAL; | |
176 | ||
66b3cf2a | 177 | kref_put(&ctx->refcount, amdgpu_ctx_do_release); |
66b3cf2a JZ |
178 | return 0; |
179 | } |