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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
d0dd7f0c | 43 | #include "amd_pcie.h" |
a2e73f56 AD |
44 | #ifdef CONFIG_DRM_AMDGPU_CIK |
45 | #include "cik.h" | |
46 | #endif | |
aaa36a97 | 47 | #include "vi.h" |
d38ceaf9 AD |
48 | #include "bif/bif_4_1_d.h" |
49 | ||
50 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
51 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
52 | ||
53 | static const char *amdgpu_asic_name[] = { | |
54 | "BONAIRE", | |
55 | "KAVERI", | |
56 | "KABINI", | |
57 | "HAWAII", | |
58 | "MULLINS", | |
59 | "TOPAZ", | |
60 | "TONGA", | |
48299f95 | 61 | "FIJI", |
d38ceaf9 | 62 | "CARRIZO", |
139f4917 | 63 | "STONEY", |
2cc0c0b5 FC |
64 | "POLARIS10", |
65 | "POLARIS11", | |
d38ceaf9 AD |
66 | "LAST", |
67 | }; | |
68 | ||
69 | bool amdgpu_device_is_px(struct drm_device *dev) | |
70 | { | |
71 | struct amdgpu_device *adev = dev->dev_private; | |
72 | ||
2f7d10b3 | 73 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
74 | return true; |
75 | return false; | |
76 | } | |
77 | ||
78 | /* | |
79 | * MMIO register access helper functions. | |
80 | */ | |
81 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
82 | bool always_indirect) | |
83 | { | |
f4b373f4 TSD |
84 | uint32_t ret; |
85 | ||
d38ceaf9 | 86 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
f4b373f4 | 87 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
88 | else { |
89 | unsigned long flags; | |
d38ceaf9 AD |
90 | |
91 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
92 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
93 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
94 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 95 | } |
f4b373f4 TSD |
96 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
97 | return ret; | |
d38ceaf9 AD |
98 | } |
99 | ||
100 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
101 | bool always_indirect) | |
102 | { | |
f4b373f4 TSD |
103 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
104 | ||
d38ceaf9 AD |
105 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
106 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
107 | else { | |
108 | unsigned long flags; | |
109 | ||
110 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
111 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
112 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
113 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
114 | } | |
115 | } | |
116 | ||
117 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
118 | { | |
119 | if ((reg * 4) < adev->rio_mem_size) | |
120 | return ioread32(adev->rio_mem + (reg * 4)); | |
121 | else { | |
122 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
123 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
124 | } | |
125 | } | |
126 | ||
127 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
128 | { | |
129 | ||
130 | if ((reg * 4) < adev->rio_mem_size) | |
131 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
132 | else { | |
133 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
134 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
135 | } | |
136 | } | |
137 | ||
138 | /** | |
139 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
140 | * | |
141 | * @adev: amdgpu_device pointer | |
142 | * @index: doorbell index | |
143 | * | |
144 | * Returns the value in the doorbell aperture at the | |
145 | * requested doorbell index (CIK). | |
146 | */ | |
147 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
148 | { | |
149 | if (index < adev->doorbell.num_doorbells) { | |
150 | return readl(adev->doorbell.ptr + index); | |
151 | } else { | |
152 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
153 | return 0; | |
154 | } | |
155 | } | |
156 | ||
157 | /** | |
158 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
159 | * | |
160 | * @adev: amdgpu_device pointer | |
161 | * @index: doorbell index | |
162 | * @v: value to write | |
163 | * | |
164 | * Writes @v to the doorbell aperture at the | |
165 | * requested doorbell index (CIK). | |
166 | */ | |
167 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
168 | { | |
169 | if (index < adev->doorbell.num_doorbells) { | |
170 | writel(v, adev->doorbell.ptr + index); | |
171 | } else { | |
172 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
173 | } | |
174 | } | |
175 | ||
176 | /** | |
177 | * amdgpu_invalid_rreg - dummy reg read function | |
178 | * | |
179 | * @adev: amdgpu device pointer | |
180 | * @reg: offset of register | |
181 | * | |
182 | * Dummy register read function. Used for register blocks | |
183 | * that certain asics don't have (all asics). | |
184 | * Returns the value in the register. | |
185 | */ | |
186 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
187 | { | |
188 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
189 | BUG(); | |
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * amdgpu_invalid_wreg - dummy reg write function | |
195 | * | |
196 | * @adev: amdgpu device pointer | |
197 | * @reg: offset of register | |
198 | * @v: value to write to the register | |
199 | * | |
200 | * Dummy register read function. Used for register blocks | |
201 | * that certain asics don't have (all asics). | |
202 | */ | |
203 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
204 | { | |
205 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
206 | reg, v); | |
207 | BUG(); | |
208 | } | |
209 | ||
210 | /** | |
211 | * amdgpu_block_invalid_rreg - dummy reg read function | |
212 | * | |
213 | * @adev: amdgpu device pointer | |
214 | * @block: offset of instance | |
215 | * @reg: offset of register | |
216 | * | |
217 | * Dummy register read function. Used for register blocks | |
218 | * that certain asics don't have (all asics). | |
219 | * Returns the value in the register. | |
220 | */ | |
221 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
222 | uint32_t block, uint32_t reg) | |
223 | { | |
224 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
225 | reg, block); | |
226 | BUG(); | |
227 | return 0; | |
228 | } | |
229 | ||
230 | /** | |
231 | * amdgpu_block_invalid_wreg - dummy reg write function | |
232 | * | |
233 | * @adev: amdgpu device pointer | |
234 | * @block: offset of instance | |
235 | * @reg: offset of register | |
236 | * @v: value to write to the register | |
237 | * | |
238 | * Dummy register read function. Used for register blocks | |
239 | * that certain asics don't have (all asics). | |
240 | */ | |
241 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
242 | uint32_t block, | |
243 | uint32_t reg, uint32_t v) | |
244 | { | |
245 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
246 | reg, block, v); | |
247 | BUG(); | |
248 | } | |
249 | ||
250 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
251 | { | |
252 | int r; | |
253 | ||
254 | if (adev->vram_scratch.robj == NULL) { | |
255 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d AD |
256 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
257 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 258 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
259 | if (r) { |
260 | return r; | |
261 | } | |
262 | } | |
263 | ||
264 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
265 | if (unlikely(r != 0)) | |
266 | return r; | |
267 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
268 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
269 | if (r) { | |
270 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
271 | return r; | |
272 | } | |
273 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
274 | (void **)&adev->vram_scratch.ptr); | |
275 | if (r) | |
276 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
277 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
278 | ||
279 | return r; | |
280 | } | |
281 | ||
282 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
283 | { | |
284 | int r; | |
285 | ||
286 | if (adev->vram_scratch.robj == NULL) { | |
287 | return; | |
288 | } | |
289 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
290 | if (likely(r == 0)) { | |
291 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
292 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
293 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
294 | } | |
295 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
296 | } | |
297 | ||
298 | /** | |
299 | * amdgpu_program_register_sequence - program an array of registers. | |
300 | * | |
301 | * @adev: amdgpu_device pointer | |
302 | * @registers: pointer to the register array | |
303 | * @array_size: size of the register array | |
304 | * | |
305 | * Programs an array or registers with and and or masks. | |
306 | * This is a helper for setting golden registers. | |
307 | */ | |
308 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
309 | const u32 *registers, | |
310 | const u32 array_size) | |
311 | { | |
312 | u32 tmp, reg, and_mask, or_mask; | |
313 | int i; | |
314 | ||
315 | if (array_size % 3) | |
316 | return; | |
317 | ||
318 | for (i = 0; i < array_size; i +=3) { | |
319 | reg = registers[i + 0]; | |
320 | and_mask = registers[i + 1]; | |
321 | or_mask = registers[i + 2]; | |
322 | ||
323 | if (and_mask == 0xffffffff) { | |
324 | tmp = or_mask; | |
325 | } else { | |
326 | tmp = RREG32(reg); | |
327 | tmp &= ~and_mask; | |
328 | tmp |= or_mask; | |
329 | } | |
330 | WREG32(reg, tmp); | |
331 | } | |
332 | } | |
333 | ||
334 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
335 | { | |
336 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
337 | } | |
338 | ||
339 | /* | |
340 | * GPU doorbell aperture helpers function. | |
341 | */ | |
342 | /** | |
343 | * amdgpu_doorbell_init - Init doorbell driver information. | |
344 | * | |
345 | * @adev: amdgpu_device pointer | |
346 | * | |
347 | * Init doorbell driver information (CIK) | |
348 | * Returns 0 on success, error on failure. | |
349 | */ | |
350 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
351 | { | |
352 | /* doorbell bar mapping */ | |
353 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
354 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
355 | ||
edf600da | 356 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
357 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
358 | if (adev->doorbell.num_doorbells == 0) | |
359 | return -EINVAL; | |
360 | ||
361 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
362 | if (adev->doorbell.ptr == NULL) { | |
363 | return -ENOMEM; | |
364 | } | |
365 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
366 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | /** | |
372 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
373 | * | |
374 | * @adev: amdgpu_device pointer | |
375 | * | |
376 | * Tear down doorbell driver information (CIK) | |
377 | */ | |
378 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
379 | { | |
380 | iounmap(adev->doorbell.ptr); | |
381 | adev->doorbell.ptr = NULL; | |
382 | } | |
383 | ||
384 | /** | |
385 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
386 | * setup amdkfd | |
387 | * | |
388 | * @adev: amdgpu_device pointer | |
389 | * @aperture_base: output returning doorbell aperture base physical address | |
390 | * @aperture_size: output returning doorbell aperture size in bytes | |
391 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
392 | * | |
393 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
394 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
395 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
396 | */ | |
397 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
398 | phys_addr_t *aperture_base, | |
399 | size_t *aperture_size, | |
400 | size_t *start_offset) | |
401 | { | |
402 | /* | |
403 | * The first num_doorbells are used by amdgpu. | |
404 | * amdkfd takes whatever's left in the aperture. | |
405 | */ | |
406 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
407 | *aperture_base = adev->doorbell.base; | |
408 | *aperture_size = adev->doorbell.size; | |
409 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
410 | } else { | |
411 | *aperture_base = 0; | |
412 | *aperture_size = 0; | |
413 | *start_offset = 0; | |
414 | } | |
415 | } | |
416 | ||
417 | /* | |
418 | * amdgpu_wb_*() | |
419 | * Writeback is the the method by which the the GPU updates special pages | |
420 | * in memory with the status of certain GPU events (fences, ring pointers, | |
421 | * etc.). | |
422 | */ | |
423 | ||
424 | /** | |
425 | * amdgpu_wb_fini - Disable Writeback and free memory | |
426 | * | |
427 | * @adev: amdgpu_device pointer | |
428 | * | |
429 | * Disables Writeback and frees the Writeback memory (all asics). | |
430 | * Used at driver shutdown. | |
431 | */ | |
432 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
433 | { | |
434 | if (adev->wb.wb_obj) { | |
435 | if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { | |
436 | amdgpu_bo_kunmap(adev->wb.wb_obj); | |
437 | amdgpu_bo_unpin(adev->wb.wb_obj); | |
438 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
439 | } | |
440 | amdgpu_bo_unref(&adev->wb.wb_obj); | |
441 | adev->wb.wb = NULL; | |
442 | adev->wb.wb_obj = NULL; | |
443 | } | |
444 | } | |
445 | ||
446 | /** | |
447 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
448 | * | |
449 | * @adev: amdgpu_device pointer | |
450 | * | |
451 | * Disables Writeback and frees the Writeback memory (all asics). | |
452 | * Used at driver startup. | |
453 | * Returns 0 on success or an -error on failure. | |
454 | */ | |
455 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
456 | { | |
457 | int r; | |
458 | ||
459 | if (adev->wb.wb_obj == NULL) { | |
460 | r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, | |
72d7668b CK |
461 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
462 | &adev->wb.wb_obj); | |
d38ceaf9 AD |
463 | if (r) { |
464 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
465 | return r; | |
466 | } | |
467 | r = amdgpu_bo_reserve(adev->wb.wb_obj, false); | |
468 | if (unlikely(r != 0)) { | |
469 | amdgpu_wb_fini(adev); | |
470 | return r; | |
471 | } | |
472 | r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, | |
473 | &adev->wb.gpu_addr); | |
474 | if (r) { | |
475 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
476 | dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); | |
477 | amdgpu_wb_fini(adev); | |
478 | return r; | |
479 | } | |
480 | r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); | |
481 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
482 | if (r) { | |
483 | dev_warn(adev->dev, "(%d) map WB bo failed\n", r); | |
484 | amdgpu_wb_fini(adev); | |
485 | return r; | |
486 | } | |
487 | ||
488 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
489 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
490 | ||
491 | /* clear wb memory */ | |
492 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
493 | } | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | /** | |
499 | * amdgpu_wb_get - Allocate a wb entry | |
500 | * | |
501 | * @adev: amdgpu_device pointer | |
502 | * @wb: wb index | |
503 | * | |
504 | * Allocate a wb slot for use by the driver (all asics). | |
505 | * Returns 0 on success or -EINVAL on failure. | |
506 | */ | |
507 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
508 | { | |
509 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
510 | if (offset < adev->wb.num_wb) { | |
511 | __set_bit(offset, adev->wb.used); | |
512 | *wb = offset; | |
513 | return 0; | |
514 | } else { | |
515 | return -EINVAL; | |
516 | } | |
517 | } | |
518 | ||
519 | /** | |
520 | * amdgpu_wb_free - Free a wb entry | |
521 | * | |
522 | * @adev: amdgpu_device pointer | |
523 | * @wb: wb index | |
524 | * | |
525 | * Free a wb slot allocated for use by the driver (all asics) | |
526 | */ | |
527 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
528 | { | |
529 | if (wb < adev->wb.num_wb) | |
530 | __clear_bit(wb, adev->wb.used); | |
531 | } | |
532 | ||
533 | /** | |
534 | * amdgpu_vram_location - try to find VRAM location | |
535 | * @adev: amdgpu device structure holding all necessary informations | |
536 | * @mc: memory controller structure holding memory informations | |
537 | * @base: base address at which to put VRAM | |
538 | * | |
539 | * Function will place try to place VRAM at base address provided | |
540 | * as parameter (which is so far either PCI aperture address or | |
541 | * for IGP TOM base address). | |
542 | * | |
543 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
544 | * address space then we limit the VRAM size to the aperture. | |
545 | * | |
546 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
547 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
548 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
549 | * not IGP. | |
550 | * | |
551 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
552 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
553 | * Novell bug 204882 + along with lots of ubuntu ones | |
554 | * | |
555 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
556 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
557 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
558 | * ones) | |
559 | * | |
560 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
561 | * explicitly check for that thought. | |
562 | * | |
563 | * FIXME: when reducing VRAM size align new size on power of 2. | |
564 | */ | |
565 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
566 | { | |
567 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
568 | ||
569 | mc->vram_start = base; | |
570 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
571 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
572 | mc->real_vram_size = mc->aper_size; | |
573 | mc->mc_vram_size = mc->aper_size; | |
574 | } | |
575 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
576 | if (limit && limit < mc->real_vram_size) | |
577 | mc->real_vram_size = limit; | |
578 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
579 | mc->mc_vram_size >> 20, mc->vram_start, | |
580 | mc->vram_end, mc->real_vram_size >> 20); | |
581 | } | |
582 | ||
583 | /** | |
584 | * amdgpu_gtt_location - try to find GTT location | |
585 | * @adev: amdgpu device structure holding all necessary informations | |
586 | * @mc: memory controller structure holding memory informations | |
587 | * | |
588 | * Function will place try to place GTT before or after VRAM. | |
589 | * | |
590 | * If GTT size is bigger than space left then we ajust GTT size. | |
591 | * Thus function will never fails. | |
592 | * | |
593 | * FIXME: when reducing GTT size align new size on power of 2. | |
594 | */ | |
595 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
596 | { | |
597 | u64 size_af, size_bf; | |
598 | ||
599 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
600 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
601 | if (size_bf > size_af) { | |
602 | if (mc->gtt_size > size_bf) { | |
603 | dev_warn(adev->dev, "limiting GTT\n"); | |
604 | mc->gtt_size = size_bf; | |
605 | } | |
606 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
607 | } else { | |
608 | if (mc->gtt_size > size_af) { | |
609 | dev_warn(adev->dev, "limiting GTT\n"); | |
610 | mc->gtt_size = size_af; | |
611 | } | |
612 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
613 | } | |
614 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
615 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
616 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
617 | } | |
618 | ||
619 | /* | |
620 | * GPU helpers function. | |
621 | */ | |
622 | /** | |
623 | * amdgpu_card_posted - check if the hw has already been initialized | |
624 | * | |
625 | * @adev: amdgpu_device pointer | |
626 | * | |
627 | * Check if the asic has been initialized (all asics). | |
628 | * Used at driver startup. | |
629 | * Returns true if initialized or false if not. | |
630 | */ | |
631 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
632 | { | |
633 | uint32_t reg; | |
634 | ||
635 | /* then check MEM_SIZE, in case the crtcs are off */ | |
636 | reg = RREG32(mmCONFIG_MEMSIZE); | |
637 | ||
638 | if (reg) | |
639 | return true; | |
640 | ||
641 | return false; | |
642 | ||
643 | } | |
644 | ||
d38ceaf9 AD |
645 | /** |
646 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
647 | * | |
648 | * @adev: amdgpu_device pointer | |
649 | * | |
650 | * Allocate the dummy page used by the driver (all asics). | |
651 | * This dummy page is used by the driver as a filler for gart entries | |
652 | * when pages are taken out of the GART | |
653 | * Returns 0 on sucess, -ENOMEM on failure. | |
654 | */ | |
655 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
656 | { | |
657 | if (adev->dummy_page.page) | |
658 | return 0; | |
659 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
660 | if (adev->dummy_page.page == NULL) | |
661 | return -ENOMEM; | |
662 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
663 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
664 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
665 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
666 | __free_page(adev->dummy_page.page); | |
667 | adev->dummy_page.page = NULL; | |
668 | return -ENOMEM; | |
669 | } | |
670 | return 0; | |
671 | } | |
672 | ||
673 | /** | |
674 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
675 | * | |
676 | * @adev: amdgpu_device pointer | |
677 | * | |
678 | * Frees the dummy page used by the driver (all asics). | |
679 | */ | |
680 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
681 | { | |
682 | if (adev->dummy_page.page == NULL) | |
683 | return; | |
684 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
685 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
686 | __free_page(adev->dummy_page.page); | |
687 | adev->dummy_page.page = NULL; | |
688 | } | |
689 | ||
690 | ||
691 | /* ATOM accessor methods */ | |
692 | /* | |
693 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
694 | * driver registers callbacks to access registers and the interpreter | |
695 | * in the driver parses the tables and executes then to program specific | |
696 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
697 | * atombios.h, and atom.c | |
698 | */ | |
699 | ||
700 | /** | |
701 | * cail_pll_read - read PLL register | |
702 | * | |
703 | * @info: atom card_info pointer | |
704 | * @reg: PLL register offset | |
705 | * | |
706 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
707 | * Returns the value of the PLL register. | |
708 | */ | |
709 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
710 | { | |
711 | return 0; | |
712 | } | |
713 | ||
714 | /** | |
715 | * cail_pll_write - write PLL register | |
716 | * | |
717 | * @info: atom card_info pointer | |
718 | * @reg: PLL register offset | |
719 | * @val: value to write to the pll register | |
720 | * | |
721 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
722 | */ | |
723 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
724 | { | |
725 | ||
726 | } | |
727 | ||
728 | /** | |
729 | * cail_mc_read - read MC (Memory Controller) register | |
730 | * | |
731 | * @info: atom card_info pointer | |
732 | * @reg: MC register offset | |
733 | * | |
734 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
735 | * Returns the value of the MC register. | |
736 | */ | |
737 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
738 | { | |
739 | return 0; | |
740 | } | |
741 | ||
742 | /** | |
743 | * cail_mc_write - write MC (Memory Controller) register | |
744 | * | |
745 | * @info: atom card_info pointer | |
746 | * @reg: MC register offset | |
747 | * @val: value to write to the pll register | |
748 | * | |
749 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
750 | */ | |
751 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
752 | { | |
753 | ||
754 | } | |
755 | ||
756 | /** | |
757 | * cail_reg_write - write MMIO register | |
758 | * | |
759 | * @info: atom card_info pointer | |
760 | * @reg: MMIO register offset | |
761 | * @val: value to write to the pll register | |
762 | * | |
763 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
764 | */ | |
765 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
766 | { | |
767 | struct amdgpu_device *adev = info->dev->dev_private; | |
768 | ||
769 | WREG32(reg, val); | |
770 | } | |
771 | ||
772 | /** | |
773 | * cail_reg_read - read MMIO register | |
774 | * | |
775 | * @info: atom card_info pointer | |
776 | * @reg: MMIO register offset | |
777 | * | |
778 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
779 | * Returns the value of the MMIO register. | |
780 | */ | |
781 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
782 | { | |
783 | struct amdgpu_device *adev = info->dev->dev_private; | |
784 | uint32_t r; | |
785 | ||
786 | r = RREG32(reg); | |
787 | return r; | |
788 | } | |
789 | ||
790 | /** | |
791 | * cail_ioreg_write - write IO register | |
792 | * | |
793 | * @info: atom card_info pointer | |
794 | * @reg: IO register offset | |
795 | * @val: value to write to the pll register | |
796 | * | |
797 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
798 | */ | |
799 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
800 | { | |
801 | struct amdgpu_device *adev = info->dev->dev_private; | |
802 | ||
803 | WREG32_IO(reg, val); | |
804 | } | |
805 | ||
806 | /** | |
807 | * cail_ioreg_read - read IO register | |
808 | * | |
809 | * @info: atom card_info pointer | |
810 | * @reg: IO register offset | |
811 | * | |
812 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
813 | * Returns the value of the IO register. | |
814 | */ | |
815 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
816 | { | |
817 | struct amdgpu_device *adev = info->dev->dev_private; | |
818 | uint32_t r; | |
819 | ||
820 | r = RREG32_IO(reg); | |
821 | return r; | |
822 | } | |
823 | ||
824 | /** | |
825 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
826 | * | |
827 | * @adev: amdgpu_device pointer | |
828 | * | |
829 | * Frees the driver info and register access callbacks for the ATOM | |
830 | * interpreter (r4xx+). | |
831 | * Called at driver shutdown. | |
832 | */ | |
833 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
834 | { | |
89e0ec9f | 835 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 836 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
837 | kfree(adev->mode_info.atom_context->iio); |
838 | } | |
d38ceaf9 AD |
839 | kfree(adev->mode_info.atom_context); |
840 | adev->mode_info.atom_context = NULL; | |
841 | kfree(adev->mode_info.atom_card_info); | |
842 | adev->mode_info.atom_card_info = NULL; | |
843 | } | |
844 | ||
845 | /** | |
846 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
847 | * | |
848 | * @adev: amdgpu_device pointer | |
849 | * | |
850 | * Initializes the driver info and register access callbacks for the | |
851 | * ATOM interpreter (r4xx+). | |
852 | * Returns 0 on sucess, -ENOMEM on failure. | |
853 | * Called at driver startup. | |
854 | */ | |
855 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
856 | { | |
857 | struct card_info *atom_card_info = | |
858 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
859 | ||
860 | if (!atom_card_info) | |
861 | return -ENOMEM; | |
862 | ||
863 | adev->mode_info.atom_card_info = atom_card_info; | |
864 | atom_card_info->dev = adev->ddev; | |
865 | atom_card_info->reg_read = cail_reg_read; | |
866 | atom_card_info->reg_write = cail_reg_write; | |
867 | /* needed for iio ops */ | |
868 | if (adev->rio_mem) { | |
869 | atom_card_info->ioreg_read = cail_ioreg_read; | |
870 | atom_card_info->ioreg_write = cail_ioreg_write; | |
871 | } else { | |
872 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
873 | atom_card_info->ioreg_read = cail_reg_read; | |
874 | atom_card_info->ioreg_write = cail_reg_write; | |
875 | } | |
876 | atom_card_info->mc_read = cail_mc_read; | |
877 | atom_card_info->mc_write = cail_mc_write; | |
878 | atom_card_info->pll_read = cail_pll_read; | |
879 | atom_card_info->pll_write = cail_pll_write; | |
880 | ||
881 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
882 | if (!adev->mode_info.atom_context) { | |
883 | amdgpu_atombios_fini(adev); | |
884 | return -ENOMEM; | |
885 | } | |
886 | ||
887 | mutex_init(&adev->mode_info.atom_context->mutex); | |
888 | amdgpu_atombios_scratch_regs_init(adev); | |
889 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
890 | return 0; | |
891 | } | |
892 | ||
893 | /* if we get transitioned to only one device, take VGA back */ | |
894 | /** | |
895 | * amdgpu_vga_set_decode - enable/disable vga decode | |
896 | * | |
897 | * @cookie: amdgpu_device pointer | |
898 | * @state: enable/disable vga decode | |
899 | * | |
900 | * Enable/disable vga decode (all asics). | |
901 | * Returns VGA resource flags. | |
902 | */ | |
903 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
904 | { | |
905 | struct amdgpu_device *adev = cookie; | |
906 | amdgpu_asic_set_vga_state(adev, state); | |
907 | if (state) | |
908 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
909 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
910 | else | |
911 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
912 | } | |
913 | ||
914 | /** | |
915 | * amdgpu_check_pot_argument - check that argument is a power of two | |
916 | * | |
917 | * @arg: value to check | |
918 | * | |
919 | * Validates that a certain argument is a power of two (all asics). | |
920 | * Returns true if argument is valid. | |
921 | */ | |
922 | static bool amdgpu_check_pot_argument(int arg) | |
923 | { | |
924 | return (arg & (arg - 1)) == 0; | |
925 | } | |
926 | ||
927 | /** | |
928 | * amdgpu_check_arguments - validate module params | |
929 | * | |
930 | * @adev: amdgpu_device pointer | |
931 | * | |
932 | * Validates certain module parameters and updates | |
933 | * the associated values used by the driver (all asics). | |
934 | */ | |
935 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
936 | { | |
5b011235 CZ |
937 | if (amdgpu_sched_jobs < 4) { |
938 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
939 | amdgpu_sched_jobs); | |
940 | amdgpu_sched_jobs = 4; | |
941 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
942 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
943 | amdgpu_sched_jobs); | |
944 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
945 | } | |
d38ceaf9 AD |
946 | |
947 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 948 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
949 | if (amdgpu_gart_size < 32) { |
950 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
951 | amdgpu_gart_size); | |
952 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
953 | } |
954 | } | |
955 | ||
956 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
957 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
958 | amdgpu_vm_size); | |
8dacc127 | 959 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
960 | } |
961 | ||
962 | if (amdgpu_vm_size < 1) { | |
963 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
964 | amdgpu_vm_size); | |
8dacc127 | 965 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
966 | } |
967 | ||
968 | /* | |
969 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
970 | */ | |
971 | if (amdgpu_vm_size > 1024) { | |
972 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
973 | amdgpu_vm_size); | |
8dacc127 | 974 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
975 | } |
976 | ||
977 | /* defines number of bits in page table versus page directory, | |
978 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
979 | * page table and the remaining bits are in the page directory */ | |
980 | if (amdgpu_vm_block_size == -1) { | |
981 | ||
982 | /* Total bits covered by PD + PTs */ | |
983 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
984 | ||
985 | /* Make sure the PD is 4K in size up to 8GB address space. | |
986 | Above that split equal between PD and PTs */ | |
987 | if (amdgpu_vm_size <= 8) | |
988 | amdgpu_vm_block_size = bits - 9; | |
989 | else | |
990 | amdgpu_vm_block_size = (bits + 3) / 2; | |
991 | ||
992 | } else if (amdgpu_vm_block_size < 9) { | |
993 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
994 | amdgpu_vm_block_size); | |
995 | amdgpu_vm_block_size = 9; | |
996 | } | |
997 | ||
998 | if (amdgpu_vm_block_size > 24 || | |
999 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1000 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1001 | amdgpu_vm_block_size); | |
1002 | amdgpu_vm_block_size = 9; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | /** | |
1007 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1008 | * | |
1009 | * @pdev: pci dev pointer | |
1694467b | 1010 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1011 | * |
1012 | * Callback for the switcheroo driver. Suspends or resumes the | |
1013 | * the asics before or after it is powered up using ACPI methods. | |
1014 | */ | |
1015 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1016 | { | |
1017 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1018 | ||
1019 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1020 | return; | |
1021 | ||
1022 | if (state == VGA_SWITCHEROO_ON) { | |
1023 | unsigned d3_delay = dev->pdev->d3_delay; | |
1024 | ||
1025 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1026 | /* don't suspend or resume card normally */ | |
1027 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1028 | ||
1029 | amdgpu_resume_kms(dev, true, true); | |
1030 | ||
1031 | dev->pdev->d3_delay = d3_delay; | |
1032 | ||
1033 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1034 | drm_kms_helper_poll_enable(dev); | |
1035 | } else { | |
1036 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1037 | drm_kms_helper_poll_disable(dev); | |
1038 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1039 | amdgpu_suspend_kms(dev, true, true); | |
1040 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /** | |
1045 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1046 | * | |
1047 | * @pdev: pci dev pointer | |
1048 | * | |
1049 | * Callback for the switcheroo driver. Check of the switcheroo | |
1050 | * state can be changed. | |
1051 | * Returns true if the state can be changed, false if not. | |
1052 | */ | |
1053 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1054 | { | |
1055 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1056 | ||
1057 | /* | |
1058 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1059 | * locking inversion with the driver load path. And the access here is | |
1060 | * completely racy anyway. So don't bother with locking for now. | |
1061 | */ | |
1062 | return dev->open_count == 0; | |
1063 | } | |
1064 | ||
1065 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1066 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1067 | .reprobe = NULL, | |
1068 | .can_switch = amdgpu_switcheroo_can_switch, | |
1069 | }; | |
1070 | ||
1071 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1072 | enum amd_ip_block_type block_type, |
1073 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1074 | { |
1075 | int i, r = 0; | |
1076 | ||
1077 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1078 | if (!adev->ip_block_status[i].valid) |
1079 | continue; | |
d38ceaf9 | 1080 | if (adev->ip_blocks[i].type == block_type) { |
5fc3aeeb | 1081 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
d38ceaf9 AD |
1082 | state); |
1083 | if (r) | |
1084 | return r; | |
a225bf1c | 1085 | break; |
d38ceaf9 AD |
1086 | } |
1087 | } | |
1088 | return r; | |
1089 | } | |
1090 | ||
1091 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1092 | enum amd_ip_block_type block_type, |
1093 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1094 | { |
1095 | int i, r = 0; | |
1096 | ||
1097 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1098 | if (!adev->ip_block_status[i].valid) |
1099 | continue; | |
d38ceaf9 | 1100 | if (adev->ip_blocks[i].type == block_type) { |
5fc3aeeb | 1101 | r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, |
d38ceaf9 AD |
1102 | state); |
1103 | if (r) | |
1104 | return r; | |
a225bf1c | 1105 | break; |
d38ceaf9 AD |
1106 | } |
1107 | } | |
1108 | return r; | |
1109 | } | |
1110 | ||
5dbbb60b AD |
1111 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1112 | enum amd_ip_block_type block_type) | |
1113 | { | |
1114 | int i, r; | |
1115 | ||
1116 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1117 | if (!adev->ip_block_status[i].valid) |
1118 | continue; | |
5dbbb60b AD |
1119 | if (adev->ip_blocks[i].type == block_type) { |
1120 | r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev); | |
1121 | if (r) | |
1122 | return r; | |
1123 | break; | |
1124 | } | |
1125 | } | |
1126 | return 0; | |
1127 | ||
1128 | } | |
1129 | ||
1130 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1131 | enum amd_ip_block_type block_type) | |
1132 | { | |
1133 | int i; | |
1134 | ||
1135 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
9ecbe7f5 AD |
1136 | if (!adev->ip_block_status[i].valid) |
1137 | continue; | |
5dbbb60b AD |
1138 | if (adev->ip_blocks[i].type == block_type) |
1139 | return adev->ip_blocks[i].funcs->is_idle((void *)adev); | |
1140 | } | |
1141 | return true; | |
1142 | ||
1143 | } | |
1144 | ||
d38ceaf9 AD |
1145 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( |
1146 | struct amdgpu_device *adev, | |
5fc3aeeb | 1147 | enum amd_ip_block_type type) |
d38ceaf9 AD |
1148 | { |
1149 | int i; | |
1150 | ||
1151 | for (i = 0; i < adev->num_ip_blocks; i++) | |
1152 | if (adev->ip_blocks[i].type == type) | |
1153 | return &adev->ip_blocks[i]; | |
1154 | ||
1155 | return NULL; | |
1156 | } | |
1157 | ||
1158 | /** | |
1159 | * amdgpu_ip_block_version_cmp | |
1160 | * | |
1161 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1162 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1163 | * @major: major version |
1164 | * @minor: minor version | |
1165 | * | |
1166 | * return 0 if equal or greater | |
1167 | * return 1 if smaller or the ip_block doesn't exist | |
1168 | */ | |
1169 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1170 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1171 | u32 major, u32 minor) |
1172 | { | |
1173 | const struct amdgpu_ip_block_version *ip_block; | |
1174 | ip_block = amdgpu_get_ip_block(adev, type); | |
1175 | ||
1176 | if (ip_block && ((ip_block->major > major) || | |
1177 | ((ip_block->major == major) && | |
1178 | (ip_block->minor >= minor)))) | |
1179 | return 0; | |
1180 | ||
1181 | return 1; | |
1182 | } | |
1183 | ||
1184 | static int amdgpu_early_init(struct amdgpu_device *adev) | |
1185 | { | |
aaa36a97 | 1186 | int i, r; |
d38ceaf9 AD |
1187 | |
1188 | switch (adev->asic_type) { | |
aaa36a97 AD |
1189 | case CHIP_TOPAZ: |
1190 | case CHIP_TONGA: | |
48299f95 | 1191 | case CHIP_FIJI: |
2cc0c0b5 FC |
1192 | case CHIP_POLARIS11: |
1193 | case CHIP_POLARIS10: | |
aaa36a97 | 1194 | case CHIP_CARRIZO: |
39bb0c92 SL |
1195 | case CHIP_STONEY: |
1196 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1197 | adev->family = AMDGPU_FAMILY_CZ; |
1198 | else | |
1199 | adev->family = AMDGPU_FAMILY_VI; | |
1200 | ||
1201 | r = vi_set_ip_blocks(adev); | |
1202 | if (r) | |
1203 | return r; | |
1204 | break; | |
a2e73f56 AD |
1205 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1206 | case CHIP_BONAIRE: | |
1207 | case CHIP_HAWAII: | |
1208 | case CHIP_KAVERI: | |
1209 | case CHIP_KABINI: | |
1210 | case CHIP_MULLINS: | |
1211 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1212 | adev->family = AMDGPU_FAMILY_CI; | |
1213 | else | |
1214 | adev->family = AMDGPU_FAMILY_KV; | |
1215 | ||
1216 | r = cik_set_ip_blocks(adev); | |
1217 | if (r) | |
1218 | return r; | |
1219 | break; | |
1220 | #endif | |
d38ceaf9 AD |
1221 | default: |
1222 | /* FIXME: not supported yet */ | |
1223 | return -EINVAL; | |
1224 | } | |
1225 | ||
8faf0e08 AD |
1226 | adev->ip_block_status = kcalloc(adev->num_ip_blocks, |
1227 | sizeof(struct amdgpu_ip_block_status), GFP_KERNEL); | |
1228 | if (adev->ip_block_status == NULL) | |
d8d090b7 | 1229 | return -ENOMEM; |
d38ceaf9 AD |
1230 | |
1231 | if (adev->ip_blocks == NULL) { | |
1232 | DRM_ERROR("No IP blocks found!\n"); | |
1233 | return r; | |
1234 | } | |
1235 | ||
1236 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1237 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1238 | DRM_ERROR("disabled ip block: %d\n", i); | |
8faf0e08 | 1239 | adev->ip_block_status[i].valid = false; |
d38ceaf9 AD |
1240 | } else { |
1241 | if (adev->ip_blocks[i].funcs->early_init) { | |
5fc3aeeb | 1242 | r = adev->ip_blocks[i].funcs->early_init((void *)adev); |
2c1a2784 | 1243 | if (r == -ENOENT) { |
8faf0e08 | 1244 | adev->ip_block_status[i].valid = false; |
2c1a2784 | 1245 | } else if (r) { |
88a907d6 | 1246 | DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1247 | return r; |
2c1a2784 | 1248 | } else { |
8faf0e08 | 1249 | adev->ip_block_status[i].valid = true; |
2c1a2784 | 1250 | } |
974e6b64 | 1251 | } else { |
8faf0e08 | 1252 | adev->ip_block_status[i].valid = true; |
d38ceaf9 | 1253 | } |
d38ceaf9 AD |
1254 | } |
1255 | } | |
1256 | ||
395d1fb9 NH |
1257 | adev->cg_flags &= amdgpu_cg_mask; |
1258 | adev->pg_flags &= amdgpu_pg_mask; | |
1259 | ||
d38ceaf9 AD |
1260 | return 0; |
1261 | } | |
1262 | ||
1263 | static int amdgpu_init(struct amdgpu_device *adev) | |
1264 | { | |
1265 | int i, r; | |
1266 | ||
1267 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1268 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 | 1269 | continue; |
5fc3aeeb | 1270 | r = adev->ip_blocks[i].funcs->sw_init((void *)adev); |
2c1a2784 | 1271 | if (r) { |
822b2cef | 1272 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1273 | return r; |
2c1a2784 | 1274 | } |
8faf0e08 | 1275 | adev->ip_block_status[i].sw = true; |
d38ceaf9 | 1276 | /* need to do gmc hw init early so we can allocate gpu mem */ |
5fc3aeeb | 1277 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1278 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1279 | if (r) { |
1280 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1281 | return r; |
2c1a2784 | 1282 | } |
5fc3aeeb | 1283 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 AD |
1284 | if (r) { |
1285 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1286 | return r; |
2c1a2784 | 1287 | } |
d38ceaf9 | 1288 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1289 | if (r) { |
1290 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1291 | return r; |
2c1a2784 | 1292 | } |
8faf0e08 | 1293 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1294 | } |
1295 | } | |
1296 | ||
1297 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1298 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 AD |
1299 | continue; |
1300 | /* gmc hw init is done early */ | |
5fc3aeeb | 1301 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1302 | continue; |
5fc3aeeb | 1303 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 | 1304 | if (r) { |
822b2cef | 1305 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1306 | return r; |
2c1a2784 | 1307 | } |
8faf0e08 | 1308 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1309 | } |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1315 | { | |
1316 | int i = 0, r; | |
1317 | ||
1318 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1319 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1320 | continue; |
1321 | /* enable clockgating to save power */ | |
5fc3aeeb | 1322 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
1323 | AMD_CG_STATE_GATE); | |
2c1a2784 | 1324 | if (r) { |
822b2cef | 1325 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1326 | return r; |
2c1a2784 | 1327 | } |
d38ceaf9 | 1328 | if (adev->ip_blocks[i].funcs->late_init) { |
5fc3aeeb | 1329 | r = adev->ip_blocks[i].funcs->late_init((void *)adev); |
2c1a2784 | 1330 | if (r) { |
822b2cef | 1331 | DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1332 | return r; |
2c1a2784 | 1333 | } |
d38ceaf9 AD |
1334 | } |
1335 | } | |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
1340 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1341 | { | |
1342 | int i, r; | |
1343 | ||
1344 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
8faf0e08 | 1345 | if (!adev->ip_block_status[i].hw) |
d38ceaf9 | 1346 | continue; |
5fc3aeeb | 1347 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1348 | amdgpu_wb_fini(adev); |
1349 | amdgpu_vram_scratch_fini(adev); | |
1350 | } | |
1351 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
5fc3aeeb | 1352 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
1353 | AMD_CG_STATE_UNGATE); | |
2c1a2784 | 1354 | if (r) { |
822b2cef | 1355 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1356 | return r; |
2c1a2784 | 1357 | } |
5fc3aeeb | 1358 | r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); |
d38ceaf9 | 1359 | /* XXX handle errors */ |
2c1a2784 | 1360 | if (r) { |
822b2cef | 1361 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1362 | } |
8faf0e08 | 1363 | adev->ip_block_status[i].hw = false; |
d38ceaf9 AD |
1364 | } |
1365 | ||
1366 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
8faf0e08 | 1367 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 | 1368 | continue; |
5fc3aeeb | 1369 | r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); |
d38ceaf9 | 1370 | /* XXX handle errors */ |
2c1a2784 | 1371 | if (r) { |
822b2cef | 1372 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1373 | } |
8faf0e08 AD |
1374 | adev->ip_block_status[i].sw = false; |
1375 | adev->ip_block_status[i].valid = false; | |
d38ceaf9 AD |
1376 | } |
1377 | ||
a6dcfd9c ML |
1378 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
1379 | if (adev->ip_blocks[i].funcs->late_fini) | |
1380 | adev->ip_blocks[i].funcs->late_fini((void *)adev); | |
1381 | } | |
1382 | ||
d38ceaf9 AD |
1383 | return 0; |
1384 | } | |
1385 | ||
1386 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1387 | { | |
1388 | int i, r; | |
1389 | ||
c5a93a28 FC |
1390 | /* ungate SMC block first */ |
1391 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1392 | AMD_CG_STATE_UNGATE); | |
1393 | if (r) { | |
1394 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1395 | } | |
1396 | ||
d38ceaf9 | 1397 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
8faf0e08 | 1398 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1399 | continue; |
1400 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 FC |
1401 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
1402 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, | |
1403 | AMD_CG_STATE_UNGATE); | |
1404 | if (r) { | |
822b2cef | 1405 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
c5a93a28 | 1406 | } |
2c1a2784 | 1407 | } |
d38ceaf9 AD |
1408 | /* XXX handle errors */ |
1409 | r = adev->ip_blocks[i].funcs->suspend(adev); | |
1410 | /* XXX handle errors */ | |
2c1a2784 | 1411 | if (r) { |
822b2cef | 1412 | DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1413 | } |
d38ceaf9 AD |
1414 | } |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1420 | { | |
1421 | int i, r; | |
1422 | ||
1423 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1424 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1425 | continue; |
1426 | r = adev->ip_blocks[i].funcs->resume(adev); | |
2c1a2784 | 1427 | if (r) { |
822b2cef | 1428 | DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1429 | return r; |
2c1a2784 | 1430 | } |
d38ceaf9 AD |
1431 | } |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
048765ad AR |
1436 | static bool amdgpu_device_is_virtual(void) |
1437 | { | |
1438 | #ifdef CONFIG_X86 | |
1439 | return boot_cpu_has(X86_FEATURE_HYPERVISOR); | |
1440 | #else | |
1441 | return false; | |
1442 | #endif | |
1443 | } | |
1444 | ||
d38ceaf9 AD |
1445 | /** |
1446 | * amdgpu_device_init - initialize the driver | |
1447 | * | |
1448 | * @adev: amdgpu_device pointer | |
1449 | * @pdev: drm dev pointer | |
1450 | * @pdev: pci dev pointer | |
1451 | * @flags: driver flags | |
1452 | * | |
1453 | * Initializes the driver info and hw (all asics). | |
1454 | * Returns 0 for success or an error on failure. | |
1455 | * Called at driver startup. | |
1456 | */ | |
1457 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1458 | struct drm_device *ddev, | |
1459 | struct pci_dev *pdev, | |
1460 | uint32_t flags) | |
1461 | { | |
1462 | int r, i; | |
1463 | bool runtime = false; | |
1464 | ||
1465 | adev->shutdown = false; | |
1466 | adev->dev = &pdev->dev; | |
1467 | adev->ddev = ddev; | |
1468 | adev->pdev = pdev; | |
1469 | adev->flags = flags; | |
2f7d10b3 | 1470 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1471 | adev->is_atom_bios = false; |
1472 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1473 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1474 | adev->accel_working = false; | |
1475 | adev->num_rings = 0; | |
1476 | adev->mman.buffer_funcs = NULL; | |
1477 | adev->mman.buffer_funcs_ring = NULL; | |
1478 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1479 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 AD |
1480 | adev->gart.gart_funcs = NULL; |
1481 | adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); | |
1482 | ||
1483 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1484 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1485 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1486 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
1487 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; | |
1488 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1489 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1490 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
1491 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; | |
1492 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1493 | ||
3e39ab90 AD |
1494 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1495 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1496 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1497 | |
1498 | /* mutex initialization are all done here so we | |
1499 | * can recall function without having locking issues */ | |
8d0a7cea | 1500 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1501 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1502 | mutex_init(&adev->pm.mutex); |
1503 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1504 | mutex_init(&adev->srbm_mutex); | |
1505 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1506 | mutex_init(&adev->mn_lock); |
1507 | hash_init(adev->mn_hash); | |
1508 | ||
1509 | amdgpu_check_arguments(adev); | |
1510 | ||
1511 | /* Registers mapping */ | |
1512 | /* TODO: block userspace mapping of io register */ | |
1513 | spin_lock_init(&adev->mmio_idx_lock); | |
1514 | spin_lock_init(&adev->smc_idx_lock); | |
1515 | spin_lock_init(&adev->pcie_idx_lock); | |
1516 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1517 | spin_lock_init(&adev->didt_idx_lock); | |
1518 | spin_lock_init(&adev->audio_endpt_idx_lock); | |
1519 | ||
1520 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1521 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1522 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); | |
1523 | if (adev->rmmio == NULL) { | |
1524 | return -ENOMEM; | |
1525 | } | |
1526 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1527 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1528 | ||
1529 | /* doorbell bar mapping */ | |
1530 | amdgpu_doorbell_init(adev); | |
1531 | ||
1532 | /* io port mapping */ | |
1533 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1534 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1535 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1536 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1537 | break; | |
1538 | } | |
1539 | } | |
1540 | if (adev->rio_mem == NULL) | |
1541 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1542 | ||
1543 | /* early init functions */ | |
1544 | r = amdgpu_early_init(adev); | |
1545 | if (r) | |
1546 | return r; | |
1547 | ||
1548 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1549 | /* this will fail for cards that aren't VGA class devices, just | |
1550 | * ignore it */ | |
1551 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1552 | ||
1553 | if (amdgpu_runtime_pm == 1) | |
1554 | runtime = true; | |
e9bef455 | 1555 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1556 | runtime = true; |
1557 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1558 | if (runtime) | |
1559 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1560 | ||
1561 | /* Read BIOS */ | |
83ba126a AD |
1562 | if (!amdgpu_get_bios(adev)) { |
1563 | r = -EINVAL; | |
1564 | goto failed; | |
1565 | } | |
d38ceaf9 AD |
1566 | /* Must be an ATOMBIOS */ |
1567 | if (!adev->is_atom_bios) { | |
1568 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
83ba126a AD |
1569 | r = -EINVAL; |
1570 | goto failed; | |
d38ceaf9 AD |
1571 | } |
1572 | r = amdgpu_atombios_init(adev); | |
2c1a2784 AD |
1573 | if (r) { |
1574 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1575 | goto failed; |
2c1a2784 | 1576 | } |
d38ceaf9 | 1577 | |
7e471e6f AD |
1578 | /* See if the asic supports SR-IOV */ |
1579 | adev->virtualization.supports_sr_iov = | |
1580 | amdgpu_atombios_has_gpu_virtualization_table(adev); | |
1581 | ||
048765ad AR |
1582 | /* Check if we are executing in a virtualized environment */ |
1583 | adev->virtualization.is_virtual = amdgpu_device_is_virtual(); | |
1584 | adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev); | |
1585 | ||
d38ceaf9 | 1586 | /* Post card if necessary */ |
048765ad AR |
1587 | if (!amdgpu_card_posted(adev) || |
1588 | (adev->virtualization.is_virtual && | |
48a70e1c | 1589 | !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) { |
d38ceaf9 AD |
1590 | if (!adev->bios) { |
1591 | dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); | |
83ba126a AD |
1592 | r = -EINVAL; |
1593 | goto failed; | |
d38ceaf9 AD |
1594 | } |
1595 | DRM_INFO("GPU not posted. posting now...\n"); | |
1596 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1597 | } | |
1598 | ||
1599 | /* Initialize clocks */ | |
1600 | r = amdgpu_atombios_get_clock_info(adev); | |
2c1a2784 AD |
1601 | if (r) { |
1602 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
83ba126a | 1603 | goto failed; |
2c1a2784 | 1604 | } |
d38ceaf9 AD |
1605 | /* init i2c buses */ |
1606 | amdgpu_atombios_i2c_init(adev); | |
1607 | ||
1608 | /* Fence driver */ | |
1609 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1610 | if (r) { |
1611 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1612 | goto failed; |
2c1a2784 | 1613 | } |
d38ceaf9 AD |
1614 | |
1615 | /* init the mode config */ | |
1616 | drm_mode_config_init(adev->ddev); | |
1617 | ||
1618 | r = amdgpu_init(adev); | |
1619 | if (r) { | |
2c1a2784 | 1620 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1621 | amdgpu_fini(adev); |
83ba126a | 1622 | goto failed; |
d38ceaf9 AD |
1623 | } |
1624 | ||
1625 | adev->accel_working = true; | |
1626 | ||
1627 | amdgpu_fbdev_init(adev); | |
1628 | ||
1629 | r = amdgpu_ib_pool_init(adev); | |
1630 | if (r) { | |
1631 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1632 | goto failed; |
d38ceaf9 AD |
1633 | } |
1634 | ||
1635 | r = amdgpu_ib_ring_tests(adev); | |
1636 | if (r) | |
1637 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1638 | ||
1639 | r = amdgpu_gem_debugfs_init(adev); | |
1640 | if (r) { | |
1641 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1642 | } | |
1643 | ||
1644 | r = amdgpu_debugfs_regs_init(adev); | |
1645 | if (r) { | |
1646 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1647 | } | |
1648 | ||
50ab2533 HR |
1649 | r = amdgpu_debugfs_firmware_init(adev); |
1650 | if (r) { | |
1651 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); | |
1652 | return r; | |
1653 | } | |
1654 | ||
d38ceaf9 AD |
1655 | if ((amdgpu_testing & 1)) { |
1656 | if (adev->accel_working) | |
1657 | amdgpu_test_moves(adev); | |
1658 | else | |
1659 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1660 | } | |
1661 | if ((amdgpu_testing & 2)) { | |
1662 | if (adev->accel_working) | |
1663 | amdgpu_test_syncing(adev); | |
1664 | else | |
1665 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1666 | } | |
1667 | if (amdgpu_benchmarking) { | |
1668 | if (adev->accel_working) | |
1669 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1670 | else | |
1671 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1672 | } | |
1673 | ||
1674 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1675 | * explicit gating rather than handling it automatically. | |
1676 | */ | |
1677 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
1678 | if (r) { |
1679 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 1680 | goto failed; |
2c1a2784 | 1681 | } |
d38ceaf9 AD |
1682 | |
1683 | return 0; | |
83ba126a AD |
1684 | |
1685 | failed: | |
1686 | if (runtime) | |
1687 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
1688 | return r; | |
d38ceaf9 AD |
1689 | } |
1690 | ||
1691 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1692 | ||
1693 | /** | |
1694 | * amdgpu_device_fini - tear down the driver | |
1695 | * | |
1696 | * @adev: amdgpu_device pointer | |
1697 | * | |
1698 | * Tear down the driver info (all asics). | |
1699 | * Called at driver shutdown. | |
1700 | */ | |
1701 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1702 | { | |
1703 | int r; | |
1704 | ||
1705 | DRM_INFO("amdgpu: finishing device.\n"); | |
1706 | adev->shutdown = true; | |
1707 | /* evict vram memory */ | |
1708 | amdgpu_bo_evict_vram(adev); | |
1709 | amdgpu_ib_pool_fini(adev); | |
1710 | amdgpu_fence_driver_fini(adev); | |
1711 | amdgpu_fbdev_fini(adev); | |
1712 | r = amdgpu_fini(adev); | |
8faf0e08 AD |
1713 | kfree(adev->ip_block_status); |
1714 | adev->ip_block_status = NULL; | |
d38ceaf9 AD |
1715 | adev->accel_working = false; |
1716 | /* free i2c buses */ | |
1717 | amdgpu_i2c_fini(adev); | |
1718 | amdgpu_atombios_fini(adev); | |
1719 | kfree(adev->bios); | |
1720 | adev->bios = NULL; | |
1721 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
1722 | if (adev->flags & AMD_IS_PX) |
1723 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
1724 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
1725 | if (adev->rio_mem) | |
1726 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1727 | adev->rio_mem = NULL; | |
1728 | iounmap(adev->rmmio); | |
1729 | adev->rmmio = NULL; | |
1730 | amdgpu_doorbell_fini(adev); | |
1731 | amdgpu_debugfs_regs_cleanup(adev); | |
1732 | amdgpu_debugfs_remove_files(adev); | |
1733 | } | |
1734 | ||
1735 | ||
1736 | /* | |
1737 | * Suspend & resume. | |
1738 | */ | |
1739 | /** | |
1740 | * amdgpu_suspend_kms - initiate device suspend | |
1741 | * | |
1742 | * @pdev: drm dev pointer | |
1743 | * @state: suspend state | |
1744 | * | |
1745 | * Puts the hw in the suspend state (all asics). | |
1746 | * Returns 0 for success or an error on failure. | |
1747 | * Called at driver suspend. | |
1748 | */ | |
1749 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) | |
1750 | { | |
1751 | struct amdgpu_device *adev; | |
1752 | struct drm_crtc *crtc; | |
1753 | struct drm_connector *connector; | |
5ceb54c6 | 1754 | int r; |
d38ceaf9 AD |
1755 | |
1756 | if (dev == NULL || dev->dev_private == NULL) { | |
1757 | return -ENODEV; | |
1758 | } | |
1759 | ||
1760 | adev = dev->dev_private; | |
1761 | ||
1762 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1763 | return 0; | |
1764 | ||
1765 | drm_kms_helper_poll_disable(dev); | |
1766 | ||
1767 | /* turn off display hw */ | |
4c7fbc39 | 1768 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1769 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1770 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1771 | } | |
4c7fbc39 | 1772 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 1773 | |
756e6880 | 1774 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 1775 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 1776 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
1777 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
1778 | struct amdgpu_bo *robj; | |
1779 | ||
756e6880 AD |
1780 | if (amdgpu_crtc->cursor_bo) { |
1781 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1782 | r = amdgpu_bo_reserve(aobj, false); | |
1783 | if (r == 0) { | |
1784 | amdgpu_bo_unpin(aobj); | |
1785 | amdgpu_bo_unreserve(aobj); | |
1786 | } | |
1787 | } | |
1788 | ||
d38ceaf9 AD |
1789 | if (rfb == NULL || rfb->obj == NULL) { |
1790 | continue; | |
1791 | } | |
1792 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1793 | /* don't unpin kernel fb objects */ | |
1794 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1795 | r = amdgpu_bo_reserve(robj, false); | |
1796 | if (r == 0) { | |
1797 | amdgpu_bo_unpin(robj); | |
1798 | amdgpu_bo_unreserve(robj); | |
1799 | } | |
1800 | } | |
1801 | } | |
1802 | /* evict vram memory */ | |
1803 | amdgpu_bo_evict_vram(adev); | |
1804 | ||
5ceb54c6 | 1805 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
1806 | |
1807 | r = amdgpu_suspend(adev); | |
1808 | ||
1809 | /* evict remaining vram memory */ | |
1810 | amdgpu_bo_evict_vram(adev); | |
1811 | ||
1812 | pci_save_state(dev->pdev); | |
1813 | if (suspend) { | |
1814 | /* Shut down the device */ | |
1815 | pci_disable_device(dev->pdev); | |
1816 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
1817 | } | |
1818 | ||
1819 | if (fbcon) { | |
1820 | console_lock(); | |
1821 | amdgpu_fbdev_set_suspend(adev, 1); | |
1822 | console_unlock(); | |
1823 | } | |
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | /** | |
1828 | * amdgpu_resume_kms - initiate device resume | |
1829 | * | |
1830 | * @pdev: drm dev pointer | |
1831 | * | |
1832 | * Bring the hw back to operating state (all asics). | |
1833 | * Returns 0 for success or an error on failure. | |
1834 | * Called at driver resume. | |
1835 | */ | |
1836 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) | |
1837 | { | |
1838 | struct drm_connector *connector; | |
1839 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 1840 | struct drm_crtc *crtc; |
d38ceaf9 AD |
1841 | int r; |
1842 | ||
1843 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1844 | return 0; | |
1845 | ||
1846 | if (fbcon) { | |
1847 | console_lock(); | |
1848 | } | |
1849 | if (resume) { | |
1850 | pci_set_power_state(dev->pdev, PCI_D0); | |
1851 | pci_restore_state(dev->pdev); | |
1852 | if (pci_enable_device(dev->pdev)) { | |
1853 | if (fbcon) | |
1854 | console_unlock(); | |
1855 | return -1; | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | /* post card */ | |
ca198528 FC |
1860 | if (!amdgpu_card_posted(adev)) |
1861 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
d38ceaf9 AD |
1862 | |
1863 | r = amdgpu_resume(adev); | |
ca198528 FC |
1864 | if (r) |
1865 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 1866 | |
5ceb54c6 AD |
1867 | amdgpu_fence_driver_resume(adev); |
1868 | ||
ca198528 FC |
1869 | if (resume) { |
1870 | r = amdgpu_ib_ring_tests(adev); | |
1871 | if (r) | |
1872 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1873 | } | |
d38ceaf9 AD |
1874 | |
1875 | r = amdgpu_late_init(adev); | |
1876 | if (r) | |
1877 | return r; | |
1878 | ||
756e6880 AD |
1879 | /* pin cursors */ |
1880 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1881 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
1882 | ||
1883 | if (amdgpu_crtc->cursor_bo) { | |
1884 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1885 | r = amdgpu_bo_reserve(aobj, false); | |
1886 | if (r == 0) { | |
1887 | r = amdgpu_bo_pin(aobj, | |
1888 | AMDGPU_GEM_DOMAIN_VRAM, | |
1889 | &amdgpu_crtc->cursor_addr); | |
1890 | if (r != 0) | |
1891 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
1892 | amdgpu_bo_unreserve(aobj); | |
1893 | } | |
1894 | } | |
1895 | } | |
1896 | ||
d38ceaf9 AD |
1897 | /* blat the mode back in */ |
1898 | if (fbcon) { | |
1899 | drm_helper_resume_force_mode(dev); | |
1900 | /* turn on display hw */ | |
4c7fbc39 | 1901 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1902 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1903 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
1904 | } | |
4c7fbc39 | 1905 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
1906 | } |
1907 | ||
1908 | drm_kms_helper_poll_enable(dev); | |
54fb2a5c | 1909 | drm_helper_hpd_irq_event(dev); |
d38ceaf9 AD |
1910 | |
1911 | if (fbcon) { | |
1912 | amdgpu_fbdev_set_suspend(adev, 0); | |
1913 | console_unlock(); | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | /** | |
1920 | * amdgpu_gpu_reset - reset the asic | |
1921 | * | |
1922 | * @adev: amdgpu device pointer | |
1923 | * | |
1924 | * Attempt the reset the GPU if it has hung (all asics). | |
1925 | * Returns 0 for success or an error on failure. | |
1926 | */ | |
1927 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
1928 | { | |
1929 | unsigned ring_sizes[AMDGPU_MAX_RINGS]; | |
1930 | uint32_t *ring_data[AMDGPU_MAX_RINGS]; | |
1931 | ||
1932 | bool saved = false; | |
1933 | ||
1934 | int i, r; | |
1935 | int resched; | |
1936 | ||
d94aed5a | 1937 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 1938 | |
a3c47d6b CZ |
1939 | /* block TTM */ |
1940 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
1941 | ||
0875dc9e CZ |
1942 | /* block scheduler */ |
1943 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1944 | struct amdgpu_ring *ring = adev->rings[i]; | |
1945 | ||
1946 | if (!ring) | |
1947 | continue; | |
1948 | kthread_park(ring->sched.thread); | |
1949 | } | |
2200edac CZ |
1950 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
1951 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 1952 | |
a0250d36 CZ |
1953 | /* save scratch */ |
1954 | amdgpu_atombios_scratch_regs_save(adev); | |
d38ceaf9 AD |
1955 | r = amdgpu_suspend(adev); |
1956 | ||
1957 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1958 | struct amdgpu_ring *ring = adev->rings[i]; | |
1959 | if (!ring) | |
1960 | continue; | |
1961 | ||
1962 | ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]); | |
1963 | if (ring_sizes[i]) { | |
1964 | saved = true; | |
1965 | dev_info(adev->dev, "Saved %d dwords of commands " | |
1966 | "on ring %d.\n", ring_sizes[i], i); | |
1967 | } | |
1968 | } | |
1969 | ||
1970 | retry: | |
f1aa7e08 CZ |
1971 | /* Disable fb access */ |
1972 | if (adev->mode_info.num_crtc) { | |
1973 | struct amdgpu_mode_mc_save save; | |
1974 | amdgpu_display_stop_mc_access(adev, &save); | |
1975 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
1976 | } | |
1977 | ||
d38ceaf9 | 1978 | r = amdgpu_asic_reset(adev); |
bfa99269 AD |
1979 | /* post card */ |
1980 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1981 | ||
d38ceaf9 AD |
1982 | if (!r) { |
1983 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
1984 | r = amdgpu_resume(adev); | |
1985 | } | |
a0250d36 CZ |
1986 | /* restore scratch */ |
1987 | amdgpu_atombios_scratch_regs_restore(adev); | |
d38ceaf9 AD |
1988 | if (!r) { |
1989 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1990 | struct amdgpu_ring *ring = adev->rings[i]; | |
1991 | if (!ring) | |
1992 | continue; | |
0875dc9e | 1993 | kthread_unpark(ring->sched.thread); |
d38ceaf9 AD |
1994 | amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]); |
1995 | ring_sizes[i] = 0; | |
1996 | ring_data[i] = NULL; | |
1997 | } | |
1998 | ||
1999 | r = amdgpu_ib_ring_tests(adev); | |
2000 | if (r) { | |
2001 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
2002 | if (saved) { | |
2003 | saved = false; | |
2004 | r = amdgpu_suspend(adev); | |
2005 | goto retry; | |
2006 | } | |
2007 | } | |
2008 | } else { | |
2200edac | 2009 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2010 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2011 | if (adev->rings[i]) { |
2012 | kthread_unpark(adev->rings[i]->sched.thread); | |
d38ceaf9 | 2013 | kfree(ring_data[i]); |
0875dc9e | 2014 | } |
d38ceaf9 AD |
2015 | } |
2016 | } | |
2017 | ||
2018 | drm_helper_resume_force_mode(adev->ddev); | |
2019 | ||
2020 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2021 | if (r) { | |
2022 | /* bad news, how to tell it to userspace ? */ | |
2023 | dev_info(adev->dev, "GPU reset failed\n"); | |
2024 | } | |
0eaeb070 | 2025 | amdgpu_irq_gpu_reset_resume_helper(adev); |
d38ceaf9 | 2026 | |
d38ceaf9 AD |
2027 | return r; |
2028 | } | |
2029 | ||
d0dd7f0c AD |
2030 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2031 | { | |
2032 | u32 mask; | |
2033 | int ret; | |
2034 | ||
cd474ba0 AD |
2035 | if (amdgpu_pcie_gen_cap) |
2036 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2037 | |
cd474ba0 AD |
2038 | if (amdgpu_pcie_lane_cap) |
2039 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2040 | |
cd474ba0 AD |
2041 | /* covers APUs as well */ |
2042 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2043 | if (adev->pm.pcie_gen_mask == 0) | |
2044 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2045 | if (adev->pm.pcie_mlw_mask == 0) | |
2046 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2047 | return; |
cd474ba0 | 2048 | } |
d0dd7f0c | 2049 | |
cd474ba0 AD |
2050 | if (adev->pm.pcie_gen_mask == 0) { |
2051 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2052 | if (!ret) { | |
2053 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2054 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2055 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2056 | ||
2057 | if (mask & DRM_PCIE_SPEED_25) | |
2058 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2059 | if (mask & DRM_PCIE_SPEED_50) | |
2060 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2061 | if (mask & DRM_PCIE_SPEED_80) | |
2062 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2063 | } else { | |
2064 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2065 | } | |
2066 | } | |
2067 | if (adev->pm.pcie_mlw_mask == 0) { | |
2068 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2069 | if (!ret) { | |
2070 | switch (mask) { | |
2071 | case 32: | |
2072 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2073 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2074 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2075 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2076 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2077 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2078 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2079 | break; | |
2080 | case 16: | |
2081 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2082 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2083 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2084 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2085 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2086 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2087 | break; | |
2088 | case 12: | |
2089 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2090 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2091 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2092 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2093 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2094 | break; | |
2095 | case 8: | |
2096 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2097 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2098 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2099 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2100 | break; | |
2101 | case 4: | |
2102 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2103 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2104 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2105 | break; | |
2106 | case 2: | |
2107 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2108 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2109 | break; | |
2110 | case 1: | |
2111 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2112 | break; | |
2113 | default: | |
2114 | break; | |
2115 | } | |
2116 | } else { | |
2117 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2118 | } |
2119 | } | |
2120 | } | |
d38ceaf9 AD |
2121 | |
2122 | /* | |
2123 | * Debugfs | |
2124 | */ | |
2125 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2126 | const struct drm_info_list *files, |
d38ceaf9 AD |
2127 | unsigned nfiles) |
2128 | { | |
2129 | unsigned i; | |
2130 | ||
2131 | for (i = 0; i < adev->debugfs_count; i++) { | |
2132 | if (adev->debugfs[i].files == files) { | |
2133 | /* Already registered */ | |
2134 | return 0; | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | i = adev->debugfs_count + 1; | |
2139 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2140 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2141 | DRM_ERROR("Report so we increase " | |
2142 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2143 | return -EINVAL; | |
2144 | } | |
2145 | adev->debugfs[adev->debugfs_count].files = files; | |
2146 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2147 | adev->debugfs_count = i; | |
2148 | #if defined(CONFIG_DEBUG_FS) | |
2149 | drm_debugfs_create_files(files, nfiles, | |
2150 | adev->ddev->control->debugfs_root, | |
2151 | adev->ddev->control); | |
2152 | drm_debugfs_create_files(files, nfiles, | |
2153 | adev->ddev->primary->debugfs_root, | |
2154 | adev->ddev->primary); | |
2155 | #endif | |
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
2160 | { | |
2161 | #if defined(CONFIG_DEBUG_FS) | |
2162 | unsigned i; | |
2163 | ||
2164 | for (i = 0; i < adev->debugfs_count; i++) { | |
2165 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2166 | adev->debugfs[i].num_files, | |
2167 | adev->ddev->control); | |
2168 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2169 | adev->debugfs[i].num_files, | |
2170 | adev->ddev->primary); | |
2171 | } | |
2172 | #endif | |
2173 | } | |
2174 | ||
2175 | #if defined(CONFIG_DEBUG_FS) | |
2176 | ||
2177 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2178 | size_t size, loff_t *pos) | |
2179 | { | |
2180 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2181 | ssize_t result = 0; | |
2182 | int r; | |
56628159 TSD |
2183 | bool use_bank; |
2184 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
2185 | |
2186 | if (size & 0x3 || *pos & 0x3) | |
2187 | return -EINVAL; | |
2188 | ||
56628159 TSD |
2189 | if (*pos & (1ULL << 62)) { |
2190 | se_bank = (*pos >> 24) & 0x3FF; | |
2191 | sh_bank = (*pos >> 34) & 0x3FF; | |
2192 | instance_bank = (*pos >> 44) & 0x3FF; | |
2193 | use_bank = 1; | |
2194 | *pos &= 0xFFFFFF; | |
2195 | } else { | |
2196 | use_bank = 0; | |
2197 | } | |
2198 | ||
2199 | if (use_bank) { | |
2200 | if (sh_bank >= adev->gfx.config.max_sh_per_se || | |
2201 | se_bank >= adev->gfx.config.max_shader_engines) | |
2202 | return -EINVAL; | |
2203 | mutex_lock(&adev->grbm_idx_mutex); | |
2204 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2205 | sh_bank, instance_bank); | |
2206 | } | |
2207 | ||
d38ceaf9 AD |
2208 | while (size) { |
2209 | uint32_t value; | |
2210 | ||
2211 | if (*pos > adev->rmmio_size) | |
56628159 | 2212 | goto end; |
d38ceaf9 AD |
2213 | |
2214 | value = RREG32(*pos >> 2); | |
2215 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2216 | if (r) { |
2217 | result = r; | |
2218 | goto end; | |
2219 | } | |
d38ceaf9 AD |
2220 | |
2221 | result += 4; | |
2222 | buf += 4; | |
2223 | *pos += 4; | |
2224 | size -= 4; | |
2225 | } | |
2226 | ||
56628159 TSD |
2227 | end: |
2228 | if (use_bank) { | |
2229 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2230 | mutex_unlock(&adev->grbm_idx_mutex); | |
2231 | } | |
2232 | ||
d38ceaf9 AD |
2233 | return result; |
2234 | } | |
2235 | ||
2236 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2237 | size_t size, loff_t *pos) | |
2238 | { | |
2239 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2240 | ssize_t result = 0; | |
2241 | int r; | |
2242 | ||
2243 | if (size & 0x3 || *pos & 0x3) | |
2244 | return -EINVAL; | |
2245 | ||
2246 | while (size) { | |
2247 | uint32_t value; | |
2248 | ||
2249 | if (*pos > adev->rmmio_size) | |
2250 | return result; | |
2251 | ||
2252 | r = get_user(value, (uint32_t *)buf); | |
2253 | if (r) | |
2254 | return r; | |
2255 | ||
2256 | WREG32(*pos >> 2, value); | |
2257 | ||
2258 | result += 4; | |
2259 | buf += 4; | |
2260 | *pos += 4; | |
2261 | size -= 4; | |
2262 | } | |
2263 | ||
2264 | return result; | |
2265 | } | |
2266 | ||
adcec288 TSD |
2267 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2268 | size_t size, loff_t *pos) | |
2269 | { | |
2270 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2271 | ssize_t result = 0; | |
2272 | int r; | |
2273 | ||
2274 | if (size & 0x3 || *pos & 0x3) | |
2275 | return -EINVAL; | |
2276 | ||
2277 | while (size) { | |
2278 | uint32_t value; | |
2279 | ||
2280 | value = RREG32_PCIE(*pos >> 2); | |
2281 | r = put_user(value, (uint32_t *)buf); | |
2282 | if (r) | |
2283 | return r; | |
2284 | ||
2285 | result += 4; | |
2286 | buf += 4; | |
2287 | *pos += 4; | |
2288 | size -= 4; | |
2289 | } | |
2290 | ||
2291 | return result; | |
2292 | } | |
2293 | ||
2294 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2295 | size_t size, loff_t *pos) | |
2296 | { | |
2297 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2298 | ssize_t result = 0; | |
2299 | int r; | |
2300 | ||
2301 | if (size & 0x3 || *pos & 0x3) | |
2302 | return -EINVAL; | |
2303 | ||
2304 | while (size) { | |
2305 | uint32_t value; | |
2306 | ||
2307 | r = get_user(value, (uint32_t *)buf); | |
2308 | if (r) | |
2309 | return r; | |
2310 | ||
2311 | WREG32_PCIE(*pos >> 2, value); | |
2312 | ||
2313 | result += 4; | |
2314 | buf += 4; | |
2315 | *pos += 4; | |
2316 | size -= 4; | |
2317 | } | |
2318 | ||
2319 | return result; | |
2320 | } | |
2321 | ||
2322 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
2323 | size_t size, loff_t *pos) | |
2324 | { | |
2325 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2326 | ssize_t result = 0; | |
2327 | int r; | |
2328 | ||
2329 | if (size & 0x3 || *pos & 0x3) | |
2330 | return -EINVAL; | |
2331 | ||
2332 | while (size) { | |
2333 | uint32_t value; | |
2334 | ||
2335 | value = RREG32_DIDT(*pos >> 2); | |
2336 | r = put_user(value, (uint32_t *)buf); | |
2337 | if (r) | |
2338 | return r; | |
2339 | ||
2340 | result += 4; | |
2341 | buf += 4; | |
2342 | *pos += 4; | |
2343 | size -= 4; | |
2344 | } | |
2345 | ||
2346 | return result; | |
2347 | } | |
2348 | ||
2349 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
2350 | size_t size, loff_t *pos) | |
2351 | { | |
2352 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2353 | ssize_t result = 0; | |
2354 | int r; | |
2355 | ||
2356 | if (size & 0x3 || *pos & 0x3) | |
2357 | return -EINVAL; | |
2358 | ||
2359 | while (size) { | |
2360 | uint32_t value; | |
2361 | ||
2362 | r = get_user(value, (uint32_t *)buf); | |
2363 | if (r) | |
2364 | return r; | |
2365 | ||
2366 | WREG32_DIDT(*pos >> 2, value); | |
2367 | ||
2368 | result += 4; | |
2369 | buf += 4; | |
2370 | *pos += 4; | |
2371 | size -= 4; | |
2372 | } | |
2373 | ||
2374 | return result; | |
2375 | } | |
2376 | ||
2377 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
2378 | size_t size, loff_t *pos) | |
2379 | { | |
2380 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2381 | ssize_t result = 0; | |
2382 | int r; | |
2383 | ||
2384 | if (size & 0x3 || *pos & 0x3) | |
2385 | return -EINVAL; | |
2386 | ||
2387 | while (size) { | |
2388 | uint32_t value; | |
2389 | ||
2390 | value = RREG32_SMC(*pos >> 2); | |
2391 | r = put_user(value, (uint32_t *)buf); | |
2392 | if (r) | |
2393 | return r; | |
2394 | ||
2395 | result += 4; | |
2396 | buf += 4; | |
2397 | *pos += 4; | |
2398 | size -= 4; | |
2399 | } | |
2400 | ||
2401 | return result; | |
2402 | } | |
2403 | ||
2404 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
2405 | size_t size, loff_t *pos) | |
2406 | { | |
2407 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2408 | ssize_t result = 0; | |
2409 | int r; | |
2410 | ||
2411 | if (size & 0x3 || *pos & 0x3) | |
2412 | return -EINVAL; | |
2413 | ||
2414 | while (size) { | |
2415 | uint32_t value; | |
2416 | ||
2417 | r = get_user(value, (uint32_t *)buf); | |
2418 | if (r) | |
2419 | return r; | |
2420 | ||
2421 | WREG32_SMC(*pos >> 2, value); | |
2422 | ||
2423 | result += 4; | |
2424 | buf += 4; | |
2425 | *pos += 4; | |
2426 | size -= 4; | |
2427 | } | |
2428 | ||
2429 | return result; | |
2430 | } | |
2431 | ||
1e051413 TSD |
2432 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
2433 | size_t size, loff_t *pos) | |
2434 | { | |
2435 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2436 | ssize_t result = 0; | |
2437 | int r; | |
2438 | uint32_t *config, no_regs = 0; | |
2439 | ||
2440 | if (size & 0x3 || *pos & 0x3) | |
2441 | return -EINVAL; | |
2442 | ||
2443 | config = kmalloc(256 * sizeof(*config), GFP_KERNEL); | |
2444 | if (!config) | |
2445 | return -ENOMEM; | |
2446 | ||
2447 | /* version, increment each time something is added */ | |
2448 | config[no_regs++] = 0; | |
2449 | config[no_regs++] = adev->gfx.config.max_shader_engines; | |
2450 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
2451 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
2452 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
2453 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
2454 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
2455 | config[no_regs++] = adev->gfx.config.max_gprs; | |
2456 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
2457 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
2458 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
2459 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
2460 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
2461 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
2462 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
2463 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
2464 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
2465 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
2466 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
2467 | config[no_regs++] = adev->gfx.config.num_gpus; | |
2468 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
2469 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
2470 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
2471 | config[no_regs++] = adev->gfx.config.num_rbs; | |
2472 | ||
2473 | while (size && (*pos < no_regs * 4)) { | |
2474 | uint32_t value; | |
2475 | ||
2476 | value = config[*pos >> 2]; | |
2477 | r = put_user(value, (uint32_t *)buf); | |
2478 | if (r) { | |
2479 | kfree(config); | |
2480 | return r; | |
2481 | } | |
2482 | ||
2483 | result += 4; | |
2484 | buf += 4; | |
2485 | *pos += 4; | |
2486 | size -= 4; | |
2487 | } | |
2488 | ||
2489 | kfree(config); | |
2490 | return result; | |
2491 | } | |
2492 | ||
2493 | ||
d38ceaf9 AD |
2494 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
2495 | .owner = THIS_MODULE, | |
2496 | .read = amdgpu_debugfs_regs_read, | |
2497 | .write = amdgpu_debugfs_regs_write, | |
2498 | .llseek = default_llseek | |
2499 | }; | |
adcec288 TSD |
2500 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
2501 | .owner = THIS_MODULE, | |
2502 | .read = amdgpu_debugfs_regs_didt_read, | |
2503 | .write = amdgpu_debugfs_regs_didt_write, | |
2504 | .llseek = default_llseek | |
2505 | }; | |
2506 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
2507 | .owner = THIS_MODULE, | |
2508 | .read = amdgpu_debugfs_regs_pcie_read, | |
2509 | .write = amdgpu_debugfs_regs_pcie_write, | |
2510 | .llseek = default_llseek | |
2511 | }; | |
2512 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
2513 | .owner = THIS_MODULE, | |
2514 | .read = amdgpu_debugfs_regs_smc_read, | |
2515 | .write = amdgpu_debugfs_regs_smc_write, | |
2516 | .llseek = default_llseek | |
2517 | }; | |
2518 | ||
1e051413 TSD |
2519 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
2520 | .owner = THIS_MODULE, | |
2521 | .read = amdgpu_debugfs_gca_config_read, | |
2522 | .llseek = default_llseek | |
2523 | }; | |
2524 | ||
adcec288 TSD |
2525 | static const struct file_operations *debugfs_regs[] = { |
2526 | &amdgpu_debugfs_regs_fops, | |
2527 | &amdgpu_debugfs_regs_didt_fops, | |
2528 | &amdgpu_debugfs_regs_pcie_fops, | |
2529 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 2530 | &amdgpu_debugfs_gca_config_fops, |
adcec288 TSD |
2531 | }; |
2532 | ||
2533 | static const char *debugfs_regs_names[] = { | |
2534 | "amdgpu_regs", | |
2535 | "amdgpu_regs_didt", | |
2536 | "amdgpu_regs_pcie", | |
2537 | "amdgpu_regs_smc", | |
1e051413 | 2538 | "amdgpu_gca_config", |
adcec288 | 2539 | }; |
d38ceaf9 AD |
2540 | |
2541 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2542 | { | |
2543 | struct drm_minor *minor = adev->ddev->primary; | |
2544 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
2545 | unsigned i, j; |
2546 | ||
2547 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2548 | ent = debugfs_create_file(debugfs_regs_names[i], | |
2549 | S_IFREG | S_IRUGO, root, | |
2550 | adev, debugfs_regs[i]); | |
2551 | if (IS_ERR(ent)) { | |
2552 | for (j = 0; j < i; j++) { | |
2553 | debugfs_remove(adev->debugfs_regs[i]); | |
2554 | adev->debugfs_regs[i] = NULL; | |
2555 | } | |
2556 | return PTR_ERR(ent); | |
2557 | } | |
d38ceaf9 | 2558 | |
adcec288 TSD |
2559 | if (!i) |
2560 | i_size_write(ent->d_inode, adev->rmmio_size); | |
2561 | adev->debugfs_regs[i] = ent; | |
2562 | } | |
d38ceaf9 AD |
2563 | |
2564 | return 0; | |
2565 | } | |
2566 | ||
2567 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
2568 | { | |
adcec288 TSD |
2569 | unsigned i; |
2570 | ||
2571 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2572 | if (adev->debugfs_regs[i]) { | |
2573 | debugfs_remove(adev->debugfs_regs[i]); | |
2574 | adev->debugfs_regs[i] = NULL; | |
2575 | } | |
2576 | } | |
d38ceaf9 AD |
2577 | } |
2578 | ||
2579 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
2580 | { | |
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
2585 | { | |
2586 | } | |
7cebc728 AK |
2587 | #else |
2588 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2589 | { | |
2590 | return 0; | |
2591 | } | |
2592 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 2593 | #endif |