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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <drm/drmP.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include <linux/vgaarb.h> | |
35 | #include <linux/vga_switcheroo.h> | |
36 | #include <linux/efi.h> | |
37 | #include "amdgpu.h" | |
38 | #include "amdgpu_i2c.h" | |
39 | #include "atom.h" | |
40 | #include "amdgpu_atombios.h" | |
d0dd7f0c | 41 | #include "amd_pcie.h" |
a2e73f56 AD |
42 | #ifdef CONFIG_DRM_AMDGPU_CIK |
43 | #include "cik.h" | |
44 | #endif | |
aaa36a97 | 45 | #include "vi.h" |
d38ceaf9 AD |
46 | #include "bif/bif_4_1_d.h" |
47 | ||
48 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
49 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
50 | ||
51 | static const char *amdgpu_asic_name[] = { | |
52 | "BONAIRE", | |
53 | "KAVERI", | |
54 | "KABINI", | |
55 | "HAWAII", | |
56 | "MULLINS", | |
57 | "TOPAZ", | |
58 | "TONGA", | |
48299f95 | 59 | "FIJI", |
d38ceaf9 | 60 | "CARRIZO", |
139f4917 | 61 | "STONEY", |
2cc0c0b5 FC |
62 | "POLARIS10", |
63 | "POLARIS11", | |
d38ceaf9 AD |
64 | "LAST", |
65 | }; | |
66 | ||
67 | bool amdgpu_device_is_px(struct drm_device *dev) | |
68 | { | |
69 | struct amdgpu_device *adev = dev->dev_private; | |
70 | ||
2f7d10b3 | 71 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
72 | return true; |
73 | return false; | |
74 | } | |
75 | ||
76 | /* | |
77 | * MMIO register access helper functions. | |
78 | */ | |
79 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
80 | bool always_indirect) | |
81 | { | |
82 | if ((reg * 4) < adev->rmmio_size && !always_indirect) | |
83 | return readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
84 | else { | |
85 | unsigned long flags; | |
86 | uint32_t ret; | |
87 | ||
88 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
89 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
90 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
91 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
92 | ||
93 | return ret; | |
94 | } | |
95 | } | |
96 | ||
97 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
98 | bool always_indirect) | |
99 | { | |
100 | if ((reg * 4) < adev->rmmio_size && !always_indirect) | |
101 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
102 | else { | |
103 | unsigned long flags; | |
104 | ||
105 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
106 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
107 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
108 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
109 | } | |
110 | } | |
111 | ||
112 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
113 | { | |
114 | if ((reg * 4) < adev->rio_mem_size) | |
115 | return ioread32(adev->rio_mem + (reg * 4)); | |
116 | else { | |
117 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
118 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
119 | } | |
120 | } | |
121 | ||
122 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
123 | { | |
124 | ||
125 | if ((reg * 4) < adev->rio_mem_size) | |
126 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
127 | else { | |
128 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
129 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
130 | } | |
131 | } | |
132 | ||
133 | /** | |
134 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
135 | * | |
136 | * @adev: amdgpu_device pointer | |
137 | * @index: doorbell index | |
138 | * | |
139 | * Returns the value in the doorbell aperture at the | |
140 | * requested doorbell index (CIK). | |
141 | */ | |
142 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
143 | { | |
144 | if (index < adev->doorbell.num_doorbells) { | |
145 | return readl(adev->doorbell.ptr + index); | |
146 | } else { | |
147 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
148 | return 0; | |
149 | } | |
150 | } | |
151 | ||
152 | /** | |
153 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
154 | * | |
155 | * @adev: amdgpu_device pointer | |
156 | * @index: doorbell index | |
157 | * @v: value to write | |
158 | * | |
159 | * Writes @v to the doorbell aperture at the | |
160 | * requested doorbell index (CIK). | |
161 | */ | |
162 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
163 | { | |
164 | if (index < adev->doorbell.num_doorbells) { | |
165 | writel(v, adev->doorbell.ptr + index); | |
166 | } else { | |
167 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
168 | } | |
169 | } | |
170 | ||
171 | /** | |
172 | * amdgpu_invalid_rreg - dummy reg read function | |
173 | * | |
174 | * @adev: amdgpu device pointer | |
175 | * @reg: offset of register | |
176 | * | |
177 | * Dummy register read function. Used for register blocks | |
178 | * that certain asics don't have (all asics). | |
179 | * Returns the value in the register. | |
180 | */ | |
181 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
182 | { | |
183 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
184 | BUG(); | |
185 | return 0; | |
186 | } | |
187 | ||
188 | /** | |
189 | * amdgpu_invalid_wreg - dummy reg write function | |
190 | * | |
191 | * @adev: amdgpu device pointer | |
192 | * @reg: offset of register | |
193 | * @v: value to write to the register | |
194 | * | |
195 | * Dummy register read function. Used for register blocks | |
196 | * that certain asics don't have (all asics). | |
197 | */ | |
198 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
199 | { | |
200 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
201 | reg, v); | |
202 | BUG(); | |
203 | } | |
204 | ||
205 | /** | |
206 | * amdgpu_block_invalid_rreg - dummy reg read function | |
207 | * | |
208 | * @adev: amdgpu device pointer | |
209 | * @block: offset of instance | |
210 | * @reg: offset of register | |
211 | * | |
212 | * Dummy register read function. Used for register blocks | |
213 | * that certain asics don't have (all asics). | |
214 | * Returns the value in the register. | |
215 | */ | |
216 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
217 | uint32_t block, uint32_t reg) | |
218 | { | |
219 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
220 | reg, block); | |
221 | BUG(); | |
222 | return 0; | |
223 | } | |
224 | ||
225 | /** | |
226 | * amdgpu_block_invalid_wreg - dummy reg write function | |
227 | * | |
228 | * @adev: amdgpu device pointer | |
229 | * @block: offset of instance | |
230 | * @reg: offset of register | |
231 | * @v: value to write to the register | |
232 | * | |
233 | * Dummy register read function. Used for register blocks | |
234 | * that certain asics don't have (all asics). | |
235 | */ | |
236 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
237 | uint32_t block, | |
238 | uint32_t reg, uint32_t v) | |
239 | { | |
240 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
241 | reg, block, v); | |
242 | BUG(); | |
243 | } | |
244 | ||
245 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
246 | { | |
247 | int r; | |
248 | ||
249 | if (adev->vram_scratch.robj == NULL) { | |
250 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d AD |
251 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
252 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 253 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
254 | if (r) { |
255 | return r; | |
256 | } | |
257 | } | |
258 | ||
259 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
260 | if (unlikely(r != 0)) | |
261 | return r; | |
262 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
263 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
264 | if (r) { | |
265 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
266 | return r; | |
267 | } | |
268 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
269 | (void **)&adev->vram_scratch.ptr); | |
270 | if (r) | |
271 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
272 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
273 | ||
274 | return r; | |
275 | } | |
276 | ||
277 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
278 | { | |
279 | int r; | |
280 | ||
281 | if (adev->vram_scratch.robj == NULL) { | |
282 | return; | |
283 | } | |
284 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
285 | if (likely(r == 0)) { | |
286 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
287 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
288 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
289 | } | |
290 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
291 | } | |
292 | ||
293 | /** | |
294 | * amdgpu_program_register_sequence - program an array of registers. | |
295 | * | |
296 | * @adev: amdgpu_device pointer | |
297 | * @registers: pointer to the register array | |
298 | * @array_size: size of the register array | |
299 | * | |
300 | * Programs an array or registers with and and or masks. | |
301 | * This is a helper for setting golden registers. | |
302 | */ | |
303 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
304 | const u32 *registers, | |
305 | const u32 array_size) | |
306 | { | |
307 | u32 tmp, reg, and_mask, or_mask; | |
308 | int i; | |
309 | ||
310 | if (array_size % 3) | |
311 | return; | |
312 | ||
313 | for (i = 0; i < array_size; i +=3) { | |
314 | reg = registers[i + 0]; | |
315 | and_mask = registers[i + 1]; | |
316 | or_mask = registers[i + 2]; | |
317 | ||
318 | if (and_mask == 0xffffffff) { | |
319 | tmp = or_mask; | |
320 | } else { | |
321 | tmp = RREG32(reg); | |
322 | tmp &= ~and_mask; | |
323 | tmp |= or_mask; | |
324 | } | |
325 | WREG32(reg, tmp); | |
326 | } | |
327 | } | |
328 | ||
329 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
330 | { | |
331 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
332 | } | |
333 | ||
334 | /* | |
335 | * GPU doorbell aperture helpers function. | |
336 | */ | |
337 | /** | |
338 | * amdgpu_doorbell_init - Init doorbell driver information. | |
339 | * | |
340 | * @adev: amdgpu_device pointer | |
341 | * | |
342 | * Init doorbell driver information (CIK) | |
343 | * Returns 0 on success, error on failure. | |
344 | */ | |
345 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
346 | { | |
347 | /* doorbell bar mapping */ | |
348 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
349 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
350 | ||
edf600da | 351 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
352 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
353 | if (adev->doorbell.num_doorbells == 0) | |
354 | return -EINVAL; | |
355 | ||
356 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
357 | if (adev->doorbell.ptr == NULL) { | |
358 | return -ENOMEM; | |
359 | } | |
360 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
361 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | /** | |
367 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
368 | * | |
369 | * @adev: amdgpu_device pointer | |
370 | * | |
371 | * Tear down doorbell driver information (CIK) | |
372 | */ | |
373 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
374 | { | |
375 | iounmap(adev->doorbell.ptr); | |
376 | adev->doorbell.ptr = NULL; | |
377 | } | |
378 | ||
379 | /** | |
380 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
381 | * setup amdkfd | |
382 | * | |
383 | * @adev: amdgpu_device pointer | |
384 | * @aperture_base: output returning doorbell aperture base physical address | |
385 | * @aperture_size: output returning doorbell aperture size in bytes | |
386 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
387 | * | |
388 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
389 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
390 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
391 | */ | |
392 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
393 | phys_addr_t *aperture_base, | |
394 | size_t *aperture_size, | |
395 | size_t *start_offset) | |
396 | { | |
397 | /* | |
398 | * The first num_doorbells are used by amdgpu. | |
399 | * amdkfd takes whatever's left in the aperture. | |
400 | */ | |
401 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
402 | *aperture_base = adev->doorbell.base; | |
403 | *aperture_size = adev->doorbell.size; | |
404 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
405 | } else { | |
406 | *aperture_base = 0; | |
407 | *aperture_size = 0; | |
408 | *start_offset = 0; | |
409 | } | |
410 | } | |
411 | ||
412 | /* | |
413 | * amdgpu_wb_*() | |
414 | * Writeback is the the method by which the the GPU updates special pages | |
415 | * in memory with the status of certain GPU events (fences, ring pointers, | |
416 | * etc.). | |
417 | */ | |
418 | ||
419 | /** | |
420 | * amdgpu_wb_fini - Disable Writeback and free memory | |
421 | * | |
422 | * @adev: amdgpu_device pointer | |
423 | * | |
424 | * Disables Writeback and frees the Writeback memory (all asics). | |
425 | * Used at driver shutdown. | |
426 | */ | |
427 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
428 | { | |
429 | if (adev->wb.wb_obj) { | |
430 | if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { | |
431 | amdgpu_bo_kunmap(adev->wb.wb_obj); | |
432 | amdgpu_bo_unpin(adev->wb.wb_obj); | |
433 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
434 | } | |
435 | amdgpu_bo_unref(&adev->wb.wb_obj); | |
436 | adev->wb.wb = NULL; | |
437 | adev->wb.wb_obj = NULL; | |
438 | } | |
439 | } | |
440 | ||
441 | /** | |
442 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
443 | * | |
444 | * @adev: amdgpu_device pointer | |
445 | * | |
446 | * Disables Writeback and frees the Writeback memory (all asics). | |
447 | * Used at driver startup. | |
448 | * Returns 0 on success or an -error on failure. | |
449 | */ | |
450 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
451 | { | |
452 | int r; | |
453 | ||
454 | if (adev->wb.wb_obj == NULL) { | |
455 | r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, | |
72d7668b CK |
456 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, |
457 | &adev->wb.wb_obj); | |
d38ceaf9 AD |
458 | if (r) { |
459 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
460 | return r; | |
461 | } | |
462 | r = amdgpu_bo_reserve(adev->wb.wb_obj, false); | |
463 | if (unlikely(r != 0)) { | |
464 | amdgpu_wb_fini(adev); | |
465 | return r; | |
466 | } | |
467 | r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, | |
468 | &adev->wb.gpu_addr); | |
469 | if (r) { | |
470 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
471 | dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); | |
472 | amdgpu_wb_fini(adev); | |
473 | return r; | |
474 | } | |
475 | r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); | |
476 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
477 | if (r) { | |
478 | dev_warn(adev->dev, "(%d) map WB bo failed\n", r); | |
479 | amdgpu_wb_fini(adev); | |
480 | return r; | |
481 | } | |
482 | ||
483 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
484 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
485 | ||
486 | /* clear wb memory */ | |
487 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | /** | |
494 | * amdgpu_wb_get - Allocate a wb entry | |
495 | * | |
496 | * @adev: amdgpu_device pointer | |
497 | * @wb: wb index | |
498 | * | |
499 | * Allocate a wb slot for use by the driver (all asics). | |
500 | * Returns 0 on success or -EINVAL on failure. | |
501 | */ | |
502 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
503 | { | |
504 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
505 | if (offset < adev->wb.num_wb) { | |
506 | __set_bit(offset, adev->wb.used); | |
507 | *wb = offset; | |
508 | return 0; | |
509 | } else { | |
510 | return -EINVAL; | |
511 | } | |
512 | } | |
513 | ||
514 | /** | |
515 | * amdgpu_wb_free - Free a wb entry | |
516 | * | |
517 | * @adev: amdgpu_device pointer | |
518 | * @wb: wb index | |
519 | * | |
520 | * Free a wb slot allocated for use by the driver (all asics) | |
521 | */ | |
522 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
523 | { | |
524 | if (wb < adev->wb.num_wb) | |
525 | __clear_bit(wb, adev->wb.used); | |
526 | } | |
527 | ||
528 | /** | |
529 | * amdgpu_vram_location - try to find VRAM location | |
530 | * @adev: amdgpu device structure holding all necessary informations | |
531 | * @mc: memory controller structure holding memory informations | |
532 | * @base: base address at which to put VRAM | |
533 | * | |
534 | * Function will place try to place VRAM at base address provided | |
535 | * as parameter (which is so far either PCI aperture address or | |
536 | * for IGP TOM base address). | |
537 | * | |
538 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
539 | * address space then we limit the VRAM size to the aperture. | |
540 | * | |
541 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
542 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
543 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
544 | * not IGP. | |
545 | * | |
546 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
547 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
548 | * Novell bug 204882 + along with lots of ubuntu ones | |
549 | * | |
550 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
551 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
552 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
553 | * ones) | |
554 | * | |
555 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
556 | * explicitly check for that thought. | |
557 | * | |
558 | * FIXME: when reducing VRAM size align new size on power of 2. | |
559 | */ | |
560 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
561 | { | |
562 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
563 | ||
564 | mc->vram_start = base; | |
565 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
566 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
567 | mc->real_vram_size = mc->aper_size; | |
568 | mc->mc_vram_size = mc->aper_size; | |
569 | } | |
570 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
571 | if (limit && limit < mc->real_vram_size) | |
572 | mc->real_vram_size = limit; | |
573 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
574 | mc->mc_vram_size >> 20, mc->vram_start, | |
575 | mc->vram_end, mc->real_vram_size >> 20); | |
576 | } | |
577 | ||
578 | /** | |
579 | * amdgpu_gtt_location - try to find GTT location | |
580 | * @adev: amdgpu device structure holding all necessary informations | |
581 | * @mc: memory controller structure holding memory informations | |
582 | * | |
583 | * Function will place try to place GTT before or after VRAM. | |
584 | * | |
585 | * If GTT size is bigger than space left then we ajust GTT size. | |
586 | * Thus function will never fails. | |
587 | * | |
588 | * FIXME: when reducing GTT size align new size on power of 2. | |
589 | */ | |
590 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
591 | { | |
592 | u64 size_af, size_bf; | |
593 | ||
594 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
595 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
596 | if (size_bf > size_af) { | |
597 | if (mc->gtt_size > size_bf) { | |
598 | dev_warn(adev->dev, "limiting GTT\n"); | |
599 | mc->gtt_size = size_bf; | |
600 | } | |
601 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
602 | } else { | |
603 | if (mc->gtt_size > size_af) { | |
604 | dev_warn(adev->dev, "limiting GTT\n"); | |
605 | mc->gtt_size = size_af; | |
606 | } | |
607 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
608 | } | |
609 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
610 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
611 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
612 | } | |
613 | ||
614 | /* | |
615 | * GPU helpers function. | |
616 | */ | |
617 | /** | |
618 | * amdgpu_card_posted - check if the hw has already been initialized | |
619 | * | |
620 | * @adev: amdgpu_device pointer | |
621 | * | |
622 | * Check if the asic has been initialized (all asics). | |
623 | * Used at driver startup. | |
624 | * Returns true if initialized or false if not. | |
625 | */ | |
626 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
627 | { | |
628 | uint32_t reg; | |
629 | ||
630 | /* then check MEM_SIZE, in case the crtcs are off */ | |
631 | reg = RREG32(mmCONFIG_MEMSIZE); | |
632 | ||
633 | if (reg) | |
634 | return true; | |
635 | ||
636 | return false; | |
637 | ||
638 | } | |
639 | ||
d38ceaf9 AD |
640 | /** |
641 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
642 | * | |
643 | * @adev: amdgpu_device pointer | |
644 | * | |
645 | * Allocate the dummy page used by the driver (all asics). | |
646 | * This dummy page is used by the driver as a filler for gart entries | |
647 | * when pages are taken out of the GART | |
648 | * Returns 0 on sucess, -ENOMEM on failure. | |
649 | */ | |
650 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
651 | { | |
652 | if (adev->dummy_page.page) | |
653 | return 0; | |
654 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
655 | if (adev->dummy_page.page == NULL) | |
656 | return -ENOMEM; | |
657 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
658 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
659 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
660 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
661 | __free_page(adev->dummy_page.page); | |
662 | adev->dummy_page.page = NULL; | |
663 | return -ENOMEM; | |
664 | } | |
665 | return 0; | |
666 | } | |
667 | ||
668 | /** | |
669 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
670 | * | |
671 | * @adev: amdgpu_device pointer | |
672 | * | |
673 | * Frees the dummy page used by the driver (all asics). | |
674 | */ | |
675 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
676 | { | |
677 | if (adev->dummy_page.page == NULL) | |
678 | return; | |
679 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
680 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
681 | __free_page(adev->dummy_page.page); | |
682 | adev->dummy_page.page = NULL; | |
683 | } | |
684 | ||
685 | ||
686 | /* ATOM accessor methods */ | |
687 | /* | |
688 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
689 | * driver registers callbacks to access registers and the interpreter | |
690 | * in the driver parses the tables and executes then to program specific | |
691 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
692 | * atombios.h, and atom.c | |
693 | */ | |
694 | ||
695 | /** | |
696 | * cail_pll_read - read PLL register | |
697 | * | |
698 | * @info: atom card_info pointer | |
699 | * @reg: PLL register offset | |
700 | * | |
701 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
702 | * Returns the value of the PLL register. | |
703 | */ | |
704 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
705 | { | |
706 | return 0; | |
707 | } | |
708 | ||
709 | /** | |
710 | * cail_pll_write - write PLL register | |
711 | * | |
712 | * @info: atom card_info pointer | |
713 | * @reg: PLL register offset | |
714 | * @val: value to write to the pll register | |
715 | * | |
716 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
717 | */ | |
718 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
719 | { | |
720 | ||
721 | } | |
722 | ||
723 | /** | |
724 | * cail_mc_read - read MC (Memory Controller) register | |
725 | * | |
726 | * @info: atom card_info pointer | |
727 | * @reg: MC register offset | |
728 | * | |
729 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
730 | * Returns the value of the MC register. | |
731 | */ | |
732 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
733 | { | |
734 | return 0; | |
735 | } | |
736 | ||
737 | /** | |
738 | * cail_mc_write - write MC (Memory Controller) register | |
739 | * | |
740 | * @info: atom card_info pointer | |
741 | * @reg: MC register offset | |
742 | * @val: value to write to the pll register | |
743 | * | |
744 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
745 | */ | |
746 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
747 | { | |
748 | ||
749 | } | |
750 | ||
751 | /** | |
752 | * cail_reg_write - write MMIO register | |
753 | * | |
754 | * @info: atom card_info pointer | |
755 | * @reg: MMIO register offset | |
756 | * @val: value to write to the pll register | |
757 | * | |
758 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
759 | */ | |
760 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
761 | { | |
762 | struct amdgpu_device *adev = info->dev->dev_private; | |
763 | ||
764 | WREG32(reg, val); | |
765 | } | |
766 | ||
767 | /** | |
768 | * cail_reg_read - read MMIO register | |
769 | * | |
770 | * @info: atom card_info pointer | |
771 | * @reg: MMIO register offset | |
772 | * | |
773 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
774 | * Returns the value of the MMIO register. | |
775 | */ | |
776 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
777 | { | |
778 | struct amdgpu_device *adev = info->dev->dev_private; | |
779 | uint32_t r; | |
780 | ||
781 | r = RREG32(reg); | |
782 | return r; | |
783 | } | |
784 | ||
785 | /** | |
786 | * cail_ioreg_write - write IO register | |
787 | * | |
788 | * @info: atom card_info pointer | |
789 | * @reg: IO register offset | |
790 | * @val: value to write to the pll register | |
791 | * | |
792 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
793 | */ | |
794 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
795 | { | |
796 | struct amdgpu_device *adev = info->dev->dev_private; | |
797 | ||
798 | WREG32_IO(reg, val); | |
799 | } | |
800 | ||
801 | /** | |
802 | * cail_ioreg_read - read IO register | |
803 | * | |
804 | * @info: atom card_info pointer | |
805 | * @reg: IO register offset | |
806 | * | |
807 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
808 | * Returns the value of the IO register. | |
809 | */ | |
810 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
811 | { | |
812 | struct amdgpu_device *adev = info->dev->dev_private; | |
813 | uint32_t r; | |
814 | ||
815 | r = RREG32_IO(reg); | |
816 | return r; | |
817 | } | |
818 | ||
819 | /** | |
820 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
821 | * | |
822 | * @adev: amdgpu_device pointer | |
823 | * | |
824 | * Frees the driver info and register access callbacks for the ATOM | |
825 | * interpreter (r4xx+). | |
826 | * Called at driver shutdown. | |
827 | */ | |
828 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
829 | { | |
89e0ec9f | 830 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 831 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
832 | kfree(adev->mode_info.atom_context->iio); |
833 | } | |
d38ceaf9 AD |
834 | kfree(adev->mode_info.atom_context); |
835 | adev->mode_info.atom_context = NULL; | |
836 | kfree(adev->mode_info.atom_card_info); | |
837 | adev->mode_info.atom_card_info = NULL; | |
838 | } | |
839 | ||
840 | /** | |
841 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
842 | * | |
843 | * @adev: amdgpu_device pointer | |
844 | * | |
845 | * Initializes the driver info and register access callbacks for the | |
846 | * ATOM interpreter (r4xx+). | |
847 | * Returns 0 on sucess, -ENOMEM on failure. | |
848 | * Called at driver startup. | |
849 | */ | |
850 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
851 | { | |
852 | struct card_info *atom_card_info = | |
853 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
854 | ||
855 | if (!atom_card_info) | |
856 | return -ENOMEM; | |
857 | ||
858 | adev->mode_info.atom_card_info = atom_card_info; | |
859 | atom_card_info->dev = adev->ddev; | |
860 | atom_card_info->reg_read = cail_reg_read; | |
861 | atom_card_info->reg_write = cail_reg_write; | |
862 | /* needed for iio ops */ | |
863 | if (adev->rio_mem) { | |
864 | atom_card_info->ioreg_read = cail_ioreg_read; | |
865 | atom_card_info->ioreg_write = cail_ioreg_write; | |
866 | } else { | |
867 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
868 | atom_card_info->ioreg_read = cail_reg_read; | |
869 | atom_card_info->ioreg_write = cail_reg_write; | |
870 | } | |
871 | atom_card_info->mc_read = cail_mc_read; | |
872 | atom_card_info->mc_write = cail_mc_write; | |
873 | atom_card_info->pll_read = cail_pll_read; | |
874 | atom_card_info->pll_write = cail_pll_write; | |
875 | ||
876 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
877 | if (!adev->mode_info.atom_context) { | |
878 | amdgpu_atombios_fini(adev); | |
879 | return -ENOMEM; | |
880 | } | |
881 | ||
882 | mutex_init(&adev->mode_info.atom_context->mutex); | |
883 | amdgpu_atombios_scratch_regs_init(adev); | |
884 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
885 | return 0; | |
886 | } | |
887 | ||
888 | /* if we get transitioned to only one device, take VGA back */ | |
889 | /** | |
890 | * amdgpu_vga_set_decode - enable/disable vga decode | |
891 | * | |
892 | * @cookie: amdgpu_device pointer | |
893 | * @state: enable/disable vga decode | |
894 | * | |
895 | * Enable/disable vga decode (all asics). | |
896 | * Returns VGA resource flags. | |
897 | */ | |
898 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
899 | { | |
900 | struct amdgpu_device *adev = cookie; | |
901 | amdgpu_asic_set_vga_state(adev, state); | |
902 | if (state) | |
903 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
904 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
905 | else | |
906 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
907 | } | |
908 | ||
909 | /** | |
910 | * amdgpu_check_pot_argument - check that argument is a power of two | |
911 | * | |
912 | * @arg: value to check | |
913 | * | |
914 | * Validates that a certain argument is a power of two (all asics). | |
915 | * Returns true if argument is valid. | |
916 | */ | |
917 | static bool amdgpu_check_pot_argument(int arg) | |
918 | { | |
919 | return (arg & (arg - 1)) == 0; | |
920 | } | |
921 | ||
922 | /** | |
923 | * amdgpu_check_arguments - validate module params | |
924 | * | |
925 | * @adev: amdgpu_device pointer | |
926 | * | |
927 | * Validates certain module parameters and updates | |
928 | * the associated values used by the driver (all asics). | |
929 | */ | |
930 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
931 | { | |
5b011235 CZ |
932 | if (amdgpu_sched_jobs < 4) { |
933 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
934 | amdgpu_sched_jobs); | |
935 | amdgpu_sched_jobs = 4; | |
936 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
937 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
938 | amdgpu_sched_jobs); | |
939 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
940 | } | |
d38ceaf9 AD |
941 | |
942 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 943 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
944 | if (amdgpu_gart_size < 32) { |
945 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
946 | amdgpu_gart_size); | |
947 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
948 | } |
949 | } | |
950 | ||
951 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
952 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
953 | amdgpu_vm_size); | |
8dacc127 | 954 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
955 | } |
956 | ||
957 | if (amdgpu_vm_size < 1) { | |
958 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
959 | amdgpu_vm_size); | |
8dacc127 | 960 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
961 | } |
962 | ||
963 | /* | |
964 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
965 | */ | |
966 | if (amdgpu_vm_size > 1024) { | |
967 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
968 | amdgpu_vm_size); | |
8dacc127 | 969 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
970 | } |
971 | ||
972 | /* defines number of bits in page table versus page directory, | |
973 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
974 | * page table and the remaining bits are in the page directory */ | |
975 | if (amdgpu_vm_block_size == -1) { | |
976 | ||
977 | /* Total bits covered by PD + PTs */ | |
978 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
979 | ||
980 | /* Make sure the PD is 4K in size up to 8GB address space. | |
981 | Above that split equal between PD and PTs */ | |
982 | if (amdgpu_vm_size <= 8) | |
983 | amdgpu_vm_block_size = bits - 9; | |
984 | else | |
985 | amdgpu_vm_block_size = (bits + 3) / 2; | |
986 | ||
987 | } else if (amdgpu_vm_block_size < 9) { | |
988 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
989 | amdgpu_vm_block_size); | |
990 | amdgpu_vm_block_size = 9; | |
991 | } | |
992 | ||
993 | if (amdgpu_vm_block_size > 24 || | |
994 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
995 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
996 | amdgpu_vm_block_size); | |
997 | amdgpu_vm_block_size = 9; | |
998 | } | |
999 | } | |
1000 | ||
1001 | /** | |
1002 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1003 | * | |
1004 | * @pdev: pci dev pointer | |
1694467b | 1005 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1006 | * |
1007 | * Callback for the switcheroo driver. Suspends or resumes the | |
1008 | * the asics before or after it is powered up using ACPI methods. | |
1009 | */ | |
1010 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1011 | { | |
1012 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1013 | ||
1014 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1015 | return; | |
1016 | ||
1017 | if (state == VGA_SWITCHEROO_ON) { | |
1018 | unsigned d3_delay = dev->pdev->d3_delay; | |
1019 | ||
1020 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1021 | /* don't suspend or resume card normally */ | |
1022 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1023 | ||
1024 | amdgpu_resume_kms(dev, true, true); | |
1025 | ||
1026 | dev->pdev->d3_delay = d3_delay; | |
1027 | ||
1028 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1029 | drm_kms_helper_poll_enable(dev); | |
1030 | } else { | |
1031 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1032 | drm_kms_helper_poll_disable(dev); | |
1033 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1034 | amdgpu_suspend_kms(dev, true, true); | |
1035 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | /** | |
1040 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1041 | * | |
1042 | * @pdev: pci dev pointer | |
1043 | * | |
1044 | * Callback for the switcheroo driver. Check of the switcheroo | |
1045 | * state can be changed. | |
1046 | * Returns true if the state can be changed, false if not. | |
1047 | */ | |
1048 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1049 | { | |
1050 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1051 | ||
1052 | /* | |
1053 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1054 | * locking inversion with the driver load path. And the access here is | |
1055 | * completely racy anyway. So don't bother with locking for now. | |
1056 | */ | |
1057 | return dev->open_count == 0; | |
1058 | } | |
1059 | ||
1060 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1061 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1062 | .reprobe = NULL, | |
1063 | .can_switch = amdgpu_switcheroo_can_switch, | |
1064 | }; | |
1065 | ||
1066 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1067 | enum amd_ip_block_type block_type, |
1068 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1069 | { |
1070 | int i, r = 0; | |
1071 | ||
1072 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1073 | if (adev->ip_blocks[i].type == block_type) { | |
5fc3aeeb | 1074 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
d38ceaf9 AD |
1075 | state); |
1076 | if (r) | |
1077 | return r; | |
1078 | } | |
1079 | } | |
1080 | return r; | |
1081 | } | |
1082 | ||
1083 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1084 | enum amd_ip_block_type block_type, |
1085 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1086 | { |
1087 | int i, r = 0; | |
1088 | ||
1089 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1090 | if (adev->ip_blocks[i].type == block_type) { | |
5fc3aeeb | 1091 | r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev, |
d38ceaf9 AD |
1092 | state); |
1093 | if (r) | |
1094 | return r; | |
1095 | } | |
1096 | } | |
1097 | return r; | |
1098 | } | |
1099 | ||
1100 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( | |
1101 | struct amdgpu_device *adev, | |
5fc3aeeb | 1102 | enum amd_ip_block_type type) |
d38ceaf9 AD |
1103 | { |
1104 | int i; | |
1105 | ||
1106 | for (i = 0; i < adev->num_ip_blocks; i++) | |
1107 | if (adev->ip_blocks[i].type == type) | |
1108 | return &adev->ip_blocks[i]; | |
1109 | ||
1110 | return NULL; | |
1111 | } | |
1112 | ||
1113 | /** | |
1114 | * amdgpu_ip_block_version_cmp | |
1115 | * | |
1116 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1117 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1118 | * @major: major version |
1119 | * @minor: minor version | |
1120 | * | |
1121 | * return 0 if equal or greater | |
1122 | * return 1 if smaller or the ip_block doesn't exist | |
1123 | */ | |
1124 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1125 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1126 | u32 major, u32 minor) |
1127 | { | |
1128 | const struct amdgpu_ip_block_version *ip_block; | |
1129 | ip_block = amdgpu_get_ip_block(adev, type); | |
1130 | ||
1131 | if (ip_block && ((ip_block->major > major) || | |
1132 | ((ip_block->major == major) && | |
1133 | (ip_block->minor >= minor)))) | |
1134 | return 0; | |
1135 | ||
1136 | return 1; | |
1137 | } | |
1138 | ||
1139 | static int amdgpu_early_init(struct amdgpu_device *adev) | |
1140 | { | |
aaa36a97 | 1141 | int i, r; |
d38ceaf9 AD |
1142 | |
1143 | switch (adev->asic_type) { | |
aaa36a97 AD |
1144 | case CHIP_TOPAZ: |
1145 | case CHIP_TONGA: | |
48299f95 | 1146 | case CHIP_FIJI: |
2cc0c0b5 FC |
1147 | case CHIP_POLARIS11: |
1148 | case CHIP_POLARIS10: | |
aaa36a97 | 1149 | case CHIP_CARRIZO: |
39bb0c92 SL |
1150 | case CHIP_STONEY: |
1151 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1152 | adev->family = AMDGPU_FAMILY_CZ; |
1153 | else | |
1154 | adev->family = AMDGPU_FAMILY_VI; | |
1155 | ||
1156 | r = vi_set_ip_blocks(adev); | |
1157 | if (r) | |
1158 | return r; | |
1159 | break; | |
a2e73f56 AD |
1160 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1161 | case CHIP_BONAIRE: | |
1162 | case CHIP_HAWAII: | |
1163 | case CHIP_KAVERI: | |
1164 | case CHIP_KABINI: | |
1165 | case CHIP_MULLINS: | |
1166 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1167 | adev->family = AMDGPU_FAMILY_CI; | |
1168 | else | |
1169 | adev->family = AMDGPU_FAMILY_KV; | |
1170 | ||
1171 | r = cik_set_ip_blocks(adev); | |
1172 | if (r) | |
1173 | return r; | |
1174 | break; | |
1175 | #endif | |
d38ceaf9 AD |
1176 | default: |
1177 | /* FIXME: not supported yet */ | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | ||
8faf0e08 AD |
1181 | adev->ip_block_status = kcalloc(adev->num_ip_blocks, |
1182 | sizeof(struct amdgpu_ip_block_status), GFP_KERNEL); | |
1183 | if (adev->ip_block_status == NULL) | |
d8d090b7 | 1184 | return -ENOMEM; |
d38ceaf9 AD |
1185 | |
1186 | if (adev->ip_blocks == NULL) { | |
1187 | DRM_ERROR("No IP blocks found!\n"); | |
1188 | return r; | |
1189 | } | |
1190 | ||
1191 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1192 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1193 | DRM_ERROR("disabled ip block: %d\n", i); | |
8faf0e08 | 1194 | adev->ip_block_status[i].valid = false; |
d38ceaf9 AD |
1195 | } else { |
1196 | if (adev->ip_blocks[i].funcs->early_init) { | |
5fc3aeeb | 1197 | r = adev->ip_blocks[i].funcs->early_init((void *)adev); |
2c1a2784 | 1198 | if (r == -ENOENT) { |
8faf0e08 | 1199 | adev->ip_block_status[i].valid = false; |
2c1a2784 | 1200 | } else if (r) { |
88a907d6 | 1201 | DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1202 | return r; |
2c1a2784 | 1203 | } else { |
8faf0e08 | 1204 | adev->ip_block_status[i].valid = true; |
2c1a2784 | 1205 | } |
974e6b64 | 1206 | } else { |
8faf0e08 | 1207 | adev->ip_block_status[i].valid = true; |
d38ceaf9 | 1208 | } |
d38ceaf9 AD |
1209 | } |
1210 | } | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static int amdgpu_init(struct amdgpu_device *adev) | |
1216 | { | |
1217 | int i, r; | |
1218 | ||
1219 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1220 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 | 1221 | continue; |
5fc3aeeb | 1222 | r = adev->ip_blocks[i].funcs->sw_init((void *)adev); |
2c1a2784 | 1223 | if (r) { |
822b2cef | 1224 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1225 | return r; |
2c1a2784 | 1226 | } |
8faf0e08 | 1227 | adev->ip_block_status[i].sw = true; |
d38ceaf9 | 1228 | /* need to do gmc hw init early so we can allocate gpu mem */ |
5fc3aeeb | 1229 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1230 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1231 | if (r) { |
1232 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1233 | return r; |
2c1a2784 | 1234 | } |
5fc3aeeb | 1235 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 AD |
1236 | if (r) { |
1237 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1238 | return r; |
2c1a2784 | 1239 | } |
d38ceaf9 | 1240 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1241 | if (r) { |
1242 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1243 | return r; |
2c1a2784 | 1244 | } |
8faf0e08 | 1245 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1246 | } |
1247 | } | |
1248 | ||
1249 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1250 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 AD |
1251 | continue; |
1252 | /* gmc hw init is done early */ | |
5fc3aeeb | 1253 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1254 | continue; |
5fc3aeeb | 1255 | r = adev->ip_blocks[i].funcs->hw_init((void *)adev); |
2c1a2784 | 1256 | if (r) { |
822b2cef | 1257 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1258 | return r; |
2c1a2784 | 1259 | } |
8faf0e08 | 1260 | adev->ip_block_status[i].hw = true; |
d38ceaf9 AD |
1261 | } |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1267 | { | |
1268 | int i = 0, r; | |
1269 | ||
1270 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1271 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1272 | continue; |
1273 | /* enable clockgating to save power */ | |
5fc3aeeb | 1274 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
1275 | AMD_CG_STATE_GATE); | |
2c1a2784 | 1276 | if (r) { |
822b2cef | 1277 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1278 | return r; |
2c1a2784 | 1279 | } |
d38ceaf9 | 1280 | if (adev->ip_blocks[i].funcs->late_init) { |
5fc3aeeb | 1281 | r = adev->ip_blocks[i].funcs->late_init((void *)adev); |
2c1a2784 | 1282 | if (r) { |
822b2cef | 1283 | DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1284 | return r; |
2c1a2784 | 1285 | } |
d38ceaf9 AD |
1286 | } |
1287 | } | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1293 | { | |
1294 | int i, r; | |
1295 | ||
1296 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
8faf0e08 | 1297 | if (!adev->ip_block_status[i].hw) |
d38ceaf9 | 1298 | continue; |
5fc3aeeb | 1299 | if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1300 | amdgpu_wb_fini(adev); |
1301 | amdgpu_vram_scratch_fini(adev); | |
1302 | } | |
1303 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
5fc3aeeb | 1304 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, |
1305 | AMD_CG_STATE_UNGATE); | |
2c1a2784 | 1306 | if (r) { |
822b2cef | 1307 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1308 | return r; |
2c1a2784 | 1309 | } |
5fc3aeeb | 1310 | r = adev->ip_blocks[i].funcs->hw_fini((void *)adev); |
d38ceaf9 | 1311 | /* XXX handle errors */ |
2c1a2784 | 1312 | if (r) { |
822b2cef | 1313 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1314 | } |
8faf0e08 | 1315 | adev->ip_block_status[i].hw = false; |
d38ceaf9 AD |
1316 | } |
1317 | ||
1318 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
8faf0e08 | 1319 | if (!adev->ip_block_status[i].sw) |
d38ceaf9 | 1320 | continue; |
5fc3aeeb | 1321 | r = adev->ip_blocks[i].funcs->sw_fini((void *)adev); |
d38ceaf9 | 1322 | /* XXX handle errors */ |
2c1a2784 | 1323 | if (r) { |
822b2cef | 1324 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1325 | } |
8faf0e08 AD |
1326 | adev->ip_block_status[i].sw = false; |
1327 | adev->ip_block_status[i].valid = false; | |
d38ceaf9 AD |
1328 | } |
1329 | ||
a6dcfd9c ML |
1330 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
1331 | if (adev->ip_blocks[i].funcs->late_fini) | |
1332 | adev->ip_blocks[i].funcs->late_fini((void *)adev); | |
1333 | } | |
1334 | ||
d38ceaf9 AD |
1335 | return 0; |
1336 | } | |
1337 | ||
1338 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1339 | { | |
1340 | int i, r; | |
1341 | ||
c5a93a28 FC |
1342 | /* ungate SMC block first */ |
1343 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1344 | AMD_CG_STATE_UNGATE); | |
1345 | if (r) { | |
1346 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1347 | } | |
1348 | ||
d38ceaf9 | 1349 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
8faf0e08 | 1350 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1351 | continue; |
1352 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 FC |
1353 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
1354 | r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev, | |
1355 | AMD_CG_STATE_UNGATE); | |
1356 | if (r) { | |
822b2cef | 1357 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
c5a93a28 | 1358 | } |
2c1a2784 | 1359 | } |
d38ceaf9 AD |
1360 | /* XXX handle errors */ |
1361 | r = adev->ip_blocks[i].funcs->suspend(adev); | |
1362 | /* XXX handle errors */ | |
2c1a2784 | 1363 | if (r) { |
822b2cef | 1364 | DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
2c1a2784 | 1365 | } |
d38ceaf9 AD |
1366 | } |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
1371 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1372 | { | |
1373 | int i, r; | |
1374 | ||
1375 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
8faf0e08 | 1376 | if (!adev->ip_block_status[i].valid) |
d38ceaf9 AD |
1377 | continue; |
1378 | r = adev->ip_blocks[i].funcs->resume(adev); | |
2c1a2784 | 1379 | if (r) { |
822b2cef | 1380 | DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r); |
d38ceaf9 | 1381 | return r; |
2c1a2784 | 1382 | } |
d38ceaf9 AD |
1383 | } |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
048765ad AR |
1388 | static bool amdgpu_device_is_virtual(void) |
1389 | { | |
1390 | #ifdef CONFIG_X86 | |
1391 | return boot_cpu_has(X86_FEATURE_HYPERVISOR); | |
1392 | #else | |
1393 | return false; | |
1394 | #endif | |
1395 | } | |
1396 | ||
d38ceaf9 AD |
1397 | /** |
1398 | * amdgpu_device_init - initialize the driver | |
1399 | * | |
1400 | * @adev: amdgpu_device pointer | |
1401 | * @pdev: drm dev pointer | |
1402 | * @pdev: pci dev pointer | |
1403 | * @flags: driver flags | |
1404 | * | |
1405 | * Initializes the driver info and hw (all asics). | |
1406 | * Returns 0 for success or an error on failure. | |
1407 | * Called at driver startup. | |
1408 | */ | |
1409 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1410 | struct drm_device *ddev, | |
1411 | struct pci_dev *pdev, | |
1412 | uint32_t flags) | |
1413 | { | |
1414 | int r, i; | |
1415 | bool runtime = false; | |
1416 | ||
1417 | adev->shutdown = false; | |
1418 | adev->dev = &pdev->dev; | |
1419 | adev->ddev = ddev; | |
1420 | adev->pdev = pdev; | |
1421 | adev->flags = flags; | |
2f7d10b3 | 1422 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1423 | adev->is_atom_bios = false; |
1424 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1425 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1426 | adev->accel_working = false; | |
1427 | adev->num_rings = 0; | |
1428 | adev->mman.buffer_funcs = NULL; | |
1429 | adev->mman.buffer_funcs_ring = NULL; | |
1430 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1431 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 AD |
1432 | adev->gart.gart_funcs = NULL; |
1433 | adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); | |
1434 | ||
1435 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1436 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1437 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1438 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
1439 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; | |
1440 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1441 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1442 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
1443 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; | |
1444 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1445 | ||
3e39ab90 AD |
1446 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1447 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1448 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1449 | |
1450 | /* mutex initialization are all done here so we | |
1451 | * can recall function without having locking issues */ | |
8d0a7cea | 1452 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1453 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1454 | mutex_init(&adev->pm.mutex); |
1455 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1456 | mutex_init(&adev->srbm_mutex); | |
1457 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1458 | mutex_init(&adev->mn_lock); |
1459 | hash_init(adev->mn_hash); | |
1460 | ||
1461 | amdgpu_check_arguments(adev); | |
1462 | ||
1463 | /* Registers mapping */ | |
1464 | /* TODO: block userspace mapping of io register */ | |
1465 | spin_lock_init(&adev->mmio_idx_lock); | |
1466 | spin_lock_init(&adev->smc_idx_lock); | |
1467 | spin_lock_init(&adev->pcie_idx_lock); | |
1468 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1469 | spin_lock_init(&adev->didt_idx_lock); | |
1470 | spin_lock_init(&adev->audio_endpt_idx_lock); | |
1471 | ||
1472 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1473 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1474 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); | |
1475 | if (adev->rmmio == NULL) { | |
1476 | return -ENOMEM; | |
1477 | } | |
1478 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1479 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1480 | ||
1481 | /* doorbell bar mapping */ | |
1482 | amdgpu_doorbell_init(adev); | |
1483 | ||
1484 | /* io port mapping */ | |
1485 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1486 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1487 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1488 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1489 | break; | |
1490 | } | |
1491 | } | |
1492 | if (adev->rio_mem == NULL) | |
1493 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1494 | ||
1495 | /* early init functions */ | |
1496 | r = amdgpu_early_init(adev); | |
1497 | if (r) | |
1498 | return r; | |
1499 | ||
1500 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1501 | /* this will fail for cards that aren't VGA class devices, just | |
1502 | * ignore it */ | |
1503 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1504 | ||
1505 | if (amdgpu_runtime_pm == 1) | |
1506 | runtime = true; | |
e9bef455 | 1507 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1508 | runtime = true; |
1509 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1510 | if (runtime) | |
1511 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1512 | ||
1513 | /* Read BIOS */ | |
1514 | if (!amdgpu_get_bios(adev)) | |
1515 | return -EINVAL; | |
1516 | /* Must be an ATOMBIOS */ | |
1517 | if (!adev->is_atom_bios) { | |
1518 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
1519 | return -EINVAL; | |
1520 | } | |
1521 | r = amdgpu_atombios_init(adev); | |
2c1a2784 AD |
1522 | if (r) { |
1523 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
d38ceaf9 | 1524 | return r; |
2c1a2784 | 1525 | } |
d38ceaf9 | 1526 | |
7e471e6f AD |
1527 | /* See if the asic supports SR-IOV */ |
1528 | adev->virtualization.supports_sr_iov = | |
1529 | amdgpu_atombios_has_gpu_virtualization_table(adev); | |
1530 | ||
048765ad AR |
1531 | /* Check if we are executing in a virtualized environment */ |
1532 | adev->virtualization.is_virtual = amdgpu_device_is_virtual(); | |
1533 | adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev); | |
1534 | ||
d38ceaf9 | 1535 | /* Post card if necessary */ |
048765ad AR |
1536 | if (!amdgpu_card_posted(adev) || |
1537 | (adev->virtualization.is_virtual && | |
48a70e1c | 1538 | !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) { |
d38ceaf9 AD |
1539 | if (!adev->bios) { |
1540 | dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); | |
1541 | return -EINVAL; | |
1542 | } | |
1543 | DRM_INFO("GPU not posted. posting now...\n"); | |
1544 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1545 | } | |
1546 | ||
1547 | /* Initialize clocks */ | |
1548 | r = amdgpu_atombios_get_clock_info(adev); | |
2c1a2784 AD |
1549 | if (r) { |
1550 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
d38ceaf9 | 1551 | return r; |
2c1a2784 | 1552 | } |
d38ceaf9 AD |
1553 | /* init i2c buses */ |
1554 | amdgpu_atombios_i2c_init(adev); | |
1555 | ||
1556 | /* Fence driver */ | |
1557 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1558 | if (r) { |
1559 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
d38ceaf9 | 1560 | return r; |
2c1a2784 | 1561 | } |
d38ceaf9 AD |
1562 | |
1563 | /* init the mode config */ | |
1564 | drm_mode_config_init(adev->ddev); | |
1565 | ||
1566 | r = amdgpu_init(adev); | |
1567 | if (r) { | |
2c1a2784 | 1568 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 AD |
1569 | amdgpu_fini(adev); |
1570 | return r; | |
1571 | } | |
1572 | ||
1573 | adev->accel_working = true; | |
1574 | ||
1575 | amdgpu_fbdev_init(adev); | |
1576 | ||
1577 | r = amdgpu_ib_pool_init(adev); | |
1578 | if (r) { | |
1579 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
1580 | return r; | |
1581 | } | |
1582 | ||
1583 | r = amdgpu_ib_ring_tests(adev); | |
1584 | if (r) | |
1585 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1586 | ||
1587 | r = amdgpu_gem_debugfs_init(adev); | |
1588 | if (r) { | |
1589 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1590 | } | |
1591 | ||
1592 | r = amdgpu_debugfs_regs_init(adev); | |
1593 | if (r) { | |
1594 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1595 | } | |
1596 | ||
1597 | if ((amdgpu_testing & 1)) { | |
1598 | if (adev->accel_working) | |
1599 | amdgpu_test_moves(adev); | |
1600 | else | |
1601 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1602 | } | |
1603 | if ((amdgpu_testing & 2)) { | |
1604 | if (adev->accel_working) | |
1605 | amdgpu_test_syncing(adev); | |
1606 | else | |
1607 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1608 | } | |
1609 | if (amdgpu_benchmarking) { | |
1610 | if (adev->accel_working) | |
1611 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1612 | else | |
1613 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1614 | } | |
1615 | ||
1616 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1617 | * explicit gating rather than handling it automatically. | |
1618 | */ | |
1619 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
1620 | if (r) { |
1621 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
d38ceaf9 | 1622 | return r; |
2c1a2784 | 1623 | } |
d38ceaf9 AD |
1624 | |
1625 | return 0; | |
1626 | } | |
1627 | ||
1628 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1629 | ||
1630 | /** | |
1631 | * amdgpu_device_fini - tear down the driver | |
1632 | * | |
1633 | * @adev: amdgpu_device pointer | |
1634 | * | |
1635 | * Tear down the driver info (all asics). | |
1636 | * Called at driver shutdown. | |
1637 | */ | |
1638 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1639 | { | |
1640 | int r; | |
1641 | ||
1642 | DRM_INFO("amdgpu: finishing device.\n"); | |
1643 | adev->shutdown = true; | |
1644 | /* evict vram memory */ | |
1645 | amdgpu_bo_evict_vram(adev); | |
1646 | amdgpu_ib_pool_fini(adev); | |
1647 | amdgpu_fence_driver_fini(adev); | |
1648 | amdgpu_fbdev_fini(adev); | |
1649 | r = amdgpu_fini(adev); | |
8faf0e08 AD |
1650 | kfree(adev->ip_block_status); |
1651 | adev->ip_block_status = NULL; | |
d38ceaf9 AD |
1652 | adev->accel_working = false; |
1653 | /* free i2c buses */ | |
1654 | amdgpu_i2c_fini(adev); | |
1655 | amdgpu_atombios_fini(adev); | |
1656 | kfree(adev->bios); | |
1657 | adev->bios = NULL; | |
1658 | vga_switcheroo_unregister_client(adev->pdev); | |
1659 | vga_client_register(adev->pdev, NULL, NULL, NULL); | |
1660 | if (adev->rio_mem) | |
1661 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1662 | adev->rio_mem = NULL; | |
1663 | iounmap(adev->rmmio); | |
1664 | adev->rmmio = NULL; | |
1665 | amdgpu_doorbell_fini(adev); | |
1666 | amdgpu_debugfs_regs_cleanup(adev); | |
1667 | amdgpu_debugfs_remove_files(adev); | |
1668 | } | |
1669 | ||
1670 | ||
1671 | /* | |
1672 | * Suspend & resume. | |
1673 | */ | |
1674 | /** | |
1675 | * amdgpu_suspend_kms - initiate device suspend | |
1676 | * | |
1677 | * @pdev: drm dev pointer | |
1678 | * @state: suspend state | |
1679 | * | |
1680 | * Puts the hw in the suspend state (all asics). | |
1681 | * Returns 0 for success or an error on failure. | |
1682 | * Called at driver suspend. | |
1683 | */ | |
1684 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) | |
1685 | { | |
1686 | struct amdgpu_device *adev; | |
1687 | struct drm_crtc *crtc; | |
1688 | struct drm_connector *connector; | |
5ceb54c6 | 1689 | int r; |
d38ceaf9 AD |
1690 | |
1691 | if (dev == NULL || dev->dev_private == NULL) { | |
1692 | return -ENODEV; | |
1693 | } | |
1694 | ||
1695 | adev = dev->dev_private; | |
1696 | ||
1697 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1698 | return 0; | |
1699 | ||
1700 | drm_kms_helper_poll_disable(dev); | |
1701 | ||
1702 | /* turn off display hw */ | |
4c7fbc39 | 1703 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1704 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1705 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1706 | } | |
4c7fbc39 | 1707 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 1708 | |
756e6880 | 1709 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 1710 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 1711 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
1712 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
1713 | struct amdgpu_bo *robj; | |
1714 | ||
756e6880 AD |
1715 | if (amdgpu_crtc->cursor_bo) { |
1716 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1717 | r = amdgpu_bo_reserve(aobj, false); | |
1718 | if (r == 0) { | |
1719 | amdgpu_bo_unpin(aobj); | |
1720 | amdgpu_bo_unreserve(aobj); | |
1721 | } | |
1722 | } | |
1723 | ||
d38ceaf9 AD |
1724 | if (rfb == NULL || rfb->obj == NULL) { |
1725 | continue; | |
1726 | } | |
1727 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1728 | /* don't unpin kernel fb objects */ | |
1729 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1730 | r = amdgpu_bo_reserve(robj, false); | |
1731 | if (r == 0) { | |
1732 | amdgpu_bo_unpin(robj); | |
1733 | amdgpu_bo_unreserve(robj); | |
1734 | } | |
1735 | } | |
1736 | } | |
1737 | /* evict vram memory */ | |
1738 | amdgpu_bo_evict_vram(adev); | |
1739 | ||
5ceb54c6 | 1740 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
1741 | |
1742 | r = amdgpu_suspend(adev); | |
1743 | ||
1744 | /* evict remaining vram memory */ | |
1745 | amdgpu_bo_evict_vram(adev); | |
1746 | ||
1747 | pci_save_state(dev->pdev); | |
1748 | if (suspend) { | |
1749 | /* Shut down the device */ | |
1750 | pci_disable_device(dev->pdev); | |
1751 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
1752 | } | |
1753 | ||
1754 | if (fbcon) { | |
1755 | console_lock(); | |
1756 | amdgpu_fbdev_set_suspend(adev, 1); | |
1757 | console_unlock(); | |
1758 | } | |
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | /** | |
1763 | * amdgpu_resume_kms - initiate device resume | |
1764 | * | |
1765 | * @pdev: drm dev pointer | |
1766 | * | |
1767 | * Bring the hw back to operating state (all asics). | |
1768 | * Returns 0 for success or an error on failure. | |
1769 | * Called at driver resume. | |
1770 | */ | |
1771 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) | |
1772 | { | |
1773 | struct drm_connector *connector; | |
1774 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 1775 | struct drm_crtc *crtc; |
d38ceaf9 AD |
1776 | int r; |
1777 | ||
1778 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1779 | return 0; | |
1780 | ||
1781 | if (fbcon) { | |
1782 | console_lock(); | |
1783 | } | |
1784 | if (resume) { | |
1785 | pci_set_power_state(dev->pdev, PCI_D0); | |
1786 | pci_restore_state(dev->pdev); | |
1787 | if (pci_enable_device(dev->pdev)) { | |
1788 | if (fbcon) | |
1789 | console_unlock(); | |
1790 | return -1; | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | /* post card */ | |
ca198528 FC |
1795 | if (!amdgpu_card_posted(adev)) |
1796 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
d38ceaf9 AD |
1797 | |
1798 | r = amdgpu_resume(adev); | |
ca198528 FC |
1799 | if (r) |
1800 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 1801 | |
5ceb54c6 AD |
1802 | amdgpu_fence_driver_resume(adev); |
1803 | ||
ca198528 FC |
1804 | if (resume) { |
1805 | r = amdgpu_ib_ring_tests(adev); | |
1806 | if (r) | |
1807 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1808 | } | |
d38ceaf9 AD |
1809 | |
1810 | r = amdgpu_late_init(adev); | |
1811 | if (r) | |
1812 | return r; | |
1813 | ||
756e6880 AD |
1814 | /* pin cursors */ |
1815 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1816 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
1817 | ||
1818 | if (amdgpu_crtc->cursor_bo) { | |
1819 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1820 | r = amdgpu_bo_reserve(aobj, false); | |
1821 | if (r == 0) { | |
1822 | r = amdgpu_bo_pin(aobj, | |
1823 | AMDGPU_GEM_DOMAIN_VRAM, | |
1824 | &amdgpu_crtc->cursor_addr); | |
1825 | if (r != 0) | |
1826 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
1827 | amdgpu_bo_unreserve(aobj); | |
1828 | } | |
1829 | } | |
1830 | } | |
1831 | ||
d38ceaf9 AD |
1832 | /* blat the mode back in */ |
1833 | if (fbcon) { | |
1834 | drm_helper_resume_force_mode(dev); | |
1835 | /* turn on display hw */ | |
4c7fbc39 | 1836 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1837 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1838 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
1839 | } | |
4c7fbc39 | 1840 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
1841 | } |
1842 | ||
1843 | drm_kms_helper_poll_enable(dev); | |
54fb2a5c | 1844 | drm_helper_hpd_irq_event(dev); |
d38ceaf9 AD |
1845 | |
1846 | if (fbcon) { | |
1847 | amdgpu_fbdev_set_suspend(adev, 0); | |
1848 | console_unlock(); | |
1849 | } | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
1854 | /** | |
1855 | * amdgpu_gpu_reset - reset the asic | |
1856 | * | |
1857 | * @adev: amdgpu device pointer | |
1858 | * | |
1859 | * Attempt the reset the GPU if it has hung (all asics). | |
1860 | * Returns 0 for success or an error on failure. | |
1861 | */ | |
1862 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
1863 | { | |
1864 | unsigned ring_sizes[AMDGPU_MAX_RINGS]; | |
1865 | uint32_t *ring_data[AMDGPU_MAX_RINGS]; | |
1866 | ||
1867 | bool saved = false; | |
1868 | ||
1869 | int i, r; | |
1870 | int resched; | |
1871 | ||
d94aed5a | 1872 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 AD |
1873 | |
1874 | /* block TTM */ | |
1875 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
1876 | ||
1877 | r = amdgpu_suspend(adev); | |
1878 | ||
1879 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1880 | struct amdgpu_ring *ring = adev->rings[i]; | |
1881 | if (!ring) | |
1882 | continue; | |
1883 | ||
1884 | ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]); | |
1885 | if (ring_sizes[i]) { | |
1886 | saved = true; | |
1887 | dev_info(adev->dev, "Saved %d dwords of commands " | |
1888 | "on ring %d.\n", ring_sizes[i], i); | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | retry: | |
1893 | r = amdgpu_asic_reset(adev); | |
bfa99269 AD |
1894 | /* post card */ |
1895 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1896 | ||
d38ceaf9 AD |
1897 | if (!r) { |
1898 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
1899 | r = amdgpu_resume(adev); | |
1900 | } | |
1901 | ||
1902 | if (!r) { | |
1903 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1904 | struct amdgpu_ring *ring = adev->rings[i]; | |
1905 | if (!ring) | |
1906 | continue; | |
1907 | ||
1908 | amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]); | |
1909 | ring_sizes[i] = 0; | |
1910 | ring_data[i] = NULL; | |
1911 | } | |
1912 | ||
1913 | r = amdgpu_ib_ring_tests(adev); | |
1914 | if (r) { | |
1915 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
1916 | if (saved) { | |
1917 | saved = false; | |
1918 | r = amdgpu_suspend(adev); | |
1919 | goto retry; | |
1920 | } | |
1921 | } | |
1922 | } else { | |
1923 | amdgpu_fence_driver_force_completion(adev); | |
1924 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1925 | if (adev->rings[i]) | |
1926 | kfree(ring_data[i]); | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | drm_helper_resume_force_mode(adev->ddev); | |
1931 | ||
1932 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
1933 | if (r) { | |
1934 | /* bad news, how to tell it to userspace ? */ | |
1935 | dev_info(adev->dev, "GPU reset failed\n"); | |
1936 | } | |
1937 | ||
d38ceaf9 AD |
1938 | return r; |
1939 | } | |
1940 | ||
cd474ba0 AD |
1941 | #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */ |
1942 | #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */ | |
1943 | ||
d0dd7f0c AD |
1944 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
1945 | { | |
1946 | u32 mask; | |
1947 | int ret; | |
1948 | ||
cd474ba0 AD |
1949 | if (amdgpu_pcie_gen_cap) |
1950 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 1951 | |
cd474ba0 AD |
1952 | if (amdgpu_pcie_lane_cap) |
1953 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 1954 | |
cd474ba0 AD |
1955 | /* covers APUs as well */ |
1956 | if (pci_is_root_bus(adev->pdev->bus)) { | |
1957 | if (adev->pm.pcie_gen_mask == 0) | |
1958 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
1959 | if (adev->pm.pcie_mlw_mask == 0) | |
1960 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 1961 | return; |
cd474ba0 | 1962 | } |
d0dd7f0c | 1963 | |
cd474ba0 AD |
1964 | if (adev->pm.pcie_gen_mask == 0) { |
1965 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
1966 | if (!ret) { | |
1967 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
1968 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
1969 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
1970 | ||
1971 | if (mask & DRM_PCIE_SPEED_25) | |
1972 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
1973 | if (mask & DRM_PCIE_SPEED_50) | |
1974 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
1975 | if (mask & DRM_PCIE_SPEED_80) | |
1976 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
1977 | } else { | |
1978 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
1979 | } | |
1980 | } | |
1981 | if (adev->pm.pcie_mlw_mask == 0) { | |
1982 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
1983 | if (!ret) { | |
1984 | switch (mask) { | |
1985 | case 32: | |
1986 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
1987 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
1988 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
1989 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
1990 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
1991 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
1992 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
1993 | break; | |
1994 | case 16: | |
1995 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
1996 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
1997 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
1998 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
1999 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2000 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2001 | break; | |
2002 | case 12: | |
2003 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2004 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2005 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2006 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2007 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2008 | break; | |
2009 | case 8: | |
2010 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2011 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2012 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2013 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2014 | break; | |
2015 | case 4: | |
2016 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2017 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2018 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2019 | break; | |
2020 | case 2: | |
2021 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2022 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2023 | break; | |
2024 | case 1: | |
2025 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2026 | break; | |
2027 | default: | |
2028 | break; | |
2029 | } | |
2030 | } else { | |
2031 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2032 | } |
2033 | } | |
2034 | } | |
d38ceaf9 AD |
2035 | |
2036 | /* | |
2037 | * Debugfs | |
2038 | */ | |
2039 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2040 | const struct drm_info_list *files, |
d38ceaf9 AD |
2041 | unsigned nfiles) |
2042 | { | |
2043 | unsigned i; | |
2044 | ||
2045 | for (i = 0; i < adev->debugfs_count; i++) { | |
2046 | if (adev->debugfs[i].files == files) { | |
2047 | /* Already registered */ | |
2048 | return 0; | |
2049 | } | |
2050 | } | |
2051 | ||
2052 | i = adev->debugfs_count + 1; | |
2053 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2054 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2055 | DRM_ERROR("Report so we increase " | |
2056 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2057 | return -EINVAL; | |
2058 | } | |
2059 | adev->debugfs[adev->debugfs_count].files = files; | |
2060 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2061 | adev->debugfs_count = i; | |
2062 | #if defined(CONFIG_DEBUG_FS) | |
2063 | drm_debugfs_create_files(files, nfiles, | |
2064 | adev->ddev->control->debugfs_root, | |
2065 | adev->ddev->control); | |
2066 | drm_debugfs_create_files(files, nfiles, | |
2067 | adev->ddev->primary->debugfs_root, | |
2068 | adev->ddev->primary); | |
2069 | #endif | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
2074 | { | |
2075 | #if defined(CONFIG_DEBUG_FS) | |
2076 | unsigned i; | |
2077 | ||
2078 | for (i = 0; i < adev->debugfs_count; i++) { | |
2079 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2080 | adev->debugfs[i].num_files, | |
2081 | adev->ddev->control); | |
2082 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2083 | adev->debugfs[i].num_files, | |
2084 | adev->ddev->primary); | |
2085 | } | |
2086 | #endif | |
2087 | } | |
2088 | ||
2089 | #if defined(CONFIG_DEBUG_FS) | |
2090 | ||
2091 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2092 | size_t size, loff_t *pos) | |
2093 | { | |
2094 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2095 | ssize_t result = 0; | |
2096 | int r; | |
2097 | ||
2098 | if (size & 0x3 || *pos & 0x3) | |
2099 | return -EINVAL; | |
2100 | ||
2101 | while (size) { | |
2102 | uint32_t value; | |
2103 | ||
2104 | if (*pos > adev->rmmio_size) | |
2105 | return result; | |
2106 | ||
2107 | value = RREG32(*pos >> 2); | |
2108 | r = put_user(value, (uint32_t *)buf); | |
2109 | if (r) | |
2110 | return r; | |
2111 | ||
2112 | result += 4; | |
2113 | buf += 4; | |
2114 | *pos += 4; | |
2115 | size -= 4; | |
2116 | } | |
2117 | ||
2118 | return result; | |
2119 | } | |
2120 | ||
2121 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2122 | size_t size, loff_t *pos) | |
2123 | { | |
2124 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2125 | ssize_t result = 0; | |
2126 | int r; | |
2127 | ||
2128 | if (size & 0x3 || *pos & 0x3) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | while (size) { | |
2132 | uint32_t value; | |
2133 | ||
2134 | if (*pos > adev->rmmio_size) | |
2135 | return result; | |
2136 | ||
2137 | r = get_user(value, (uint32_t *)buf); | |
2138 | if (r) | |
2139 | return r; | |
2140 | ||
2141 | WREG32(*pos >> 2, value); | |
2142 | ||
2143 | result += 4; | |
2144 | buf += 4; | |
2145 | *pos += 4; | |
2146 | size -= 4; | |
2147 | } | |
2148 | ||
2149 | return result; | |
2150 | } | |
2151 | ||
adcec288 TSD |
2152 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2153 | size_t size, loff_t *pos) | |
2154 | { | |
2155 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2156 | ssize_t result = 0; | |
2157 | int r; | |
2158 | ||
2159 | if (size & 0x3 || *pos & 0x3) | |
2160 | return -EINVAL; | |
2161 | ||
2162 | while (size) { | |
2163 | uint32_t value; | |
2164 | ||
2165 | value = RREG32_PCIE(*pos >> 2); | |
2166 | r = put_user(value, (uint32_t *)buf); | |
2167 | if (r) | |
2168 | return r; | |
2169 | ||
2170 | result += 4; | |
2171 | buf += 4; | |
2172 | *pos += 4; | |
2173 | size -= 4; | |
2174 | } | |
2175 | ||
2176 | return result; | |
2177 | } | |
2178 | ||
2179 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2180 | size_t size, loff_t *pos) | |
2181 | { | |
2182 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2183 | ssize_t result = 0; | |
2184 | int r; | |
2185 | ||
2186 | if (size & 0x3 || *pos & 0x3) | |
2187 | return -EINVAL; | |
2188 | ||
2189 | while (size) { | |
2190 | uint32_t value; | |
2191 | ||
2192 | r = get_user(value, (uint32_t *)buf); | |
2193 | if (r) | |
2194 | return r; | |
2195 | ||
2196 | WREG32_PCIE(*pos >> 2, value); | |
2197 | ||
2198 | result += 4; | |
2199 | buf += 4; | |
2200 | *pos += 4; | |
2201 | size -= 4; | |
2202 | } | |
2203 | ||
2204 | return result; | |
2205 | } | |
2206 | ||
2207 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
2208 | size_t size, loff_t *pos) | |
2209 | { | |
2210 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2211 | ssize_t result = 0; | |
2212 | int r; | |
2213 | ||
2214 | if (size & 0x3 || *pos & 0x3) | |
2215 | return -EINVAL; | |
2216 | ||
2217 | while (size) { | |
2218 | uint32_t value; | |
2219 | ||
2220 | value = RREG32_DIDT(*pos >> 2); | |
2221 | r = put_user(value, (uint32_t *)buf); | |
2222 | if (r) | |
2223 | return r; | |
2224 | ||
2225 | result += 4; | |
2226 | buf += 4; | |
2227 | *pos += 4; | |
2228 | size -= 4; | |
2229 | } | |
2230 | ||
2231 | return result; | |
2232 | } | |
2233 | ||
2234 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
2235 | size_t size, loff_t *pos) | |
2236 | { | |
2237 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2238 | ssize_t result = 0; | |
2239 | int r; | |
2240 | ||
2241 | if (size & 0x3 || *pos & 0x3) | |
2242 | return -EINVAL; | |
2243 | ||
2244 | while (size) { | |
2245 | uint32_t value; | |
2246 | ||
2247 | r = get_user(value, (uint32_t *)buf); | |
2248 | if (r) | |
2249 | return r; | |
2250 | ||
2251 | WREG32_DIDT(*pos >> 2, value); | |
2252 | ||
2253 | result += 4; | |
2254 | buf += 4; | |
2255 | *pos += 4; | |
2256 | size -= 4; | |
2257 | } | |
2258 | ||
2259 | return result; | |
2260 | } | |
2261 | ||
2262 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
2263 | size_t size, loff_t *pos) | |
2264 | { | |
2265 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2266 | ssize_t result = 0; | |
2267 | int r; | |
2268 | ||
2269 | if (size & 0x3 || *pos & 0x3) | |
2270 | return -EINVAL; | |
2271 | ||
2272 | while (size) { | |
2273 | uint32_t value; | |
2274 | ||
2275 | value = RREG32_SMC(*pos >> 2); | |
2276 | r = put_user(value, (uint32_t *)buf); | |
2277 | if (r) | |
2278 | return r; | |
2279 | ||
2280 | result += 4; | |
2281 | buf += 4; | |
2282 | *pos += 4; | |
2283 | size -= 4; | |
2284 | } | |
2285 | ||
2286 | return result; | |
2287 | } | |
2288 | ||
2289 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
2290 | size_t size, loff_t *pos) | |
2291 | { | |
2292 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2293 | ssize_t result = 0; | |
2294 | int r; | |
2295 | ||
2296 | if (size & 0x3 || *pos & 0x3) | |
2297 | return -EINVAL; | |
2298 | ||
2299 | while (size) { | |
2300 | uint32_t value; | |
2301 | ||
2302 | r = get_user(value, (uint32_t *)buf); | |
2303 | if (r) | |
2304 | return r; | |
2305 | ||
2306 | WREG32_SMC(*pos >> 2, value); | |
2307 | ||
2308 | result += 4; | |
2309 | buf += 4; | |
2310 | *pos += 4; | |
2311 | size -= 4; | |
2312 | } | |
2313 | ||
2314 | return result; | |
2315 | } | |
2316 | ||
d38ceaf9 AD |
2317 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
2318 | .owner = THIS_MODULE, | |
2319 | .read = amdgpu_debugfs_regs_read, | |
2320 | .write = amdgpu_debugfs_regs_write, | |
2321 | .llseek = default_llseek | |
2322 | }; | |
adcec288 TSD |
2323 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
2324 | .owner = THIS_MODULE, | |
2325 | .read = amdgpu_debugfs_regs_didt_read, | |
2326 | .write = amdgpu_debugfs_regs_didt_write, | |
2327 | .llseek = default_llseek | |
2328 | }; | |
2329 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
2330 | .owner = THIS_MODULE, | |
2331 | .read = amdgpu_debugfs_regs_pcie_read, | |
2332 | .write = amdgpu_debugfs_regs_pcie_write, | |
2333 | .llseek = default_llseek | |
2334 | }; | |
2335 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
2336 | .owner = THIS_MODULE, | |
2337 | .read = amdgpu_debugfs_regs_smc_read, | |
2338 | .write = amdgpu_debugfs_regs_smc_write, | |
2339 | .llseek = default_llseek | |
2340 | }; | |
2341 | ||
2342 | static const struct file_operations *debugfs_regs[] = { | |
2343 | &amdgpu_debugfs_regs_fops, | |
2344 | &amdgpu_debugfs_regs_didt_fops, | |
2345 | &amdgpu_debugfs_regs_pcie_fops, | |
2346 | &amdgpu_debugfs_regs_smc_fops, | |
2347 | }; | |
2348 | ||
2349 | static const char *debugfs_regs_names[] = { | |
2350 | "amdgpu_regs", | |
2351 | "amdgpu_regs_didt", | |
2352 | "amdgpu_regs_pcie", | |
2353 | "amdgpu_regs_smc", | |
2354 | }; | |
d38ceaf9 AD |
2355 | |
2356 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2357 | { | |
2358 | struct drm_minor *minor = adev->ddev->primary; | |
2359 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
2360 | unsigned i, j; |
2361 | ||
2362 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2363 | ent = debugfs_create_file(debugfs_regs_names[i], | |
2364 | S_IFREG | S_IRUGO, root, | |
2365 | adev, debugfs_regs[i]); | |
2366 | if (IS_ERR(ent)) { | |
2367 | for (j = 0; j < i; j++) { | |
2368 | debugfs_remove(adev->debugfs_regs[i]); | |
2369 | adev->debugfs_regs[i] = NULL; | |
2370 | } | |
2371 | return PTR_ERR(ent); | |
2372 | } | |
d38ceaf9 | 2373 | |
adcec288 TSD |
2374 | if (!i) |
2375 | i_size_write(ent->d_inode, adev->rmmio_size); | |
2376 | adev->debugfs_regs[i] = ent; | |
2377 | } | |
d38ceaf9 AD |
2378 | |
2379 | return 0; | |
2380 | } | |
2381 | ||
2382 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
2383 | { | |
adcec288 TSD |
2384 | unsigned i; |
2385 | ||
2386 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
2387 | if (adev->debugfs_regs[i]) { | |
2388 | debugfs_remove(adev->debugfs_regs[i]); | |
2389 | adev->debugfs_regs[i] = NULL; | |
2390 | } | |
2391 | } | |
d38ceaf9 AD |
2392 | } |
2393 | ||
2394 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
2395 | { | |
2396 | return 0; | |
2397 | } | |
2398 | ||
2399 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
2400 | { | |
2401 | } | |
7cebc728 AK |
2402 | #else |
2403 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
2404 | { | |
2405 | return 0; | |
2406 | } | |
2407 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 2408 | #endif |