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Merge branch 'parisc-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
d38ceaf9
AD		 56 */
57#define KMS_DRIVER_MAJOR 3
d347ce66 58#define KMS_DRIVER_MINOR 3
d38ceaf9
AD		 59#define KMS_DRIVER_PATCHLEVEL 0
60
61int amdgpu_vram_limit = 0;
62int amdgpu_gart_size = -1; /* auto */
63int amdgpu_benchmarking = 0;
64int amdgpu_testing = 0;
65int amdgpu_audio = -1;
66int amdgpu_disp_priority = 0;
67int amdgpu_hw_i2c = 0;
68int amdgpu_pcie_gen2 = -1;
69int amdgpu_msi = -1;
a895c222 70int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 71int amdgpu_dpm = -1;
72int amdgpu_smc_load_fw = 1;
73int amdgpu_aspm = -1;
74int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 75unsigned amdgpu_ip_block_mask = 0xffffffff;
76int amdgpu_bapm = -1;
77int amdgpu_deep_color = 0;
ed885b21 78int amdgpu_vm_size = 64;
d38ceaf9 79int amdgpu_vm_block_size = -1;
d9c13156 80int amdgpu_vm_fault_stop = 0;
b495bd3a 81int amdgpu_vm_debug = 0;
d38ceaf9 82int amdgpu_exp_hw_support = 0;
b70f014d 83int amdgpu_sched_jobs = 32;
4afcb303 84int amdgpu_sched_hw_submission = 2;
e61710c5 85int amdgpu_powerplay = -1;
6bb6b297 86int amdgpu_powercontainment = 1;
cd474ba0
AD		 87unsigned amdgpu_pcie_gen_cap = 0;
88unsigned amdgpu_pcie_lane_cap = 0;
395d1fb9
NH		 89unsigned amdgpu_cg_mask = 0xffffffff;
90unsigned amdgpu_pg_mask = 0xffffffff;
6f8941a2 91char *amdgpu_disable_cu = NULL;
d38ceaf9
AD		 92
93MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
94module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
95
96MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
97module_param_named(gartsize, amdgpu_gart_size, int, 0600);
98
99MODULE_PARM_DESC(benchmark, "Run benchmark");
100module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
101
102MODULE_PARM_DESC(test, "Run tests");
103module_param_named(test, amdgpu_testing, int, 0444);
104
105MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
106module_param_named(audio, amdgpu_audio, int, 0444);
107
108MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
109module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
110
111MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
112module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
113
114MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
115module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
116
117MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
118module_param_named(msi, amdgpu_msi, int, 0444);
119
a895c222 120MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 121module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
122
123MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
124module_param_named(dpm, amdgpu_dpm, int, 0444);
125
126MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
127module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
128
129MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
130module_param_named(aspm, amdgpu_aspm, int, 0444);
131
132MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
133module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
134
d38ceaf9
AD		 135MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
136module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
137
138MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
139module_param_named(bapm, amdgpu_bapm, int, 0444);
140
141MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
142module_param_named(deep_color, amdgpu_deep_color, int, 0444);
143
ed885b21 144MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 145module_param_named(vm_size, amdgpu_vm_size, int, 0444);
146
147MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
148module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
149
d9c13156
CK		 150MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
151module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
152
b495bd3a
CK		 153MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
154module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
155
d38ceaf9
AD		 156MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
157module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
158
b70f014d 159MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 160module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
161
4afcb303
JZ		 162MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
163module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
164
3a74f6f2 165#ifdef CONFIG_DRM_AMD_POWERPLAY
e61710c5 166MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
3a74f6f2 167module_param_named(powerplay, amdgpu_powerplay, int, 0444);
6bb6b297
HR		 168
169MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
170module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
3a74f6f2
JZ		 171#endif
172
cd474ba0
AD		 173MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
174module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
175
176MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
177module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
178
395d1fb9
NH		 179MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
180module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
181
182MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
183module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
184
6f8941a2
NH		 185MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
186module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
187
f498d9ed 188static const struct pci_device_id pciidlist[] = {
89330c39
AD		 189#ifdef CONFIG_DRM_AMDGPU_CIK
190 /* Kaveri */
2f7d10b3
JZ		 191 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
192 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
193 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
194 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
195 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
196 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
197 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
198 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
199 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
200 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
201 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
202 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
203 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
204 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
205 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
206 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
207 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
208 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
209 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
210 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
211 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
212 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 213 /* Bonaire */
2f7d10b3
JZ		 214 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
215 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
216 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
217 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 218 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
219 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
220 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
221 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
222 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
223 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 224 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 225 /* Hawaii */
226 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
227 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
228 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
229 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
230 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
231 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
232 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
233 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
234 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
235 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
236 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
237 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
238 /* Kabini */
2f7d10b3
JZ		 239 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
240 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
241 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
242 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
243 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
244 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
245 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
246 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
247 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
248 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
249 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
250 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
251 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
252 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
253 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
254 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 255 /* mullins */
2f7d10b3
JZ		 256 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
257 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
258 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
259 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
260 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
261 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
262 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
263 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
264 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
265 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
266 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
267 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
268 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
269 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
270 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
271 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 272#endif
1256a8b8 273 /* topaz */
dba280b2
AD		 274 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
275 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
276 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
277 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
278 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 279 /* tonga */
280 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
281 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
282 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 283 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 284 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
285 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 286 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 287 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
288 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 289 /* fiji */
290 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 291 /* carrizo */
2f7d10b3
JZ		 292 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
293 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
294 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
295 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
296 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 297 /* stoney */
298 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 299 /* Polaris11 */
300 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 301 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 302 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 303 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 304 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 305 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 306 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
307 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
308 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 309 /* Polaris10 */
310 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 311 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
312 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
313 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
314 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 315 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 316 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
317 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
318 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
319 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
320 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
d38ceaf9
AD		 321
322 {0, 0, 0}
323};
324
325MODULE_DEVICE_TABLE(pci, pciidlist);
326
327static struct drm_driver kms_driver;
328
329static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
330{
331 struct apertures_struct *ap;
332 bool primary = false;
333
334 ap = alloc_apertures(1);
335 if (!ap)
336 return -ENOMEM;
337
338 ap->ranges[0].base = pci_resource_start(pdev, 0);
339 ap->ranges[0].size = pci_resource_len(pdev, 0);
340
341#ifdef CONFIG_X86
342 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
343#endif
344 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
345 kfree(ap);
346
347 return 0;
348}
349
350static int amdgpu_pci_probe(struct pci_dev *pdev,
351 const struct pci_device_id *ent)
352{
353 unsigned long flags = ent->driver_data;
354 int ret;
355
2f7d10b3 356 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 357 DRM_INFO("This hardware requires experimental hardware support.\n"
358 "See modparam exp_hw_support\n");
359 return -ENODEV;
360 }
361
efb1c658
OG		 362 /*
363 * Initialize amdkfd before starting radeon. If it was not loaded yet,
364 * defer radeon probing
365 */
366 ret = amdgpu_amdkfd_init();
367 if (ret == -EPROBE_DEFER)
368 return ret;
369
d38ceaf9
AD		 370 /* Get rid of things like offb */
371 ret = amdgpu_kick_out_firmware_fb(pdev);
372 if (ret)
373 return ret;
374
375 return drm_get_pci_dev(pdev, ent, &kms_driver);
376}
377
378static void
379amdgpu_pci_remove(struct pci_dev *pdev)
380{
381 struct drm_device *dev = pci_get_drvdata(pdev);
382
383 drm_put_dev(dev);
384}
385
386static int amdgpu_pmops_suspend(struct device *dev)
387{
388 struct pci_dev *pdev = to_pci_dev(dev);
389 struct drm_device *drm_dev = pci_get_drvdata(pdev);
390 return amdgpu_suspend_kms(drm_dev, true, true);
391}
392
393static int amdgpu_pmops_resume(struct device *dev)
394{
395 struct pci_dev *pdev = to_pci_dev(dev);
396 struct drm_device *drm_dev = pci_get_drvdata(pdev);
397 return amdgpu_resume_kms(drm_dev, true, true);
398}
399
400static int amdgpu_pmops_freeze(struct device *dev)
401{
402 struct pci_dev *pdev = to_pci_dev(dev);
403 struct drm_device *drm_dev = pci_get_drvdata(pdev);
404 return amdgpu_suspend_kms(drm_dev, false, true);
405}
406
407static int amdgpu_pmops_thaw(struct device *dev)
408{
409 struct pci_dev *pdev = to_pci_dev(dev);
410 struct drm_device *drm_dev = pci_get_drvdata(pdev);
411 return amdgpu_resume_kms(drm_dev, false, true);
412}
413
414static int amdgpu_pmops_runtime_suspend(struct device *dev)
415{
416 struct pci_dev *pdev = to_pci_dev(dev);
417 struct drm_device *drm_dev = pci_get_drvdata(pdev);
418 int ret;
419
420 if (!amdgpu_device_is_px(drm_dev)) {
421 pm_runtime_forbid(dev);
422 return -EBUSY;
423 }
424
425 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
426 drm_kms_helper_poll_disable(drm_dev);
427 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
428
429 ret = amdgpu_suspend_kms(drm_dev, false, false);
430 pci_save_state(pdev);
431 pci_disable_device(pdev);
432 pci_ignore_hotplug(pdev);
11670975
AD		 433 if (amdgpu_is_atpx_hybrid())
434 pci_set_power_state(pdev, PCI_D3cold);
522761cb 435 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 436 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 437 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
438
439 return 0;
440}
441
442static int amdgpu_pmops_runtime_resume(struct device *dev)
443{
444 struct pci_dev *pdev = to_pci_dev(dev);
445 struct drm_device *drm_dev = pci_get_drvdata(pdev);
446 int ret;
447
448 if (!amdgpu_device_is_px(drm_dev))
449 return -EINVAL;
450
451 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
452
522761cb
AD		 453 if (amdgpu_is_atpx_hybrid() ||
454 !amdgpu_has_atpx_dgpu_power_cntl())
455 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 456 pci_restore_state(pdev);
457 ret = pci_enable_device(pdev);
458 if (ret)
459 return ret;
460 pci_set_master(pdev);
461
462 ret = amdgpu_resume_kms(drm_dev, false, false);
463 drm_kms_helper_poll_enable(drm_dev);
464 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
465 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
466 return 0;
467}
468
469static int amdgpu_pmops_runtime_idle(struct device *dev)
470{
471 struct pci_dev *pdev = to_pci_dev(dev);
472 struct drm_device *drm_dev = pci_get_drvdata(pdev);
473 struct drm_crtc *crtc;
474
475 if (!amdgpu_device_is_px(drm_dev)) {
476 pm_runtime_forbid(dev);
477 return -EBUSY;
478 }
479
480 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
481 if (crtc->enabled) {
482 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
483 return -EBUSY;
484 }
485 }
486
487 pm_runtime_mark_last_busy(dev);
488 pm_runtime_autosuspend(dev);
489 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
490 return 1;
491}
492
493long amdgpu_drm_ioctl(struct file *filp,
494 unsigned int cmd, unsigned long arg)
495{
496 struct drm_file *file_priv = filp->private_data;
497 struct drm_device *dev;
498 long ret;
499 dev = file_priv->minor->dev;
500 ret = pm_runtime_get_sync(dev->dev);
501 if (ret < 0)
502 return ret;
503
504 ret = drm_ioctl(filp, cmd, arg);
505
506 pm_runtime_mark_last_busy(dev->dev);
507 pm_runtime_put_autosuspend(dev->dev);
508 return ret;
509}
510
511static const struct dev_pm_ops amdgpu_pm_ops = {
512 .suspend = amdgpu_pmops_suspend,
513 .resume = amdgpu_pmops_resume,
514 .freeze = amdgpu_pmops_freeze,
515 .thaw = amdgpu_pmops_thaw,
516 .poweroff = amdgpu_pmops_freeze,
517 .restore = amdgpu_pmops_resume,
518 .runtime_suspend = amdgpu_pmops_runtime_suspend,
519 .runtime_resume = amdgpu_pmops_runtime_resume,
520 .runtime_idle = amdgpu_pmops_runtime_idle,
521};
522
523static const struct file_operations amdgpu_driver_kms_fops = {
524 .owner = THIS_MODULE,
525 .open = drm_open,
526 .release = drm_release,
527 .unlocked_ioctl = amdgpu_drm_ioctl,
528 .mmap = amdgpu_mmap,
529 .poll = drm_poll,
530 .read = drm_read,
531#ifdef CONFIG_COMPAT
532 .compat_ioctl = amdgpu_kms_compat_ioctl,
533#endif
534};
535
536static struct drm_driver kms_driver = {
537 .driver_features =
538 DRIVER_USE_AGP |
539 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
7056bb5c 540 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
d38ceaf9
AD		 541 .dev_priv_size = 0,
542 .load = amdgpu_driver_load_kms,
543 .open = amdgpu_driver_open_kms,
544 .preclose = amdgpu_driver_preclose_kms,
545 .postclose = amdgpu_driver_postclose_kms,
546 .lastclose = amdgpu_driver_lastclose_kms,
547 .set_busid = drm_pci_set_busid,
548 .unload = amdgpu_driver_unload_kms,
549 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
550 .enable_vblank = amdgpu_enable_vblank_kms,
551 .disable_vblank = amdgpu_disable_vblank_kms,
552 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
553 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
554#if defined(CONFIG_DEBUG_FS)
555 .debugfs_init = amdgpu_debugfs_init,
556 .debugfs_cleanup = amdgpu_debugfs_cleanup,
557#endif
558 .irq_preinstall = amdgpu_irq_preinstall,
559 .irq_postinstall = amdgpu_irq_postinstall,
560 .irq_uninstall = amdgpu_irq_uninstall,
561 .irq_handler = amdgpu_irq_handler,
562 .ioctls = amdgpu_ioctls_kms,
e7294dee 563 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 564 .gem_open_object = amdgpu_gem_object_open,
565 .gem_close_object = amdgpu_gem_object_close,
566 .dumb_create = amdgpu_mode_dumb_create,
567 .dumb_map_offset = amdgpu_mode_dumb_mmap,
568 .dumb_destroy = drm_gem_dumb_destroy,
569 .fops = &amdgpu_driver_kms_fops,
570
571 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
572 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
573 .gem_prime_export = amdgpu_gem_prime_export,
574 .gem_prime_import = drm_gem_prime_import,
575 .gem_prime_pin = amdgpu_gem_prime_pin,
576 .gem_prime_unpin = amdgpu_gem_prime_unpin,
577 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
578 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
579 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
580 .gem_prime_vmap = amdgpu_gem_prime_vmap,
581 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
582
583 .name = DRIVER_NAME,
584 .desc = DRIVER_DESC,
585 .date = DRIVER_DATE,
586 .major = KMS_DRIVER_MAJOR,
587 .minor = KMS_DRIVER_MINOR,
588 .patchlevel = KMS_DRIVER_PATCHLEVEL,
589};
590
591static struct drm_driver *driver;
592static struct pci_driver *pdriver;
593
594static struct pci_driver amdgpu_kms_pci_driver = {
595 .name = DRIVER_NAME,
596 .id_table = pciidlist,
597 .probe = amdgpu_pci_probe,
598 .remove = amdgpu_pci_remove,
599 .driver.pm = &amdgpu_pm_ops,
600};
601
d573de2d
RZ		 602
603
d38ceaf9
AD		 604static int __init amdgpu_init(void)
605{
257bf15a 606 amdgpu_sync_init();
d573de2d 607 amdgpu_fence_slab_init();
d38ceaf9
AD		 608 if (vgacon_text_force()) {
609 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
610 return -EINVAL;
611 }
d38ceaf9
AD		 612 DRM_INFO("amdgpu kernel modesetting enabled.\n");
613 driver = &kms_driver;
614 pdriver = &amdgpu_kms_pci_driver;
d38ceaf9
AD		 615 driver->num_ioctls = amdgpu_max_kms_ioctl;
616 amdgpu_register_atpx_handler();
d38ceaf9
AD		 617 /* let modprobe override vga console setting */
618 return drm_pci_init(driver, pdriver);
619}
620
621static void __exit amdgpu_exit(void)
622{
130e0371 623 amdgpu_amdkfd_fini();
d38ceaf9
AD		 624 drm_pci_exit(driver, pdriver);
625 amdgpu_unregister_atpx_handler();
257bf15a 626 amdgpu_sync_fini();
d573de2d 627 amdgpu_fence_slab_fini();
d38ceaf9
AD		 628}
629
630module_init(amdgpu_init);
631module_exit(amdgpu_exit);
632
633MODULE_AUTHOR(DRIVER_AUTHOR);
634MODULE_DESCRIPTION(DRIVER_DESC);
635MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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