Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Dave Airlie | |
30 | */ | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/atomic.h> | |
33 | #include <linux/wait.h> | |
34 | #include <linux/kref.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/firmware.h> | |
37 | #include <drm/drmP.h> | |
38 | #include "amdgpu.h" | |
39 | #include "amdgpu_trace.h" | |
40 | ||
41 | /* | |
42 | * Fences | |
43 | * Fences mark an event in the GPUs pipeline and are used | |
44 | * for GPU/CPU synchronization. When the fence is written, | |
45 | * it is expected that all buffers associated with that fence | |
46 | * are no longer in use by the associated ring on the GPU and | |
47 | * that the the relevant GPU caches have been flushed. | |
48 | */ | |
49 | ||
22e5a2f4 CK |
50 | struct amdgpu_fence { |
51 | struct fence base; | |
52 | ||
53 | /* RB, DMA, etc. */ | |
54 | struct amdgpu_ring *ring; | |
55 | uint64_t seq; | |
56 | ||
57 | wait_queue_t fence_wake; | |
58 | }; | |
59 | ||
b49c84a5 CZ |
60 | static struct kmem_cache *amdgpu_fence_slab; |
61 | static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0); | |
62 | ||
22e5a2f4 CK |
63 | /* |
64 | * Cast helper | |
65 | */ | |
66 | static const struct fence_ops amdgpu_fence_ops; | |
67 | static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) | |
68 | { | |
69 | struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); | |
70 | ||
71 | if (__f->base.ops == &amdgpu_fence_ops) | |
72 | return __f; | |
73 | ||
74 | return NULL; | |
75 | } | |
76 | ||
d38ceaf9 AD |
77 | /** |
78 | * amdgpu_fence_write - write a fence value | |
79 | * | |
80 | * @ring: ring the fence is associated with | |
81 | * @seq: sequence number to write | |
82 | * | |
83 | * Writes a fence value to memory (all asics). | |
84 | */ | |
85 | static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) | |
86 | { | |
87 | struct amdgpu_fence_driver *drv = &ring->fence_drv; | |
88 | ||
89 | if (drv->cpu_addr) | |
90 | *drv->cpu_addr = cpu_to_le32(seq); | |
91 | } | |
92 | ||
93 | /** | |
94 | * amdgpu_fence_read - read a fence value | |
95 | * | |
96 | * @ring: ring the fence is associated with | |
97 | * | |
98 | * Reads a fence value from memory (all asics). | |
99 | * Returns the value of the fence read from memory. | |
100 | */ | |
101 | static u32 amdgpu_fence_read(struct amdgpu_ring *ring) | |
102 | { | |
103 | struct amdgpu_fence_driver *drv = &ring->fence_drv; | |
104 | u32 seq = 0; | |
105 | ||
106 | if (drv->cpu_addr) | |
107 | seq = le32_to_cpu(*drv->cpu_addr); | |
108 | else | |
109 | seq = lower_32_bits(atomic64_read(&drv->last_seq)); | |
110 | ||
111 | return seq; | |
112 | } | |
113 | ||
d38ceaf9 AD |
114 | /** |
115 | * amdgpu_fence_emit - emit a fence on the requested ring | |
116 | * | |
117 | * @ring: ring the fence is associated with | |
364beb2c | 118 | * @f: resulting fence object |
d38ceaf9 AD |
119 | * |
120 | * Emits a fence command on the requested ring (all asics). | |
121 | * Returns 0 on success, -ENOMEM on failure. | |
122 | */ | |
364beb2c | 123 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) |
d38ceaf9 AD |
124 | { |
125 | struct amdgpu_device *adev = ring->adev; | |
364beb2c | 126 | struct amdgpu_fence *fence; |
d38ceaf9 | 127 | |
364beb2c CK |
128 | fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); |
129 | if (fence == NULL) | |
d38ceaf9 | 130 | return -ENOMEM; |
364beb2c CK |
131 | |
132 | fence->seq = ++ring->fence_drv.sync_seq; | |
133 | fence->ring = ring; | |
134 | fence_init(&fence->base, &amdgpu_fence_ops, | |
135 | &ring->fence_drv.fence_queue.lock, | |
136 | adev->fence_context + ring->idx, | |
137 | fence->seq); | |
890ee23f | 138 | amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, |
364beb2c CK |
139 | fence->seq, AMDGPU_FENCE_FLAG_INT); |
140 | *f = &fence->base; | |
d38ceaf9 AD |
141 | return 0; |
142 | } | |
143 | ||
c2776afe CK |
144 | /** |
145 | * amdgpu_fence_schedule_fallback - schedule fallback check | |
146 | * | |
147 | * @ring: pointer to struct amdgpu_ring | |
148 | * | |
149 | * Start a timer as fallback to our interrupts. | |
150 | */ | |
151 | static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) | |
152 | { | |
153 | mod_timer(&ring->fence_drv.fallback_timer, | |
154 | jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); | |
155 | } | |
156 | ||
d38ceaf9 | 157 | /** |
ca08e04d | 158 | * amdgpu_fence_process - check for fence activity |
d38ceaf9 AD |
159 | * |
160 | * @ring: pointer to struct amdgpu_ring | |
161 | * | |
162 | * Checks the current fence value and calculates the last | |
ca08e04d CK |
163 | * signalled fence value. Wakes the fence queue if the |
164 | * sequence number has increased. | |
d38ceaf9 | 165 | */ |
ca08e04d | 166 | void amdgpu_fence_process(struct amdgpu_ring *ring) |
d38ceaf9 AD |
167 | { |
168 | uint64_t seq, last_seq, last_emitted; | |
d38ceaf9 AD |
169 | bool wake = false; |
170 | ||
d38ceaf9 AD |
171 | last_seq = atomic64_read(&ring->fence_drv.last_seq); |
172 | do { | |
5907a0d8 | 173 | last_emitted = ring->fence_drv.sync_seq; |
d38ceaf9 AD |
174 | seq = amdgpu_fence_read(ring); |
175 | seq |= last_seq & 0xffffffff00000000LL; | |
176 | if (seq < last_seq) { | |
177 | seq &= 0xffffffff; | |
178 | seq |= last_emitted & 0xffffffff00000000LL; | |
179 | } | |
180 | ||
d9713ef6 | 181 | if (seq <= last_seq || seq > last_emitted) |
d38ceaf9 | 182 | break; |
d9713ef6 | 183 | |
d38ceaf9 AD |
184 | /* If we loop over we don't want to return without |
185 | * checking if a fence is signaled as it means that the | |
186 | * seq we just read is different from the previous on. | |
187 | */ | |
188 | wake = true; | |
189 | last_seq = seq; | |
d9713ef6 | 190 | |
d38ceaf9 AD |
191 | } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); |
192 | ||
193 | if (seq < last_emitted) | |
c2776afe | 194 | amdgpu_fence_schedule_fallback(ring); |
d38ceaf9 | 195 | |
ca08e04d | 196 | if (wake) |
7f06c236 | 197 | wake_up_all(&ring->fence_drv.fence_queue); |
d38ceaf9 AD |
198 | } |
199 | ||
200 | /** | |
c2776afe | 201 | * amdgpu_fence_fallback - fallback for hardware interrupts |
d38ceaf9 | 202 | * |
c2776afe | 203 | * @work: delayed work item |
d38ceaf9 | 204 | * |
c2776afe | 205 | * Checks for fence activity. |
d38ceaf9 | 206 | */ |
c2776afe | 207 | static void amdgpu_fence_fallback(unsigned long arg) |
d38ceaf9 | 208 | { |
c2776afe CK |
209 | struct amdgpu_ring *ring = (void *)arg; |
210 | ||
211 | amdgpu_fence_process(ring); | |
d38ceaf9 AD |
212 | } |
213 | ||
214 | /** | |
215 | * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled | |
216 | * | |
217 | * @ring: ring the fence is associated with | |
218 | * @seq: sequence number | |
219 | * | |
220 | * Check if the last signaled fence sequnce number is >= the requested | |
221 | * sequence number (all asics). | |
222 | * Returns true if the fence has signaled (current fence value | |
223 | * is >= requested value) or false if it has not (current fence | |
224 | * value is < the requested value. Helper function for | |
225 | * amdgpu_fence_signaled(). | |
226 | */ | |
227 | static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq) | |
228 | { | |
229 | if (atomic64_read(&ring->fence_drv.last_seq) >= seq) | |
230 | return true; | |
231 | ||
232 | /* poll new last sequence at least once */ | |
233 | amdgpu_fence_process(ring); | |
234 | if (atomic64_read(&ring->fence_drv.last_seq) >= seq) | |
235 | return true; | |
236 | ||
237 | return false; | |
238 | } | |
239 | ||
7f06c236 | 240 | /* |
9b389668 | 241 | * amdgpu_ring_wait_seq - wait for seq of the specific ring to signal |
7f06c236 | 242 | * @ring: ring to wait on for the seq number |
243 | * @seq: seq number wait for | |
7f06c236 | 244 | * |
245 | * return value: | |
00d2a2b2 | 246 | * 0: seq signaled, and gpu not hang |
7f06c236 | 247 | * -EINVAL: some paramter is not valid |
d38ceaf9 | 248 | */ |
00d2a2b2 | 249 | static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) |
d38ceaf9 | 250 | { |
7f06c236 | 251 | BUG_ON(!ring); |
5907a0d8 | 252 | if (seq > ring->fence_drv.sync_seq) |
7f06c236 | 253 | return -EINVAL; |
d38ceaf9 | 254 | |
7f06c236 | 255 | if (atomic64_read(&ring->fence_drv.last_seq) >= seq) |
00d2a2b2 | 256 | return 0; |
d38ceaf9 | 257 | |
c2776afe | 258 | amdgpu_fence_schedule_fallback(ring); |
9b389668 CK |
259 | wait_event(ring->fence_drv.fence_queue, |
260 | amdgpu_fence_seq_signaled(ring, seq)); | |
d38ceaf9 | 261 | |
9b389668 | 262 | return 0; |
d38ceaf9 AD |
263 | } |
264 | ||
d38ceaf9 AD |
265 | /** |
266 | * amdgpu_fence_wait_empty - wait for all fences to signal | |
267 | * | |
268 | * @adev: amdgpu device pointer | |
269 | * @ring: ring index the fence is associated with | |
270 | * | |
271 | * Wait for all fences on the requested ring to signal (all asics). | |
272 | * Returns 0 if the fences have passed, error for all other cases. | |
273 | * Caller must hold ring lock. | |
274 | */ | |
275 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) | |
276 | { | |
5907a0d8 | 277 | uint64_t seq = ring->fence_drv.sync_seq; |
00d2a2b2 | 278 | |
7f06c236 | 279 | if (!seq) |
d38ceaf9 AD |
280 | return 0; |
281 | ||
00d2a2b2 | 282 | return amdgpu_fence_ring_wait_seq(ring, seq); |
d38ceaf9 AD |
283 | } |
284 | ||
d38ceaf9 AD |
285 | /** |
286 | * amdgpu_fence_count_emitted - get the count of emitted fences | |
287 | * | |
288 | * @ring: ring the fence is associated with | |
289 | * | |
290 | * Get the number of fences emitted on the requested ring (all asics). | |
291 | * Returns the number of emitted fences on the ring. Used by the | |
292 | * dynpm code to ring track activity. | |
293 | */ | |
294 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) | |
295 | { | |
296 | uint64_t emitted; | |
297 | ||
298 | /* We are not protected by ring lock when reading the last sequence | |
299 | * but it's ok to report slightly wrong fence count here. | |
300 | */ | |
301 | amdgpu_fence_process(ring); | |
5907a0d8 | 302 | emitted = ring->fence_drv.sync_seq |
d38ceaf9 AD |
303 | - atomic64_read(&ring->fence_drv.last_seq); |
304 | /* to avoid 32bits warp around */ | |
305 | if (emitted > 0x10000000) | |
306 | emitted = 0x10000000; | |
307 | ||
308 | return (unsigned)emitted; | |
309 | } | |
310 | ||
d38ceaf9 AD |
311 | /** |
312 | * amdgpu_fence_driver_start_ring - make the fence driver | |
313 | * ready for use on the requested ring. | |
314 | * | |
315 | * @ring: ring to start the fence driver on | |
316 | * @irq_src: interrupt source to use for this ring | |
317 | * @irq_type: interrupt type to use for this ring | |
318 | * | |
319 | * Make the fence driver ready for processing (all asics). | |
320 | * Not all asics have all rings, so each asic will only | |
321 | * start the fence driver on the rings it has. | |
322 | * Returns 0 for success, errors for failure. | |
323 | */ | |
324 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, | |
325 | struct amdgpu_irq_src *irq_src, | |
326 | unsigned irq_type) | |
327 | { | |
328 | struct amdgpu_device *adev = ring->adev; | |
329 | uint64_t index; | |
330 | ||
331 | if (ring != &adev->uvd.ring) { | |
332 | ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; | |
333 | ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); | |
334 | } else { | |
335 | /* put fence directly behind firmware */ | |
336 | index = ALIGN(adev->uvd.fw->size, 8); | |
337 | ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; | |
338 | ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; | |
339 | } | |
340 | amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq)); | |
c6a4079b CZ |
341 | amdgpu_irq_get(adev, irq_src, irq_type); |
342 | ||
d38ceaf9 AD |
343 | ring->fence_drv.irq_src = irq_src; |
344 | ring->fence_drv.irq_type = irq_type; | |
c6a4079b CZ |
345 | ring->fence_drv.initialized = true; |
346 | ||
d38ceaf9 AD |
347 | dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " |
348 | "cpu addr 0x%p\n", ring->idx, | |
349 | ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); | |
350 | return 0; | |
351 | } | |
352 | ||
353 | /** | |
354 | * amdgpu_fence_driver_init_ring - init the fence driver | |
355 | * for the requested ring. | |
356 | * | |
357 | * @ring: ring to init the fence driver on | |
e6151a08 | 358 | * @num_hw_submission: number of entries on the hardware queue |
d38ceaf9 AD |
359 | * |
360 | * Init the fence driver for the requested ring (all asics). | |
361 | * Helper function for amdgpu_fence_driver_init(). | |
362 | */ | |
e6151a08 CK |
363 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, |
364 | unsigned num_hw_submission) | |
d38ceaf9 | 365 | { |
cadf97b1 | 366 | long timeout; |
5907a0d8 | 367 | int r; |
d38ceaf9 | 368 | |
e6151a08 CK |
369 | /* Check that num_hw_submission is a power of two */ |
370 | if ((num_hw_submission & (num_hw_submission - 1)) != 0) | |
371 | return -EINVAL; | |
372 | ||
d38ceaf9 AD |
373 | ring->fence_drv.cpu_addr = NULL; |
374 | ring->fence_drv.gpu_addr = 0; | |
5907a0d8 | 375 | ring->fence_drv.sync_seq = 0; |
d38ceaf9 AD |
376 | atomic64_set(&ring->fence_drv.last_seq, 0); |
377 | ring->fence_drv.initialized = false; | |
378 | ||
c2776afe CK |
379 | setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, |
380 | (unsigned long)ring); | |
b80d8475 | 381 | |
5ec92a76 CK |
382 | init_waitqueue_head(&ring->fence_drv.fence_queue); |
383 | ||
cadf97b1 CZ |
384 | timeout = msecs_to_jiffies(amdgpu_lockup_timeout); |
385 | if (timeout == 0) { | |
386 | /* | |
387 | * FIXME: | |
388 | * Delayed workqueue cannot use it directly, | |
389 | * so the scheduler will not use delayed workqueue if | |
390 | * MAX_SCHEDULE_TIMEOUT is set. | |
391 | * Currently keep it simple and silly. | |
392 | */ | |
393 | timeout = MAX_SCHEDULE_TIMEOUT; | |
394 | } | |
395 | r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, | |
e6151a08 | 396 | num_hw_submission, |
cadf97b1 CZ |
397 | timeout, ring->name); |
398 | if (r) { | |
399 | DRM_ERROR("Failed to create scheduler on ring %s.\n", | |
400 | ring->name); | |
401 | return r; | |
b80d8475 | 402 | } |
4f839a24 CK |
403 | |
404 | return 0; | |
d38ceaf9 AD |
405 | } |
406 | ||
407 | /** | |
408 | * amdgpu_fence_driver_init - init the fence driver | |
409 | * for all possible rings. | |
410 | * | |
411 | * @adev: amdgpu device pointer | |
412 | * | |
413 | * Init the fence driver for all possible rings (all asics). | |
414 | * Not all asics have all rings, so each asic will only | |
415 | * start the fence driver on the rings it has using | |
416 | * amdgpu_fence_driver_start_ring(). | |
417 | * Returns 0 for success. | |
418 | */ | |
419 | int amdgpu_fence_driver_init(struct amdgpu_device *adev) | |
420 | { | |
b49c84a5 CZ |
421 | if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) { |
422 | amdgpu_fence_slab = kmem_cache_create( | |
423 | "amdgpu_fence", sizeof(struct amdgpu_fence), 0, | |
424 | SLAB_HWCACHE_ALIGN, NULL); | |
425 | if (!amdgpu_fence_slab) | |
426 | return -ENOMEM; | |
427 | } | |
d38ceaf9 AD |
428 | if (amdgpu_debugfs_fence_init(adev)) |
429 | dev_err(adev->dev, "fence debugfs file creation failed\n"); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_fence_driver_fini - tear down the fence driver | |
436 | * for all possible rings. | |
437 | * | |
438 | * @adev: amdgpu device pointer | |
439 | * | |
440 | * Tear down the fence driver for all possible rings (all asics). | |
441 | */ | |
442 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev) | |
443 | { | |
444 | int i, r; | |
445 | ||
b49c84a5 CZ |
446 | if (atomic_dec_and_test(&amdgpu_fence_slab_ref)) |
447 | kmem_cache_destroy(amdgpu_fence_slab); | |
d38ceaf9 AD |
448 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
449 | struct amdgpu_ring *ring = adev->rings[i]; | |
c2776afe | 450 | |
d38ceaf9 AD |
451 | if (!ring || !ring->fence_drv.initialized) |
452 | continue; | |
453 | r = amdgpu_fence_wait_empty(ring); | |
454 | if (r) { | |
455 | /* no need to trigger GPU reset as we are unloading */ | |
456 | amdgpu_fence_driver_force_completion(adev); | |
457 | } | |
7f06c236 | 458 | wake_up_all(&ring->fence_drv.fence_queue); |
c6a4079b CZ |
459 | amdgpu_irq_put(adev, ring->fence_drv.irq_src, |
460 | ring->fence_drv.irq_type); | |
4f839a24 | 461 | amd_sched_fini(&ring->sched); |
c2776afe | 462 | del_timer_sync(&ring->fence_drv.fallback_timer); |
d38ceaf9 AD |
463 | ring->fence_drv.initialized = false; |
464 | } | |
d38ceaf9 AD |
465 | } |
466 | ||
5ceb54c6 AD |
467 | /** |
468 | * amdgpu_fence_driver_suspend - suspend the fence driver | |
469 | * for all possible rings. | |
470 | * | |
471 | * @adev: amdgpu device pointer | |
472 | * | |
473 | * Suspend the fence driver for all possible rings (all asics). | |
474 | */ | |
475 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) | |
476 | { | |
477 | int i, r; | |
478 | ||
5ceb54c6 AD |
479 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
480 | struct amdgpu_ring *ring = adev->rings[i]; | |
481 | if (!ring || !ring->fence_drv.initialized) | |
482 | continue; | |
483 | ||
484 | /* wait for gpu to finish processing current batch */ | |
485 | r = amdgpu_fence_wait_empty(ring); | |
486 | if (r) { | |
487 | /* delay GPU reset to resume */ | |
488 | amdgpu_fence_driver_force_completion(adev); | |
489 | } | |
490 | ||
491 | /* disable the interrupt */ | |
492 | amdgpu_irq_put(adev, ring->fence_drv.irq_src, | |
493 | ring->fence_drv.irq_type); | |
494 | } | |
5ceb54c6 AD |
495 | } |
496 | ||
497 | /** | |
498 | * amdgpu_fence_driver_resume - resume the fence driver | |
499 | * for all possible rings. | |
500 | * | |
501 | * @adev: amdgpu device pointer | |
502 | * | |
503 | * Resume the fence driver for all possible rings (all asics). | |
504 | * Not all asics have all rings, so each asic will only | |
505 | * start the fence driver on the rings it has using | |
506 | * amdgpu_fence_driver_start_ring(). | |
507 | * Returns 0 for success. | |
508 | */ | |
509 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev) | |
510 | { | |
511 | int i; | |
512 | ||
5ceb54c6 AD |
513 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
514 | struct amdgpu_ring *ring = adev->rings[i]; | |
515 | if (!ring || !ring->fence_drv.initialized) | |
516 | continue; | |
517 | ||
518 | /* enable the interrupt */ | |
519 | amdgpu_irq_get(adev, ring->fence_drv.irq_src, | |
520 | ring->fence_drv.irq_type); | |
521 | } | |
5ceb54c6 AD |
522 | } |
523 | ||
d38ceaf9 AD |
524 | /** |
525 | * amdgpu_fence_driver_force_completion - force all fence waiter to complete | |
526 | * | |
527 | * @adev: amdgpu device pointer | |
528 | * | |
529 | * In case of GPU reset failure make sure no process keep waiting on fence | |
530 | * that will never complete. | |
531 | */ | |
532 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) | |
533 | { | |
534 | int i; | |
535 | ||
536 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
537 | struct amdgpu_ring *ring = adev->rings[i]; | |
538 | if (!ring || !ring->fence_drv.initialized) | |
539 | continue; | |
540 | ||
5907a0d8 | 541 | amdgpu_fence_write(ring, ring->fence_drv.sync_seq); |
d38ceaf9 AD |
542 | } |
543 | } | |
544 | ||
a95e2642 CK |
545 | /* |
546 | * Common fence implementation | |
547 | */ | |
548 | ||
549 | static const char *amdgpu_fence_get_driver_name(struct fence *fence) | |
550 | { | |
551 | return "amdgpu"; | |
552 | } | |
553 | ||
554 | static const char *amdgpu_fence_get_timeline_name(struct fence *f) | |
555 | { | |
556 | struct amdgpu_fence *fence = to_amdgpu_fence(f); | |
557 | return (const char *)fence->ring->name; | |
558 | } | |
559 | ||
560 | /** | |
561 | * amdgpu_fence_is_signaled - test if fence is signaled | |
562 | * | |
563 | * @f: fence to test | |
564 | * | |
565 | * Test the fence sequence number if it is already signaled. If it isn't | |
566 | * signaled start fence processing. Returns True if the fence is signaled. | |
567 | */ | |
568 | static bool amdgpu_fence_is_signaled(struct fence *f) | |
569 | { | |
570 | struct amdgpu_fence *fence = to_amdgpu_fence(f); | |
571 | struct amdgpu_ring *ring = fence->ring; | |
572 | ||
573 | if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) | |
574 | return true; | |
575 | ||
576 | amdgpu_fence_process(ring); | |
577 | ||
578 | if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) | |
579 | return true; | |
580 | ||
581 | return false; | |
582 | } | |
583 | ||
584 | /** | |
585 | * amdgpu_fence_check_signaled - callback from fence_queue | |
586 | * | |
587 | * this function is called with fence_queue lock held, which is also used | |
588 | * for the fence locking itself, so unlocked variants are used for | |
589 | * fence_signal, and remove_wait_queue. | |
590 | */ | |
591 | static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) | |
592 | { | |
593 | struct amdgpu_fence *fence; | |
594 | struct amdgpu_device *adev; | |
595 | u64 seq; | |
596 | int ret; | |
597 | ||
598 | fence = container_of(wait, struct amdgpu_fence, fence_wake); | |
599 | adev = fence->ring->adev; | |
600 | ||
601 | /* | |
602 | * We cannot use amdgpu_fence_process here because we're already | |
603 | * in the waitqueue, in a call from wake_up_all. | |
604 | */ | |
605 | seq = atomic64_read(&fence->ring->fence_drv.last_seq); | |
606 | if (seq >= fence->seq) { | |
607 | ret = fence_signal_locked(&fence->base); | |
608 | if (!ret) | |
609 | FENCE_TRACE(&fence->base, "signaled from irq context\n"); | |
610 | else | |
611 | FENCE_TRACE(&fence->base, "was already signaled\n"); | |
612 | ||
613 | __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake); | |
614 | fence_put(&fence->base); | |
615 | } else | |
616 | FENCE_TRACE(&fence->base, "pending\n"); | |
617 | return 0; | |
618 | } | |
619 | ||
620 | /** | |
621 | * amdgpu_fence_enable_signaling - enable signalling on fence | |
622 | * @fence: fence | |
623 | * | |
624 | * This function is called with fence_queue lock held, and adds a callback | |
625 | * to fence_queue that checks if this fence is signaled, and if so it | |
626 | * signals the fence and removes itself. | |
627 | */ | |
628 | static bool amdgpu_fence_enable_signaling(struct fence *f) | |
629 | { | |
630 | struct amdgpu_fence *fence = to_amdgpu_fence(f); | |
631 | struct amdgpu_ring *ring = fence->ring; | |
632 | ||
633 | if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) | |
634 | return false; | |
635 | ||
636 | fence->fence_wake.flags = 0; | |
637 | fence->fence_wake.private = NULL; | |
638 | fence->fence_wake.func = amdgpu_fence_check_signaled; | |
639 | __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); | |
640 | fence_get(f); | |
c2776afe CK |
641 | if (!timer_pending(&ring->fence_drv.fallback_timer)) |
642 | amdgpu_fence_schedule_fallback(ring); | |
a95e2642 CK |
643 | FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); |
644 | return true; | |
645 | } | |
646 | ||
b4413535 CK |
647 | /** |
648 | * amdgpu_fence_free - free up the fence memory | |
649 | * | |
650 | * @rcu: RCU callback head | |
651 | * | |
652 | * Free up the fence memory after the RCU grace period. | |
653 | */ | |
654 | static void amdgpu_fence_free(struct rcu_head *rcu) | |
b49c84a5 | 655 | { |
b4413535 | 656 | struct fence *f = container_of(rcu, struct fence, rcu); |
b49c84a5 CZ |
657 | struct amdgpu_fence *fence = to_amdgpu_fence(f); |
658 | kmem_cache_free(amdgpu_fence_slab, fence); | |
659 | } | |
660 | ||
b4413535 CK |
661 | /** |
662 | * amdgpu_fence_release - callback that fence can be freed | |
663 | * | |
664 | * @fence: fence | |
665 | * | |
666 | * This function is called when the reference count becomes zero. | |
667 | * It just RCU schedules freeing up the fence. | |
668 | */ | |
669 | static void amdgpu_fence_release(struct fence *f) | |
670 | { | |
671 | call_rcu(&f->rcu, amdgpu_fence_free); | |
672 | } | |
673 | ||
22e5a2f4 | 674 | static const struct fence_ops amdgpu_fence_ops = { |
a95e2642 CK |
675 | .get_driver_name = amdgpu_fence_get_driver_name, |
676 | .get_timeline_name = amdgpu_fence_get_timeline_name, | |
677 | .enable_signaling = amdgpu_fence_enable_signaling, | |
678 | .signaled = amdgpu_fence_is_signaled, | |
679 | .wait = fence_default_wait, | |
b49c84a5 | 680 | .release = amdgpu_fence_release, |
a95e2642 | 681 | }; |
d38ceaf9 AD |
682 | |
683 | /* | |
684 | * Fence debugfs | |
685 | */ | |
686 | #if defined(CONFIG_DEBUG_FS) | |
687 | static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) | |
688 | { | |
689 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
690 | struct drm_device *dev = node->minor->dev; | |
691 | struct amdgpu_device *adev = dev->dev_private; | |
5907a0d8 | 692 | int i; |
d38ceaf9 AD |
693 | |
694 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
695 | struct amdgpu_ring *ring = adev->rings[i]; | |
696 | if (!ring || !ring->fence_drv.initialized) | |
697 | continue; | |
698 | ||
699 | amdgpu_fence_process(ring); | |
700 | ||
344c19f9 | 701 | seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); |
d38ceaf9 AD |
702 | seq_printf(m, "Last signaled fence 0x%016llx\n", |
703 | (unsigned long long)atomic64_read(&ring->fence_drv.last_seq)); | |
704 | seq_printf(m, "Last emitted 0x%016llx\n", | |
5907a0d8 | 705 | ring->fence_drv.sync_seq); |
d38ceaf9 AD |
706 | } |
707 | return 0; | |
708 | } | |
709 | ||
18db89b4 AD |
710 | /** |
711 | * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset | |
712 | * | |
713 | * Manually trigger a gpu reset at the next fence wait. | |
714 | */ | |
715 | static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) | |
716 | { | |
717 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
718 | struct drm_device *dev = node->minor->dev; | |
719 | struct amdgpu_device *adev = dev->dev_private; | |
720 | ||
721 | seq_printf(m, "gpu reset\n"); | |
722 | amdgpu_gpu_reset(adev); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
d38ceaf9 AD |
727 | static struct drm_info_list amdgpu_debugfs_fence_list[] = { |
728 | {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, | |
18db89b4 | 729 | {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} |
d38ceaf9 AD |
730 | }; |
731 | #endif | |
732 | ||
733 | int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) | |
734 | { | |
735 | #if defined(CONFIG_DEBUG_FS) | |
18db89b4 | 736 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); |
d38ceaf9 AD |
737 | #else |
738 | return 0; | |
739 | #endif | |
740 | } | |
741 |