[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_irq.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_IRQ_H__
#define __AMDGPU_IRQ_H__

#include <linux/irqdomain.h>
#include "amdgpu_ih.h"

#define AMDGPU_MAX_IRQ_SRC_ID	0x100

struct amdgpu_device;
struct amdgpu_iv_entry;

enum amdgpu_interrupt_state {
	AMDGPU_IRQ_STATE_DISABLE,
	AMDGPU_IRQ_STATE_ENABLE,
};

struct amdgpu_irq_src {
	unsigned				num_types;
	atomic_t				*enabled_types;
	const struct amdgpu_irq_src_funcs	*funcs;
	void *data;
};

/* provided by interrupt generating IP blocks */
struct amdgpu_irq_src_funcs {
	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
		   unsigned type, enum amdgpu_interrupt_state state);

	int (*process)(struct amdgpu_device *adev,
		       struct amdgpu_irq_src *source,
		       struct amdgpu_iv_entry *entry);
};

struct amdgpu_irq {
	bool				installed;
	spinlock_t			lock;
	/* interrupt sources */
	struct amdgpu_irq_src		*sources[AMDGPU_MAX_IRQ_SRC_ID];

	/* status, etc. */
	bool				msi_enabled; /* msi enabled */

	/* interrupt ring */
	struct amdgpu_ih_ring		ih;
	const struct amdgpu_ih_funcs	*ih_funcs;

	/* gen irq stuff */
	struct irq_domain		*domain; /* GPU irq controller domain */
	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
};

void amdgpu_irq_preinstall(struct drm_device *dev);
int amdgpu_irq_postinstall(struct drm_device *dev);
void amdgpu_irq_uninstall(struct drm_device *dev);
irqreturn_t amdgpu_irq_handler(int irq, void *arg);

int amdgpu_irq_init(struct amdgpu_device *adev);
void amdgpu_irq_fini(struct amdgpu_device *adev);
int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
		      struct amdgpu_irq_src *source);
void amdgpu_irq_dispatch(struct amdgpu_device *adev,
			 struct amdgpu_iv_entry *entry);
int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		      unsigned type);
int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		   unsigned type);
bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
			    struct amdgpu_irq_src *src,
			    unsigned type);
int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		   unsigned type);
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
			unsigned type);
void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);

int amdgpu_irq_add_domain(struct amdgpu_device *adev);
void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_IRQ_H__
	25	#define __AMDGPU_IRQ_H__
	26
5f232365	27	#include <linux/irqdomain.h>
d38ceaf9 AD	28	#include "amdgpu_ih.h"
	29
	30	#define AMDGPU_MAX_IRQ_SRC_ID 0x100
	31
	32	struct amdgpu_device;
	33	struct amdgpu_iv_entry;
	34
	35	enum amdgpu_interrupt_state {
	36	AMDGPU_IRQ_STATE_DISABLE,
	37	AMDGPU_IRQ_STATE_ENABLE,
	38	};
	39
	40	struct amdgpu_irq_src {
	41	unsigned num_types;
	42	atomic_t *enabled_types;
	43	const struct amdgpu_irq_src_funcs *funcs;
0cf3be21	44	void *data;
d38ceaf9 AD	45	};
	46
	47	/* provided by interrupt generating IP blocks */
	48	struct amdgpu_irq_src_funcs {
	49	int (set)(struct amdgpu_device adev, struct amdgpu_irq_src *source,
	50	unsigned type, enum amdgpu_interrupt_state state);
	51
	52	int (process)(struct amdgpu_device adev,
	53	struct amdgpu_irq_src *source,
	54	struct amdgpu_iv_entry *entry);
	55	};
	56
	57	struct amdgpu_irq {
	58	bool installed;
	59	spinlock_t lock;
	60	/* interrupt sources */
	61	struct amdgpu_irq_src *sources[AMDGPU_MAX_IRQ_SRC_ID];
	62
	63	/* status, etc. */
	64	bool msi_enabled; /* msi enabled */
	65
	66	/* interrupt ring */
	67	struct amdgpu_ih_ring ih;
	68	const struct amdgpu_ih_funcs *ih_funcs;
5f232365 AD	69
	70	/* gen irq stuff */
	71	struct irq_domain domain; / GPU irq controller domain */
	72	unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
d38ceaf9 AD	73	};
	74
	75	void amdgpu_irq_preinstall(struct drm_device *dev);
	76	int amdgpu_irq_postinstall(struct drm_device *dev);
	77	void amdgpu_irq_uninstall(struct drm_device *dev);
	78	irqreturn_t amdgpu_irq_handler(int irq, void *arg);
	79
	80	int amdgpu_irq_init(struct amdgpu_device *adev);
	81	void amdgpu_irq_fini(struct amdgpu_device *adev);
	82	int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
	83	struct amdgpu_irq_src *source);
	84	void amdgpu_irq_dispatch(struct amdgpu_device *adev,
	85	struct amdgpu_iv_entry *entry);
	86	int amdgpu_irq_update(struct amdgpu_device adev, struct amdgpu_irq_src src,
	87	unsigned type);
	88	int amdgpu_irq_get(struct amdgpu_device adev, struct amdgpu_irq_src src,
	89	unsigned type);
	90	bool amdgpu_irq_get_delayed(struct amdgpu_device *adev,
	91	struct amdgpu_irq_src *src,
	92	unsigned type);
	93	int amdgpu_irq_put(struct amdgpu_device adev, struct amdgpu_irq_src src,
	94	unsigned type);
	95	bool amdgpu_irq_enabled(struct amdgpu_device adev, struct amdgpu_irq_src src,
	96	unsigned type);
0eaeb070	97	void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
d38ceaf9	98
5f232365 AD	99	int amdgpu_irq_add_domain(struct amdgpu_device *adev);
	100	void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
	101	unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
	102
d38ceaf9	103	#endif