Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Permission is hereby granted, free of charge, to any person obtaining a | |
3 | * copy of this software and associated documentation files (the "Software"), | |
4 | * to deal in the Software without restriction, including without limitation | |
5 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
6 | * and/or sell copies of the Software, and to permit persons to whom the | |
7 | * Software is furnished to do so, subject to the following conditions: | |
8 | * | |
9 | * The above copyright notice and this permission notice shall be included in | |
10 | * all copies or substantial portions of the Software. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
15 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
16 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
17 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
18 | * OTHER DEALINGS IN THE SOFTWARE. | |
19 | * | |
20 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
21 | * Alex Deucher <alexdeucher@gmail.com> | |
22 | */ | |
23 | #include <drm/drmP.h> | |
24 | #include "amdgpu.h" | |
25 | #include "amdgpu_drv.h" | |
26 | #include "amdgpu_pm.h" | |
27 | #include "amdgpu_dpm.h" | |
28 | #include "atom.h" | |
29 | #include <linux/power_supply.h> | |
30 | #include <linux/hwmon.h> | |
31 | #include <linux/hwmon-sysfs.h> | |
32 | ||
1b5708ff RZ |
33 | #include "amd_powerplay.h" |
34 | ||
d38ceaf9 AD |
35 | static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); |
36 | ||
37 | void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) | |
38 | { | |
e61710c5 | 39 | if (adev->pp_enabled) |
1b5708ff RZ |
40 | /* TODO */ |
41 | return; | |
42 | ||
d38ceaf9 AD |
43 | if (adev->pm.dpm_enabled) { |
44 | mutex_lock(&adev->pm.mutex); | |
45 | if (power_supply_is_system_supplied() > 0) | |
46 | adev->pm.dpm.ac_power = true; | |
47 | else | |
48 | adev->pm.dpm.ac_power = false; | |
49 | if (adev->pm.funcs->enable_bapm) | |
50 | amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); | |
51 | mutex_unlock(&adev->pm.mutex); | |
52 | } | |
53 | } | |
54 | ||
55 | static ssize_t amdgpu_get_dpm_state(struct device *dev, | |
56 | struct device_attribute *attr, | |
57 | char *buf) | |
58 | { | |
59 | struct drm_device *ddev = dev_get_drvdata(dev); | |
60 | struct amdgpu_device *adev = ddev->dev_private; | |
1b5708ff RZ |
61 | enum amd_pm_state_type pm; |
62 | ||
e61710c5 | 63 | if (adev->pp_enabled) { |
1b5708ff RZ |
64 | pm = amdgpu_dpm_get_current_power_state(adev); |
65 | } else | |
66 | pm = adev->pm.dpm.user_state; | |
d38ceaf9 AD |
67 | |
68 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
69 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
70 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | |
71 | } | |
72 | ||
73 | static ssize_t amdgpu_set_dpm_state(struct device *dev, | |
74 | struct device_attribute *attr, | |
75 | const char *buf, | |
76 | size_t count) | |
77 | { | |
78 | struct drm_device *ddev = dev_get_drvdata(dev); | |
79 | struct amdgpu_device *adev = ddev->dev_private; | |
1b5708ff | 80 | enum amd_pm_state_type state; |
d38ceaf9 | 81 | |
d38ceaf9 | 82 | if (strncmp("battery", buf, strlen("battery")) == 0) |
1b5708ff | 83 | state = POWER_STATE_TYPE_BATTERY; |
d38ceaf9 | 84 | else if (strncmp("balanced", buf, strlen("balanced")) == 0) |
1b5708ff | 85 | state = POWER_STATE_TYPE_BALANCED; |
d38ceaf9 | 86 | else if (strncmp("performance", buf, strlen("performance")) == 0) |
1b5708ff | 87 | state = POWER_STATE_TYPE_PERFORMANCE; |
d38ceaf9 | 88 | else { |
d38ceaf9 AD |
89 | count = -EINVAL; |
90 | goto fail; | |
91 | } | |
d38ceaf9 | 92 | |
e61710c5 | 93 | if (adev->pp_enabled) { |
1b5708ff RZ |
94 | amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL); |
95 | } else { | |
96 | mutex_lock(&adev->pm.mutex); | |
97 | adev->pm.dpm.user_state = state; | |
98 | mutex_unlock(&adev->pm.mutex); | |
99 | ||
100 | /* Can't set dpm state when the card is off */ | |
101 | if (!(adev->flags & AMD_IS_PX) || | |
102 | (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) | |
103 | amdgpu_pm_compute_clocks(adev); | |
104 | } | |
d38ceaf9 AD |
105 | fail: |
106 | return count; | |
107 | } | |
108 | ||
109 | static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, | |
1b5708ff RZ |
110 | struct device_attribute *attr, |
111 | char *buf) | |
d38ceaf9 AD |
112 | { |
113 | struct drm_device *ddev = dev_get_drvdata(dev); | |
114 | struct amdgpu_device *adev = ddev->dev_private; | |
d38ceaf9 | 115 | |
e61710c5 | 116 | if (adev->pp_enabled) { |
1b5708ff RZ |
117 | enum amd_dpm_forced_level level; |
118 | ||
119 | level = amdgpu_dpm_get_performance_level(adev); | |
120 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
121 | (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : | |
122 | (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); | |
123 | } else { | |
124 | enum amdgpu_dpm_forced_level level; | |
125 | ||
126 | level = adev->pm.dpm.forced_level; | |
127 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
128 | (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" : | |
129 | (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); | |
130 | } | |
d38ceaf9 AD |
131 | } |
132 | ||
133 | static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, | |
134 | struct device_attribute *attr, | |
135 | const char *buf, | |
136 | size_t count) | |
137 | { | |
138 | struct drm_device *ddev = dev_get_drvdata(dev); | |
139 | struct amdgpu_device *adev = ddev->dev_private; | |
140 | enum amdgpu_dpm_forced_level level; | |
141 | int ret = 0; | |
142 | ||
d38ceaf9 AD |
143 | if (strncmp("low", buf, strlen("low")) == 0) { |
144 | level = AMDGPU_DPM_FORCED_LEVEL_LOW; | |
145 | } else if (strncmp("high", buf, strlen("high")) == 0) { | |
146 | level = AMDGPU_DPM_FORCED_LEVEL_HIGH; | |
147 | } else if (strncmp("auto", buf, strlen("auto")) == 0) { | |
148 | level = AMDGPU_DPM_FORCED_LEVEL_AUTO; | |
149 | } else { | |
150 | count = -EINVAL; | |
151 | goto fail; | |
152 | } | |
1b5708ff | 153 | |
e61710c5 | 154 | if (adev->pp_enabled) |
1b5708ff RZ |
155 | amdgpu_dpm_force_performance_level(adev, level); |
156 | else { | |
157 | mutex_lock(&adev->pm.mutex); | |
d38ceaf9 AD |
158 | if (adev->pm.dpm.thermal_active) { |
159 | count = -EINVAL; | |
160 | goto fail; | |
161 | } | |
162 | ret = amdgpu_dpm_force_performance_level(adev, level); | |
163 | if (ret) | |
164 | count = -EINVAL; | |
1b5708ff RZ |
165 | else |
166 | adev->pm.dpm.forced_level = level; | |
167 | mutex_unlock(&adev->pm.mutex); | |
d38ceaf9 AD |
168 | } |
169 | fail: | |
170 | mutex_unlock(&adev->pm.mutex); | |
171 | ||
172 | return count; | |
173 | } | |
174 | ||
175 | static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); | |
176 | static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, | |
177 | amdgpu_get_dpm_forced_performance_level, | |
178 | amdgpu_set_dpm_forced_performance_level); | |
179 | ||
180 | static ssize_t amdgpu_hwmon_show_temp(struct device *dev, | |
181 | struct device_attribute *attr, | |
182 | char *buf) | |
183 | { | |
184 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
185 | int temp; | |
186 | ||
e61710c5 | 187 | if (!adev->pp_enabled && !adev->pm.funcs->get_temperature) |
d38ceaf9 | 188 | temp = 0; |
8804b8d5 RZ |
189 | else |
190 | temp = amdgpu_dpm_get_temperature(adev); | |
d38ceaf9 AD |
191 | |
192 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
193 | } | |
194 | ||
195 | static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, | |
196 | struct device_attribute *attr, | |
197 | char *buf) | |
198 | { | |
199 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
200 | int hyst = to_sensor_dev_attr(attr)->index; | |
201 | int temp; | |
202 | ||
203 | if (hyst) | |
204 | temp = adev->pm.dpm.thermal.min_temp; | |
205 | else | |
206 | temp = adev->pm.dpm.thermal.max_temp; | |
207 | ||
208 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
209 | } | |
210 | ||
211 | static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, | |
212 | struct device_attribute *attr, | |
213 | char *buf) | |
214 | { | |
215 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
216 | u32 pwm_mode = 0; | |
217 | ||
e61710c5 | 218 | if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode) |
8804b8d5 RZ |
219 | return -EINVAL; |
220 | ||
221 | pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); | |
d38ceaf9 AD |
222 | |
223 | /* never 0 (full-speed), fuse or smc-controlled always */ | |
224 | return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); | |
225 | } | |
226 | ||
227 | static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, | |
228 | struct device_attribute *attr, | |
229 | const char *buf, | |
230 | size_t count) | |
231 | { | |
232 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
233 | int err; | |
234 | int value; | |
235 | ||
e61710c5 | 236 | if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode) |
d38ceaf9 AD |
237 | return -EINVAL; |
238 | ||
239 | err = kstrtoint(buf, 10, &value); | |
240 | if (err) | |
241 | return err; | |
242 | ||
243 | switch (value) { | |
244 | case 1: /* manual, percent-based */ | |
245 | amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC); | |
246 | break; | |
247 | default: /* disable */ | |
248 | amdgpu_dpm_set_fan_control_mode(adev, 0); | |
249 | break; | |
250 | } | |
251 | ||
252 | return count; | |
253 | } | |
254 | ||
255 | static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, | |
256 | struct device_attribute *attr, | |
257 | char *buf) | |
258 | { | |
259 | return sprintf(buf, "%i\n", 0); | |
260 | } | |
261 | ||
262 | static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, | |
263 | struct device_attribute *attr, | |
264 | char *buf) | |
265 | { | |
266 | return sprintf(buf, "%i\n", 255); | |
267 | } | |
268 | ||
269 | static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, | |
270 | struct device_attribute *attr, | |
271 | const char *buf, size_t count) | |
272 | { | |
273 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
274 | int err; | |
275 | u32 value; | |
276 | ||
277 | err = kstrtou32(buf, 10, &value); | |
278 | if (err) | |
279 | return err; | |
280 | ||
281 | value = (value * 100) / 255; | |
282 | ||
283 | err = amdgpu_dpm_set_fan_speed_percent(adev, value); | |
284 | if (err) | |
285 | return err; | |
286 | ||
287 | return count; | |
288 | } | |
289 | ||
290 | static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, | |
291 | struct device_attribute *attr, | |
292 | char *buf) | |
293 | { | |
294 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
295 | int err; | |
296 | u32 speed; | |
297 | ||
298 | err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); | |
299 | if (err) | |
300 | return err; | |
301 | ||
302 | speed = (speed * 255) / 100; | |
303 | ||
304 | return sprintf(buf, "%i\n", speed); | |
305 | } | |
306 | ||
307 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); | |
308 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); | |
309 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); | |
310 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); | |
311 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); | |
312 | static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); | |
313 | static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); | |
314 | ||
315 | static struct attribute *hwmon_attributes[] = { | |
316 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
317 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
318 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, | |
319 | &sensor_dev_attr_pwm1.dev_attr.attr, | |
320 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | |
321 | &sensor_dev_attr_pwm1_min.dev_attr.attr, | |
322 | &sensor_dev_attr_pwm1_max.dev_attr.attr, | |
323 | NULL | |
324 | }; | |
325 | ||
326 | static umode_t hwmon_attributes_visible(struct kobject *kobj, | |
327 | struct attribute *attr, int index) | |
328 | { | |
cc29ec87 | 329 | struct device *dev = kobj_to_dev(kobj); |
d38ceaf9 AD |
330 | struct amdgpu_device *adev = dev_get_drvdata(dev); |
331 | umode_t effective_mode = attr->mode; | |
332 | ||
1b5708ff | 333 | /* Skip limit attributes if DPM is not enabled */ |
d38ceaf9 AD |
334 | if (!adev->pm.dpm_enabled && |
335 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || | |
27100735 AD |
336 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || |
337 | attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
338 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
339 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
340 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
d38ceaf9 AD |
341 | return 0; |
342 | ||
e61710c5 | 343 | if (adev->pp_enabled) |
8804b8d5 RZ |
344 | return effective_mode; |
345 | ||
d38ceaf9 AD |
346 | /* Skip fan attributes if fan is not present */ |
347 | if (adev->pm.no_fan && | |
348 | (attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
349 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
350 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
351 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
352 | return 0; | |
353 | ||
354 | /* mask fan attributes if we have no bindings for this asic to expose */ | |
355 | if ((!adev->pm.funcs->get_fan_speed_percent && | |
356 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ | |
357 | (!adev->pm.funcs->get_fan_control_mode && | |
358 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ | |
359 | effective_mode &= ~S_IRUGO; | |
360 | ||
361 | if ((!adev->pm.funcs->set_fan_speed_percent && | |
362 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ | |
363 | (!adev->pm.funcs->set_fan_control_mode && | |
364 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ | |
365 | effective_mode &= ~S_IWUSR; | |
366 | ||
367 | /* hide max/min values if we can't both query and manage the fan */ | |
368 | if ((!adev->pm.funcs->set_fan_speed_percent && | |
369 | !adev->pm.funcs->get_fan_speed_percent) && | |
370 | (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
371 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
372 | return 0; | |
373 | ||
374 | return effective_mode; | |
375 | } | |
376 | ||
377 | static const struct attribute_group hwmon_attrgroup = { | |
378 | .attrs = hwmon_attributes, | |
379 | .is_visible = hwmon_attributes_visible, | |
380 | }; | |
381 | ||
382 | static const struct attribute_group *hwmon_groups[] = { | |
383 | &hwmon_attrgroup, | |
384 | NULL | |
385 | }; | |
386 | ||
387 | void amdgpu_dpm_thermal_work_handler(struct work_struct *work) | |
388 | { | |
389 | struct amdgpu_device *adev = | |
390 | container_of(work, struct amdgpu_device, | |
391 | pm.dpm.thermal.work); | |
392 | /* switch to the thermal state */ | |
3a2c788d | 393 | enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; |
d38ceaf9 AD |
394 | |
395 | if (!adev->pm.dpm_enabled) | |
396 | return; | |
397 | ||
398 | if (adev->pm.funcs->get_temperature) { | |
399 | int temp = amdgpu_dpm_get_temperature(adev); | |
400 | ||
401 | if (temp < adev->pm.dpm.thermal.min_temp) | |
402 | /* switch back the user state */ | |
403 | dpm_state = adev->pm.dpm.user_state; | |
404 | } else { | |
405 | if (adev->pm.dpm.thermal.high_to_low) | |
406 | /* switch back the user state */ | |
407 | dpm_state = adev->pm.dpm.user_state; | |
408 | } | |
409 | mutex_lock(&adev->pm.mutex); | |
410 | if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) | |
411 | adev->pm.dpm.thermal_active = true; | |
412 | else | |
413 | adev->pm.dpm.thermal_active = false; | |
414 | adev->pm.dpm.state = dpm_state; | |
415 | mutex_unlock(&adev->pm.mutex); | |
416 | ||
417 | amdgpu_pm_compute_clocks(adev); | |
418 | } | |
419 | ||
420 | static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, | |
3a2c788d | 421 | enum amd_pm_state_type dpm_state) |
d38ceaf9 AD |
422 | { |
423 | int i; | |
424 | struct amdgpu_ps *ps; | |
425 | u32 ui_class; | |
426 | bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? | |
427 | true : false; | |
428 | ||
429 | /* check if the vblank period is too short to adjust the mclk */ | |
430 | if (single_display && adev->pm.funcs->vblank_too_short) { | |
431 | if (amdgpu_dpm_vblank_too_short(adev)) | |
432 | single_display = false; | |
433 | } | |
434 | ||
435 | /* certain older asics have a separare 3D performance state, | |
436 | * so try that first if the user selected performance | |
437 | */ | |
438 | if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) | |
439 | dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; | |
440 | /* balanced states don't exist at the moment */ | |
441 | if (dpm_state == POWER_STATE_TYPE_BALANCED) | |
442 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
443 | ||
444 | restart_search: | |
445 | /* Pick the best power state based on current conditions */ | |
446 | for (i = 0; i < adev->pm.dpm.num_ps; i++) { | |
447 | ps = &adev->pm.dpm.ps[i]; | |
448 | ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; | |
449 | switch (dpm_state) { | |
450 | /* user states */ | |
451 | case POWER_STATE_TYPE_BATTERY: | |
452 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { | |
453 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
454 | if (single_display) | |
455 | return ps; | |
456 | } else | |
457 | return ps; | |
458 | } | |
459 | break; | |
460 | case POWER_STATE_TYPE_BALANCED: | |
461 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { | |
462 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
463 | if (single_display) | |
464 | return ps; | |
465 | } else | |
466 | return ps; | |
467 | } | |
468 | break; | |
469 | case POWER_STATE_TYPE_PERFORMANCE: | |
470 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { | |
471 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
472 | if (single_display) | |
473 | return ps; | |
474 | } else | |
475 | return ps; | |
476 | } | |
477 | break; | |
478 | /* internal states */ | |
479 | case POWER_STATE_TYPE_INTERNAL_UVD: | |
480 | if (adev->pm.dpm.uvd_ps) | |
481 | return adev->pm.dpm.uvd_ps; | |
482 | else | |
483 | break; | |
484 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: | |
485 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | |
486 | return ps; | |
487 | break; | |
488 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: | |
489 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | |
490 | return ps; | |
491 | break; | |
492 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
493 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | |
494 | return ps; | |
495 | break; | |
496 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
497 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | |
498 | return ps; | |
499 | break; | |
500 | case POWER_STATE_TYPE_INTERNAL_BOOT: | |
501 | return adev->pm.dpm.boot_ps; | |
502 | case POWER_STATE_TYPE_INTERNAL_THERMAL: | |
503 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | |
504 | return ps; | |
505 | break; | |
506 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
507 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) | |
508 | return ps; | |
509 | break; | |
510 | case POWER_STATE_TYPE_INTERNAL_ULV: | |
511 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) | |
512 | return ps; | |
513 | break; | |
514 | case POWER_STATE_TYPE_INTERNAL_3DPERF: | |
515 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | |
516 | return ps; | |
517 | break; | |
518 | default: | |
519 | break; | |
520 | } | |
521 | } | |
522 | /* use a fallback state if we didn't match */ | |
523 | switch (dpm_state) { | |
524 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: | |
525 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; | |
526 | goto restart_search; | |
527 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: | |
528 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
529 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
530 | if (adev->pm.dpm.uvd_ps) { | |
531 | return adev->pm.dpm.uvd_ps; | |
532 | } else { | |
533 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
534 | goto restart_search; | |
535 | } | |
536 | case POWER_STATE_TYPE_INTERNAL_THERMAL: | |
537 | dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; | |
538 | goto restart_search; | |
539 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
540 | dpm_state = POWER_STATE_TYPE_BATTERY; | |
541 | goto restart_search; | |
542 | case POWER_STATE_TYPE_BATTERY: | |
543 | case POWER_STATE_TYPE_BALANCED: | |
544 | case POWER_STATE_TYPE_INTERNAL_3DPERF: | |
545 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
546 | goto restart_search; | |
547 | default: | |
548 | break; | |
549 | } | |
550 | ||
551 | return NULL; | |
552 | } | |
553 | ||
554 | static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) | |
555 | { | |
556 | int i; | |
557 | struct amdgpu_ps *ps; | |
3a2c788d | 558 | enum amd_pm_state_type dpm_state; |
d38ceaf9 AD |
559 | int ret; |
560 | ||
561 | /* if dpm init failed */ | |
562 | if (!adev->pm.dpm_enabled) | |
563 | return; | |
564 | ||
565 | if (adev->pm.dpm.user_state != adev->pm.dpm.state) { | |
566 | /* add other state override checks here */ | |
567 | if ((!adev->pm.dpm.thermal_active) && | |
568 | (!adev->pm.dpm.uvd_active)) | |
569 | adev->pm.dpm.state = adev->pm.dpm.user_state; | |
570 | } | |
571 | dpm_state = adev->pm.dpm.state; | |
572 | ||
573 | ps = amdgpu_dpm_pick_power_state(adev, dpm_state); | |
574 | if (ps) | |
575 | adev->pm.dpm.requested_ps = ps; | |
576 | else | |
577 | return; | |
578 | ||
579 | /* no need to reprogram if nothing changed unless we are on BTC+ */ | |
580 | if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) { | |
581 | /* vce just modifies an existing state so force a change */ | |
582 | if (ps->vce_active != adev->pm.dpm.vce_active) | |
583 | goto force; | |
2f7d10b3 | 584 | if (adev->flags & AMD_IS_APU) { |
d38ceaf9 AD |
585 | /* for APUs if the num crtcs changed but state is the same, |
586 | * all we need to do is update the display configuration. | |
587 | */ | |
588 | if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) { | |
589 | /* update display watermarks based on new power state */ | |
590 | amdgpu_display_bandwidth_update(adev); | |
591 | /* update displays */ | |
592 | amdgpu_dpm_display_configuration_changed(adev); | |
593 | adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; | |
594 | adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; | |
595 | } | |
596 | return; | |
597 | } else { | |
598 | /* for BTC+ if the num crtcs hasn't changed and state is the same, | |
599 | * nothing to do, if the num crtcs is > 1 and state is the same, | |
600 | * update display configuration. | |
601 | */ | |
602 | if (adev->pm.dpm.new_active_crtcs == | |
603 | adev->pm.dpm.current_active_crtcs) { | |
604 | return; | |
605 | } else if ((adev->pm.dpm.current_active_crtc_count > 1) && | |
606 | (adev->pm.dpm.new_active_crtc_count > 1)) { | |
607 | /* update display watermarks based on new power state */ | |
608 | amdgpu_display_bandwidth_update(adev); | |
609 | /* update displays */ | |
610 | amdgpu_dpm_display_configuration_changed(adev); | |
611 | adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; | |
612 | adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; | |
613 | return; | |
614 | } | |
615 | } | |
616 | } | |
617 | ||
618 | force: | |
619 | if (amdgpu_dpm == 1) { | |
620 | printk("switching from power state:\n"); | |
621 | amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); | |
622 | printk("switching to power state:\n"); | |
623 | amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); | |
624 | } | |
625 | ||
d38ceaf9 AD |
626 | mutex_lock(&adev->ring_lock); |
627 | ||
628 | /* update whether vce is active */ | |
629 | ps->vce_active = adev->pm.dpm.vce_active; | |
630 | ||
631 | ret = amdgpu_dpm_pre_set_power_state(adev); | |
632 | if (ret) | |
633 | goto done; | |
634 | ||
635 | /* update display watermarks based on new power state */ | |
636 | amdgpu_display_bandwidth_update(adev); | |
637 | /* update displays */ | |
638 | amdgpu_dpm_display_configuration_changed(adev); | |
639 | ||
640 | adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; | |
641 | adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; | |
642 | ||
643 | /* wait for the rings to drain */ | |
644 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
645 | struct amdgpu_ring *ring = adev->rings[i]; | |
646 | if (ring && ring->ready) | |
647 | amdgpu_fence_wait_empty(ring); | |
648 | } | |
649 | ||
650 | /* program the new power state */ | |
651 | amdgpu_dpm_set_power_state(adev); | |
652 | ||
653 | /* update current power state */ | |
654 | adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps; | |
655 | ||
656 | amdgpu_dpm_post_set_power_state(adev); | |
657 | ||
658 | if (adev->pm.funcs->force_performance_level) { | |
659 | if (adev->pm.dpm.thermal_active) { | |
660 | enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; | |
661 | /* force low perf level for thermal */ | |
662 | amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW); | |
663 | /* save the user's level */ | |
664 | adev->pm.dpm.forced_level = level; | |
665 | } else { | |
666 | /* otherwise, user selected level */ | |
667 | amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); | |
668 | } | |
669 | } | |
670 | ||
671 | done: | |
672 | mutex_unlock(&adev->ring_lock); | |
d38ceaf9 AD |
673 | } |
674 | ||
675 | void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) | |
676 | { | |
e61710c5 | 677 | if (adev->pp_enabled) |
d38ceaf9 | 678 | amdgpu_dpm_powergate_uvd(adev, !enable); |
1b5708ff RZ |
679 | else { |
680 | if (adev->pm.funcs->powergate_uvd) { | |
d38ceaf9 | 681 | mutex_lock(&adev->pm.mutex); |
1b5708ff RZ |
682 | /* enable/disable UVD */ |
683 | amdgpu_dpm_powergate_uvd(adev, !enable); | |
d38ceaf9 AD |
684 | mutex_unlock(&adev->pm.mutex); |
685 | } else { | |
1b5708ff RZ |
686 | if (enable) { |
687 | mutex_lock(&adev->pm.mutex); | |
688 | adev->pm.dpm.uvd_active = true; | |
689 | adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; | |
690 | mutex_unlock(&adev->pm.mutex); | |
691 | } else { | |
692 | mutex_lock(&adev->pm.mutex); | |
693 | adev->pm.dpm.uvd_active = false; | |
694 | mutex_unlock(&adev->pm.mutex); | |
695 | } | |
696 | amdgpu_pm_compute_clocks(adev); | |
d38ceaf9 AD |
697 | } |
698 | ||
d38ceaf9 AD |
699 | } |
700 | } | |
701 | ||
702 | void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) | |
703 | { | |
e61710c5 | 704 | if (adev->pp_enabled) |
b7a07769 | 705 | amdgpu_dpm_powergate_vce(adev, !enable); |
1b5708ff RZ |
706 | else { |
707 | if (adev->pm.funcs->powergate_vce) { | |
b7a07769 | 708 | mutex_lock(&adev->pm.mutex); |
1b5708ff | 709 | amdgpu_dpm_powergate_vce(adev, !enable); |
b7a07769 SJ |
710 | mutex_unlock(&adev->pm.mutex); |
711 | } else { | |
1b5708ff RZ |
712 | if (enable) { |
713 | mutex_lock(&adev->pm.mutex); | |
714 | adev->pm.dpm.vce_active = true; | |
715 | /* XXX select vce level based on ring/task */ | |
716 | adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL; | |
717 | mutex_unlock(&adev->pm.mutex); | |
718 | } else { | |
719 | mutex_lock(&adev->pm.mutex); | |
720 | adev->pm.dpm.vce_active = false; | |
721 | mutex_unlock(&adev->pm.mutex); | |
722 | } | |
723 | amdgpu_pm_compute_clocks(adev); | |
b7a07769 | 724 | } |
b7a07769 | 725 | } |
d38ceaf9 AD |
726 | } |
727 | ||
728 | void amdgpu_pm_print_power_states(struct amdgpu_device *adev) | |
729 | { | |
730 | int i; | |
731 | ||
e61710c5 | 732 | if (adev->pp_enabled) |
1b5708ff RZ |
733 | /* TO DO */ |
734 | return; | |
735 | ||
736 | for (i = 0; i < adev->pm.dpm.num_ps; i++) | |
d38ceaf9 | 737 | amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); |
1b5708ff | 738 | |
d38ceaf9 AD |
739 | } |
740 | ||
741 | int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) | |
742 | { | |
743 | int ret; | |
744 | ||
c86f5ebf AD |
745 | if (adev->pm.sysfs_initialized) |
746 | return 0; | |
747 | ||
e61710c5 | 748 | if (!adev->pp_enabled) { |
1b5708ff RZ |
749 | if (adev->pm.funcs->get_temperature == NULL) |
750 | return 0; | |
751 | } | |
752 | ||
d38ceaf9 AD |
753 | adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, |
754 | DRIVER_NAME, adev, | |
755 | hwmon_groups); | |
756 | if (IS_ERR(adev->pm.int_hwmon_dev)) { | |
757 | ret = PTR_ERR(adev->pm.int_hwmon_dev); | |
758 | dev_err(adev->dev, | |
759 | "Unable to register hwmon device: %d\n", ret); | |
760 | return ret; | |
761 | } | |
762 | ||
763 | ret = device_create_file(adev->dev, &dev_attr_power_dpm_state); | |
764 | if (ret) { | |
765 | DRM_ERROR("failed to create device file for dpm state\n"); | |
766 | return ret; | |
767 | } | |
768 | ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level); | |
769 | if (ret) { | |
770 | DRM_ERROR("failed to create device file for dpm state\n"); | |
771 | return ret; | |
772 | } | |
773 | ret = amdgpu_debugfs_pm_init(adev); | |
774 | if (ret) { | |
775 | DRM_ERROR("Failed to register debugfs file for dpm!\n"); | |
776 | return ret; | |
777 | } | |
778 | ||
c86f5ebf AD |
779 | adev->pm.sysfs_initialized = true; |
780 | ||
d38ceaf9 AD |
781 | return 0; |
782 | } | |
783 | ||
784 | void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) | |
785 | { | |
786 | if (adev->pm.int_hwmon_dev) | |
787 | hwmon_device_unregister(adev->pm.int_hwmon_dev); | |
788 | device_remove_file(adev->dev, &dev_attr_power_dpm_state); | |
789 | device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level); | |
790 | } | |
791 | ||
792 | void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) | |
793 | { | |
794 | struct drm_device *ddev = adev->ddev; | |
795 | struct drm_crtc *crtc; | |
796 | struct amdgpu_crtc *amdgpu_crtc; | |
797 | ||
798 | if (!adev->pm.dpm_enabled) | |
799 | return; | |
800 | ||
e61710c5 | 801 | if (adev->pp_enabled) { |
1b5708ff RZ |
802 | int i = 0; |
803 | ||
804 | amdgpu_display_bandwidth_update(adev); | |
805 | mutex_lock(&adev->ring_lock); | |
806 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
807 | struct amdgpu_ring *ring = adev->rings[i]; | |
808 | if (ring && ring->ready) | |
809 | amdgpu_fence_wait_empty(ring); | |
75ac63db | 810 | } |
1b5708ff | 811 | mutex_unlock(&adev->ring_lock); |
d38ceaf9 | 812 | |
1b5708ff RZ |
813 | amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL); |
814 | } else { | |
815 | mutex_lock(&adev->pm.mutex); | |
816 | adev->pm.dpm.new_active_crtcs = 0; | |
817 | adev->pm.dpm.new_active_crtc_count = 0; | |
818 | if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { | |
819 | list_for_each_entry(crtc, | |
820 | &ddev->mode_config.crtc_list, head) { | |
821 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
822 | if (crtc->enabled) { | |
823 | adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); | |
824 | adev->pm.dpm.new_active_crtc_count++; | |
825 | } | |
d38ceaf9 AD |
826 | } |
827 | } | |
1b5708ff RZ |
828 | /* update battery/ac status */ |
829 | if (power_supply_is_system_supplied() > 0) | |
830 | adev->pm.dpm.ac_power = true; | |
831 | else | |
832 | adev->pm.dpm.ac_power = false; | |
d38ceaf9 | 833 | |
1b5708ff | 834 | amdgpu_dpm_change_power_state_locked(adev); |
d38ceaf9 | 835 | |
1b5708ff RZ |
836 | mutex_unlock(&adev->pm.mutex); |
837 | } | |
d38ceaf9 AD |
838 | } |
839 | ||
840 | /* | |
841 | * Debugfs info | |
842 | */ | |
843 | #if defined(CONFIG_DEBUG_FS) | |
844 | ||
845 | static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) | |
846 | { | |
847 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
848 | struct drm_device *dev = node->minor->dev; | |
849 | struct amdgpu_device *adev = dev->dev_private; | |
850 | ||
1b5708ff RZ |
851 | if (!adev->pm.dpm_enabled) { |
852 | seq_printf(m, "dpm not enabled\n"); | |
853 | return 0; | |
854 | } | |
e61710c5 | 855 | if (adev->pp_enabled) { |
1b5708ff RZ |
856 | amdgpu_dpm_debugfs_print_current_performance_level(adev, m); |
857 | } else { | |
d38ceaf9 AD |
858 | mutex_lock(&adev->pm.mutex); |
859 | if (adev->pm.funcs->debugfs_print_current_performance_level) | |
860 | amdgpu_dpm_debugfs_print_current_performance_level(adev, m); | |
861 | else | |
862 | seq_printf(m, "Debugfs support not implemented for this asic\n"); | |
863 | mutex_unlock(&adev->pm.mutex); | |
864 | } | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | static struct drm_info_list amdgpu_pm_info_list[] = { | |
870 | {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, | |
871 | }; | |
872 | #endif | |
873 | ||
874 | static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) | |
875 | { | |
876 | #if defined(CONFIG_DEBUG_FS) | |
877 | return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); | |
878 | #else | |
879 | return 0; | |
880 | #endif | |
881 | } |