projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'omap-for-v4.8/soc' into omap-for-v4.8/fixes
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_drv.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "atom.h"
29#include <linux/power_supply.h>
30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
32
1b5708ff
RZ		 33#include "amd_powerplay.h"
34
d38ceaf9
AD		 35static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
36
37void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
38{
e61710c5 39 if (adev->pp_enabled)
1b5708ff
RZ		 40 /* TODO */
41 return;
42
d38ceaf9
AD		 43 if (adev->pm.dpm_enabled) {
44 mutex_lock(&adev->pm.mutex);
45 if (power_supply_is_system_supplied() > 0)
46 adev->pm.dpm.ac_power = true;
47 else
48 adev->pm.dpm.ac_power = false;
49 if (adev->pm.funcs->enable_bapm)
50 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
51 mutex_unlock(&adev->pm.mutex);
52 }
53}
54
55static ssize_t amdgpu_get_dpm_state(struct device *dev,
56 struct device_attribute *attr,
57 char *buf)
58{
59 struct drm_device *ddev = dev_get_drvdata(dev);
60 struct amdgpu_device *adev = ddev->dev_private;
1b5708ff
RZ		 61 enum amd_pm_state_type pm;
62
e61710c5 63 if (adev->pp_enabled) {
1b5708ff
RZ		 64 pm = amdgpu_dpm_get_current_power_state(adev);
65 } else
66 pm = adev->pm.dpm.user_state;
d38ceaf9
AD		 67
68 return snprintf(buf, PAGE_SIZE, "%s\n",
69 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
70 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
71}
72
73static ssize_t amdgpu_set_dpm_state(struct device *dev,
74 struct device_attribute *attr,
75 const char *buf,
76 size_t count)
77{
78 struct drm_device *ddev = dev_get_drvdata(dev);
79 struct amdgpu_device *adev = ddev->dev_private;
1b5708ff 80 enum amd_pm_state_type state;
d38ceaf9 81
d38ceaf9 82 if (strncmp("battery", buf, strlen("battery")) == 0)
1b5708ff 83 state = POWER_STATE_TYPE_BATTERY;
d38ceaf9 84 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
1b5708ff 85 state = POWER_STATE_TYPE_BALANCED;
d38ceaf9 86 else if (strncmp("performance", buf, strlen("performance")) == 0)
1b5708ff 87 state = POWER_STATE_TYPE_PERFORMANCE;
d38ceaf9 88 else {
d38ceaf9
AD		 89 count = -EINVAL;
90 goto fail;
91 }
d38ceaf9 92
e61710c5 93 if (adev->pp_enabled) {
1b5708ff
RZ		 94 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
95 } else {
96 mutex_lock(&adev->pm.mutex);
97 adev->pm.dpm.user_state = state;
98 mutex_unlock(&adev->pm.mutex);
99
100 /* Can't set dpm state when the card is off */
101 if (!(adev->flags & AMD_IS_PX) ||
102 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
103 amdgpu_pm_compute_clocks(adev);
104 }
d38ceaf9
AD		 105fail:
106 return count;
107}
108
109static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
1b5708ff
RZ		 110 struct device_attribute *attr,
111 char *buf)
d38ceaf9
AD		 112{
113 struct drm_device *ddev = dev_get_drvdata(dev);
114 struct amdgpu_device *adev = ddev->dev_private;
d38ceaf9 115
0c67df48
AD		 116 if ((adev->flags & AMD_IS_PX) &&
117 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
118 return snprintf(buf, PAGE_SIZE, "off\n");
119
e61710c5 120 if (adev->pp_enabled) {
1b5708ff
RZ		 121 enum amd_dpm_forced_level level;
122
123 level = amdgpu_dpm_get_performance_level(adev);
124 return snprintf(buf, PAGE_SIZE, "%s\n",
125 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
f3898ea1
EH		 126 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
127 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
128 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
1b5708ff
RZ		 129 } else {
130 enum amdgpu_dpm_forced_level level;
131
132 level = adev->pm.dpm.forced_level;
133 return snprintf(buf, PAGE_SIZE, "%s\n",
134 (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
135 (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
136 }
d38ceaf9
AD		 137}
138
139static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
140 struct device_attribute *attr,
141 const char *buf,
142 size_t count)
143{
144 struct drm_device *ddev = dev_get_drvdata(dev);
145 struct amdgpu_device *adev = ddev->dev_private;
146 enum amdgpu_dpm_forced_level level;
147 int ret = 0;
148
0c67df48
AD		 149 /* Can't force performance level when the card is off */
150 if ((adev->flags & AMD_IS_PX) &&
151 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
152 return -EINVAL;
153
d38ceaf9
AD		 154 if (strncmp("low", buf, strlen("low")) == 0) {
155 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
156 } else if (strncmp("high", buf, strlen("high")) == 0) {
157 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
158 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
159 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
f3898ea1
EH		 160 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
161 level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
d38ceaf9
AD		 162 } else {
163 count = -EINVAL;
164 goto fail;
165 }
1b5708ff 166
e61710c5 167 if (adev->pp_enabled)
1b5708ff
RZ		 168 amdgpu_dpm_force_performance_level(adev, level);
169 else {
170 mutex_lock(&adev->pm.mutex);
d38ceaf9
AD		 171 if (adev->pm.dpm.thermal_active) {
172 count = -EINVAL;
10f950f6 173 mutex_unlock(&adev->pm.mutex);
d38ceaf9
AD		 174 goto fail;
175 }
176 ret = amdgpu_dpm_force_performance_level(adev, level);
177 if (ret)
178 count = -EINVAL;
1b5708ff
RZ		 179 else
180 adev->pm.dpm.forced_level = level;
181 mutex_unlock(&adev->pm.mutex);
d38ceaf9
AD		 182 }
183fail:
d38ceaf9
AD		 184 return count;
185}
186
f3898ea1
EH		 187static ssize_t amdgpu_get_pp_num_states(struct device *dev,
188 struct device_attribute *attr,
189 char *buf)
190{
191 struct drm_device *ddev = dev_get_drvdata(dev);
192 struct amdgpu_device *adev = ddev->dev_private;
193 struct pp_states_info data;
194 int i, buf_len;
195
196 if (adev->pp_enabled)
197 amdgpu_dpm_get_pp_num_states(adev, &data);
198
199 buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
200 for (i = 0; i < data.nums; i++)
201 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
202 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
203 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
204 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
205 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
206
207 return buf_len;
208}
209
210static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
211 struct device_attribute *attr,
212 char *buf)
213{
214 struct drm_device *ddev = dev_get_drvdata(dev);
215 struct amdgpu_device *adev = ddev->dev_private;
216 struct pp_states_info data;
217 enum amd_pm_state_type pm = 0;
218 int i = 0;
219
220 if (adev->pp_enabled) {
221
222 pm = amdgpu_dpm_get_current_power_state(adev);
223 amdgpu_dpm_get_pp_num_states(adev, &data);
224
225 for (i = 0; i < data.nums; i++) {
226 if (pm == data.states[i])
227 break;
228 }
229
230 if (i == data.nums)
231 i = -EINVAL;
232 }
233
234 return snprintf(buf, PAGE_SIZE, "%d\n", i);
235}
236
237static ssize_t amdgpu_get_pp_force_state(struct device *dev,
238 struct device_attribute *attr,
239 char *buf)
240{
241 struct drm_device *ddev = dev_get_drvdata(dev);
242 struct amdgpu_device *adev = ddev->dev_private;
243 struct pp_states_info data;
244 enum amd_pm_state_type pm = 0;
245 int i;
246
247 if (adev->pp_force_state_enabled && adev->pp_enabled) {
248 pm = amdgpu_dpm_get_current_power_state(adev);
249 amdgpu_dpm_get_pp_num_states(adev, &data);
250
251 for (i = 0; i < data.nums; i++) {
252 if (pm == data.states[i])
253 break;
254 }
255
256 if (i == data.nums)
257 i = -EINVAL;
258
259 return snprintf(buf, PAGE_SIZE, "%d\n", i);
260
261 } else
262 return snprintf(buf, PAGE_SIZE, "\n");
263}
264
265static ssize_t amdgpu_set_pp_force_state(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf,
268 size_t count)
269{
270 struct drm_device *ddev = dev_get_drvdata(dev);
271 struct amdgpu_device *adev = ddev->dev_private;
272 enum amd_pm_state_type state = 0;
041bf022 273 unsigned long idx;
f3898ea1
EH		 274 int ret;
275
276 if (strlen(buf) == 1)
277 adev->pp_force_state_enabled = false;
041bf022
DC		 278 else if (adev->pp_enabled) {
279 struct pp_states_info data;
f3898ea1 280
041bf022
DC		 281 ret = kstrtoul(buf, 0, &idx);
282 if (ret || idx >= ARRAY_SIZE(data.states)) {
f3898ea1
EH		 283 count = -EINVAL;
284 goto fail;
285 }
286
041bf022
DC		 287 amdgpu_dpm_get_pp_num_states(adev, &data);
288 state = data.states[idx];
289 /* only set user selected power states */
290 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
291 state != POWER_STATE_TYPE_DEFAULT) {
292 amdgpu_dpm_dispatch_task(adev,
293 AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
294 adev->pp_force_state_enabled = true;
f3898ea1
EH		 295 }
296 }
297fail:
298 return count;
299}
300
301static ssize_t amdgpu_get_pp_table(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304{
305 struct drm_device *ddev = dev_get_drvdata(dev);
306 struct amdgpu_device *adev = ddev->dev_private;
307 char *table = NULL;
308 int size, i;
309
310 if (adev->pp_enabled)
311 size = amdgpu_dpm_get_pp_table(adev, &table);
312 else
313 return 0;
314
315 if (size >= PAGE_SIZE)
316 size = PAGE_SIZE - 1;
317
318 for (i = 0; i < size; i++) {
319 sprintf(buf + i, "%02x", table[i]);
320 }
321 sprintf(buf + i, "\n");
322
323 return size;
324}
325
326static ssize_t amdgpu_set_pp_table(struct device *dev,
327 struct device_attribute *attr,
328 const char *buf,
329 size_t count)
330{
331 struct drm_device *ddev = dev_get_drvdata(dev);
332 struct amdgpu_device *adev = ddev->dev_private;
333
334 if (adev->pp_enabled)
335 amdgpu_dpm_set_pp_table(adev, buf, count);
336
337 return count;
338}
339
340static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
341 struct device_attribute *attr,
342 char *buf)
343{
344 struct drm_device *ddev = dev_get_drvdata(dev);
345 struct amdgpu_device *adev = ddev->dev_private;
346 ssize_t size = 0;
347
348 if (adev->pp_enabled)
349 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
c85e299f
EH		 350 else if (adev->pm.funcs->print_clock_levels)
351 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
f3898ea1
EH		 352
353 return size;
354}
355
356static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
360{
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct amdgpu_device *adev = ddev->dev_private;
363 int ret;
364 long level;
5632708f
EH		 365 uint32_t i, mask = 0;
366 char sub_str[2];
f3898ea1 367
14b33074
EH		 368 for (i = 0; i < strlen(buf); i++) {
369 if (*(buf + i) == '\n')
370 continue;
5632708f
EH		 371 sub_str[0] = *(buf + i);
372 sub_str[1] = '\0';
373 ret = kstrtol(sub_str, 0, &level);
f3898ea1 374
5632708f
EH		 375 if (ret) {
376 count = -EINVAL;
377 goto fail;
378 }
379 mask |= 1 << level;
f3898ea1
EH		 380 }
381
382 if (adev->pp_enabled)
5632708f 383 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
c85e299f
EH		 384 else if (adev->pm.funcs->force_clock_level)
385 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
f3898ea1
EH		 386fail:
387 return count;
388}
389
390static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
391 struct device_attribute *attr,
392 char *buf)
393{
394 struct drm_device *ddev = dev_get_drvdata(dev);
395 struct amdgpu_device *adev = ddev->dev_private;
396 ssize_t size = 0;
397
398 if (adev->pp_enabled)
399 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
c85e299f
EH		 400 else if (adev->pm.funcs->print_clock_levels)
401 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
f3898ea1
EH		 402
403 return size;
404}
405
406static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
407 struct device_attribute *attr,
408 const char *buf,
409 size_t count)
410{
411 struct drm_device *ddev = dev_get_drvdata(dev);
412 struct amdgpu_device *adev = ddev->dev_private;
413 int ret;
414 long level;
5632708f
EH		 415 uint32_t i, mask = 0;
416 char sub_str[2];
f3898ea1 417
14b33074
EH		 418 for (i = 0; i < strlen(buf); i++) {
419 if (*(buf + i) == '\n')
420 continue;
5632708f
EH		 421 sub_str[0] = *(buf + i);
422 sub_str[1] = '\0';
423 ret = kstrtol(sub_str, 0, &level);
f3898ea1 424
5632708f
EH		 425 if (ret) {
426 count = -EINVAL;
427 goto fail;
428 }
429 mask |= 1 << level;
f3898ea1
EH		 430 }
431
432 if (adev->pp_enabled)
5632708f 433 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
c85e299f
EH		 434 else if (adev->pm.funcs->force_clock_level)
435 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
f3898ea1
EH		 436fail:
437 return count;
438}
439
440static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
441 struct device_attribute *attr,
442 char *buf)
443{
444 struct drm_device *ddev = dev_get_drvdata(dev);
445 struct amdgpu_device *adev = ddev->dev_private;
446 ssize_t size = 0;
447
448 if (adev->pp_enabled)
449 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
c85e299f
EH		 450 else if (adev->pm.funcs->print_clock_levels)
451 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
f3898ea1
EH		 452
453 return size;
454}
455
456static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
457 struct device_attribute *attr,
458 const char *buf,
459 size_t count)
460{
461 struct drm_device *ddev = dev_get_drvdata(dev);
462 struct amdgpu_device *adev = ddev->dev_private;
463 int ret;
464 long level;
5632708f
EH		 465 uint32_t i, mask = 0;
466 char sub_str[2];
f3898ea1 467
14b33074
EH		 468 for (i = 0; i < strlen(buf); i++) {
469 if (*(buf + i) == '\n')
470 continue;
5632708f
EH		 471 sub_str[0] = *(buf + i);
472 sub_str[1] = '\0';
473 ret = kstrtol(sub_str, 0, &level);
f3898ea1 474
5632708f
EH		 475 if (ret) {
476 count = -EINVAL;
477 goto fail;
478 }
479 mask |= 1 << level;
f3898ea1
EH		 480 }
481
482 if (adev->pp_enabled)
5632708f 483 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
c85e299f
EH		 484 else if (adev->pm.funcs->force_clock_level)
485 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
f3898ea1
EH		 486fail:
487 return count;
488}
489
428bafa8
EH		 490static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
491 struct device_attribute *attr,
492 char *buf)
493{
494 struct drm_device *ddev = dev_get_drvdata(dev);
495 struct amdgpu_device *adev = ddev->dev_private;
496 uint32_t value = 0;
497
498 if (adev->pp_enabled)
499 value = amdgpu_dpm_get_sclk_od(adev);
8b2e574d
EH		 500 else if (adev->pm.funcs->get_sclk_od)
501 value = adev->pm.funcs->get_sclk_od(adev);
428bafa8
EH		 502
503 return snprintf(buf, PAGE_SIZE, "%d\n", value);
504}
505
506static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
507 struct device_attribute *attr,
508 const char *buf,
509 size_t count)
510{
511 struct drm_device *ddev = dev_get_drvdata(dev);
512 struct amdgpu_device *adev = ddev->dev_private;
513 int ret;
514 long int value;
515
516 ret = kstrtol(buf, 0, &value);
517
518 if (ret) {
519 count = -EINVAL;
520 goto fail;
521 }
522
8b2e574d 523 if (adev->pp_enabled) {
428bafa8 524 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
8b2e574d
EH		 525 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
526 } else if (adev->pm.funcs->set_sclk_od) {
527 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
528 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
529 amdgpu_pm_compute_clocks(adev);
530 }
428bafa8
EH		 531
532fail:
533 return count;
534}
535
f2bdc05f
EH		 536static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
537 struct device_attribute *attr,
538 char *buf)
539{
540 struct drm_device *ddev = dev_get_drvdata(dev);
541 struct amdgpu_device *adev = ddev->dev_private;
542 uint32_t value = 0;
543
544 if (adev->pp_enabled)
545 value = amdgpu_dpm_get_mclk_od(adev);
546 else if (adev->pm.funcs->get_mclk_od)
547 value = adev->pm.funcs->get_mclk_od(adev);
548
549 return snprintf(buf, PAGE_SIZE, "%d\n", value);
550}
551
552static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
553 struct device_attribute *attr,
554 const char *buf,
555 size_t count)
556{
557 struct drm_device *ddev = dev_get_drvdata(dev);
558 struct amdgpu_device *adev = ddev->dev_private;
559 int ret;
560 long int value;
561
562 ret = kstrtol(buf, 0, &value);
563
564 if (ret) {
565 count = -EINVAL;
566 goto fail;
567 }
568
569 if (adev->pp_enabled) {
570 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
571 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
572 } else if (adev->pm.funcs->set_mclk_od) {
573 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
574 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
575 amdgpu_pm_compute_clocks(adev);
576 }
577
578fail:
579 return count;
580}
581
d38ceaf9
AD		 582static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
583static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
584 amdgpu_get_dpm_forced_performance_level,
585 amdgpu_set_dpm_forced_performance_level);
f3898ea1
EH		 586static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
587static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
588static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
589 amdgpu_get_pp_force_state,
590 amdgpu_set_pp_force_state);
591static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
592 amdgpu_get_pp_table,
593 amdgpu_set_pp_table);
594static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
595 amdgpu_get_pp_dpm_sclk,
596 amdgpu_set_pp_dpm_sclk);
597static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
598 amdgpu_get_pp_dpm_mclk,
599 amdgpu_set_pp_dpm_mclk);
600static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
601 amdgpu_get_pp_dpm_pcie,
602 amdgpu_set_pp_dpm_pcie);
428bafa8
EH		 603static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
604 amdgpu_get_pp_sclk_od,
605 amdgpu_set_pp_sclk_od);
f2bdc05f
EH		 606static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
607 amdgpu_get_pp_mclk_od,
608 amdgpu_set_pp_mclk_od);
d38ceaf9
AD		 609
610static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
611 struct device_attribute *attr,
612 char *buf)
613{
614 struct amdgpu_device *adev = dev_get_drvdata(dev);
0c67df48 615 struct drm_device *ddev = adev->ddev;
d38ceaf9
AD		 616 int temp;
617
0c67df48
AD		 618 /* Can't get temperature when the card is off */
619 if ((adev->flags & AMD_IS_PX) &&
620 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
621 return -EINVAL;
622
e61710c5 623 if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
d38ceaf9 624 temp = 0;
8804b8d5
RZ		 625 else
626 temp = amdgpu_dpm_get_temperature(adev);
d38ceaf9
AD		 627
628 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
629}
630
631static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
632 struct device_attribute *attr,
633 char *buf)
634{
635 struct amdgpu_device *adev = dev_get_drvdata(dev);
636 int hyst = to_sensor_dev_attr(attr)->index;
637 int temp;
638
639 if (hyst)
640 temp = adev->pm.dpm.thermal.min_temp;
641 else
642 temp = adev->pm.dpm.thermal.max_temp;
643
644 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
645}
646
647static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
648 struct device_attribute *attr,
649 char *buf)
650{
651 struct amdgpu_device *adev = dev_get_drvdata(dev);
652 u32 pwm_mode = 0;
653
e61710c5 654 if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
8804b8d5
RZ		 655 return -EINVAL;
656
657 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
d38ceaf9
AD		 658
659 /* never 0 (full-speed), fuse or smc-controlled always */
660 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
661}
662
663static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
664 struct device_attribute *attr,
665 const char *buf,
666 size_t count)
667{
668 struct amdgpu_device *adev = dev_get_drvdata(dev);
669 int err;
670 int value;
671
e61710c5 672 if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
d38ceaf9
AD		 673 return -EINVAL;
674
675 err = kstrtoint(buf, 10, &value);
676 if (err)
677 return err;
678
679 switch (value) {
680 case 1: /* manual, percent-based */
681 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
682 break;
683 default: /* disable */
684 amdgpu_dpm_set_fan_control_mode(adev, 0);
685 break;
686 }
687
688 return count;
689}
690
691static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
692 struct device_attribute *attr,
693 char *buf)
694{
695 return sprintf(buf, "%i\n", 0);
696}
697
698static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
699 struct device_attribute *attr,
700 char *buf)
701{
702 return sprintf(buf, "%i\n", 255);
703}
704
705static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
706 struct device_attribute *attr,
707 const char *buf, size_t count)
708{
709 struct amdgpu_device *adev = dev_get_drvdata(dev);
710 int err;
711 u32 value;
712
713 err = kstrtou32(buf, 10, &value);
714 if (err)
715 return err;
716
717 value = (value * 100) / 255;
718
719 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
720 if (err)
721 return err;
722
723 return count;
724}
725
726static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
727 struct device_attribute *attr,
728 char *buf)
729{
730 struct amdgpu_device *adev = dev_get_drvdata(dev);
731 int err;
732 u32 speed;
733
734 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
735 if (err)
736 return err;
737
738 speed = (speed * 255) / 100;
739
740 return sprintf(buf, "%i\n", speed);
741}
742
743static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
744static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
745static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
746static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
747static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
748static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
749static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
750
751static struct attribute *hwmon_attributes[] = {
752 &sensor_dev_attr_temp1_input.dev_attr.attr,
753 &sensor_dev_attr_temp1_crit.dev_attr.attr,
754 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
755 &sensor_dev_attr_pwm1.dev_attr.attr,
756 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
757 &sensor_dev_attr_pwm1_min.dev_attr.attr,
758 &sensor_dev_attr_pwm1_max.dev_attr.attr,
759 NULL
760};
761
762static umode_t hwmon_attributes_visible(struct kobject *kobj,
763 struct attribute *attr, int index)
764{
cc29ec87 765 struct device *dev = kobj_to_dev(kobj);
d38ceaf9
AD		 766 struct amdgpu_device *adev = dev_get_drvdata(dev);
767 umode_t effective_mode = attr->mode;
768
1b5708ff 769 /* Skip limit attributes if DPM is not enabled */
d38ceaf9
AD		 770 if (!adev->pm.dpm_enabled &&
771 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
27100735
AD		 772 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
773 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
774 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
775 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
776 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
d38ceaf9
AD		 777 return 0;
778
e61710c5 779 if (adev->pp_enabled)
8804b8d5
RZ		 780 return effective_mode;
781
d38ceaf9
AD		 782 /* Skip fan attributes if fan is not present */
783 if (adev->pm.no_fan &&
784 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
785 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
786 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
787 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
788 return 0;
789
790 /* mask fan attributes if we have no bindings for this asic to expose */
791 if ((!adev->pm.funcs->get_fan_speed_percent &&
792 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
793 (!adev->pm.funcs->get_fan_control_mode &&
794 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
795 effective_mode &= ~S_IRUGO;
796
797 if ((!adev->pm.funcs->set_fan_speed_percent &&
798 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
799 (!adev->pm.funcs->set_fan_control_mode &&
800 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
801 effective_mode &= ~S_IWUSR;
802
803 /* hide max/min values if we can't both query and manage the fan */
804 if ((!adev->pm.funcs->set_fan_speed_percent &&
805 !adev->pm.funcs->get_fan_speed_percent) &&
806 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
807 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
808 return 0;
809
810 return effective_mode;
811}
812
813static const struct attribute_group hwmon_attrgroup = {
814 .attrs = hwmon_attributes,
815 .is_visible = hwmon_attributes_visible,
816};
817
818static const struct attribute_group *hwmon_groups[] = {
819 &hwmon_attrgroup,
820 NULL
821};
822
823void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
824{
825 struct amdgpu_device *adev =
826 container_of(work, struct amdgpu_device,
827 pm.dpm.thermal.work);
828 /* switch to the thermal state */
3a2c788d 829 enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
d38ceaf9
AD		 830
831 if (!adev->pm.dpm_enabled)
832 return;
833
834 if (adev->pm.funcs->get_temperature) {
835 int temp = amdgpu_dpm_get_temperature(adev);
836
837 if (temp < adev->pm.dpm.thermal.min_temp)
838 /* switch back the user state */
839 dpm_state = adev->pm.dpm.user_state;
840 } else {
841 if (adev->pm.dpm.thermal.high_to_low)
842 /* switch back the user state */
843 dpm_state = adev->pm.dpm.user_state;
844 }
845 mutex_lock(&adev->pm.mutex);
846 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
847 adev->pm.dpm.thermal_active = true;
848 else
849 adev->pm.dpm.thermal_active = false;
850 adev->pm.dpm.state = dpm_state;
851 mutex_unlock(&adev->pm.mutex);
852
853 amdgpu_pm_compute_clocks(adev);
854}
855
856static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3a2c788d 857 enum amd_pm_state_type dpm_state)
d38ceaf9
AD		 858{
859 int i;
860 struct amdgpu_ps *ps;
861 u32 ui_class;
862 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
863 true : false;
864
865 /* check if the vblank period is too short to adjust the mclk */
866 if (single_display && adev->pm.funcs->vblank_too_short) {
867 if (amdgpu_dpm_vblank_too_short(adev))
868 single_display = false;
869 }
870
871 /* certain older asics have a separare 3D performance state,
872 * so try that first if the user selected performance
873 */
874 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
875 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
876 /* balanced states don't exist at the moment */
877 if (dpm_state == POWER_STATE_TYPE_BALANCED)
878 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
879
880restart_search:
881 /* Pick the best power state based on current conditions */
882 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
883 ps = &adev->pm.dpm.ps[i];
884 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
885 switch (dpm_state) {
886 /* user states */
887 case POWER_STATE_TYPE_BATTERY:
888 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
889 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
890 if (single_display)
891 return ps;
892 } else
893 return ps;
894 }
895 break;
896 case POWER_STATE_TYPE_BALANCED:
897 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
898 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
899 if (single_display)
900 return ps;
901 } else
902 return ps;
903 }
904 break;
905 case POWER_STATE_TYPE_PERFORMANCE:
906 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
907 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
908 if (single_display)
909 return ps;
910 } else
911 return ps;
912 }
913 break;
914 /* internal states */
915 case POWER_STATE_TYPE_INTERNAL_UVD:
916 if (adev->pm.dpm.uvd_ps)
917 return adev->pm.dpm.uvd_ps;
918 else
919 break;
920 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
921 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
922 return ps;
923 break;
924 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
925 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
926 return ps;
927 break;
928 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
929 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
930 return ps;
931 break;
932 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
933 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
934 return ps;
935 break;
936 case POWER_STATE_TYPE_INTERNAL_BOOT:
937 return adev->pm.dpm.boot_ps;
938 case POWER_STATE_TYPE_INTERNAL_THERMAL:
939 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
940 return ps;
941 break;
942 case POWER_STATE_TYPE_INTERNAL_ACPI:
943 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
944 return ps;
945 break;
946 case POWER_STATE_TYPE_INTERNAL_ULV:
947 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
948 return ps;
949 break;
950 case POWER_STATE_TYPE_INTERNAL_3DPERF:
951 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
952 return ps;
953 break;
954 default:
955 break;
956 }
957 }
958 /* use a fallback state if we didn't match */
959 switch (dpm_state) {
960 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
961 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
962 goto restart_search;
963 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
964 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
965 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
966 if (adev->pm.dpm.uvd_ps) {
967 return adev->pm.dpm.uvd_ps;
968 } else {
969 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
970 goto restart_search;
971 }
972 case POWER_STATE_TYPE_INTERNAL_THERMAL:
973 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
974 goto restart_search;
975 case POWER_STATE_TYPE_INTERNAL_ACPI:
976 dpm_state = POWER_STATE_TYPE_BATTERY;
977 goto restart_search;
978 case POWER_STATE_TYPE_BATTERY:
979 case POWER_STATE_TYPE_BALANCED:
980 case POWER_STATE_TYPE_INTERNAL_3DPERF:
981 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
982 goto restart_search;
983 default:
984 break;
985 }
986
987 return NULL;
988}
989
990static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
991{
992 int i;
993 struct amdgpu_ps *ps;
3a2c788d 994 enum amd_pm_state_type dpm_state;
d38ceaf9
AD		 995 int ret;
996
997 /* if dpm init failed */
998 if (!adev->pm.dpm_enabled)
999 return;
1000
1001 if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1002 /* add other state override checks here */
1003 if ((!adev->pm.dpm.thermal_active) &&
1004 (!adev->pm.dpm.uvd_active))
1005 adev->pm.dpm.state = adev->pm.dpm.user_state;
1006 }
1007 dpm_state = adev->pm.dpm.state;
1008
1009 ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1010 if (ps)
1011 adev->pm.dpm.requested_ps = ps;
1012 else
1013 return;
1014
1015 /* no need to reprogram if nothing changed unless we are on BTC+ */
1016 if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
1017 /* vce just modifies an existing state so force a change */
1018 if (ps->vce_active != adev->pm.dpm.vce_active)
1019 goto force;
2f7d10b3 1020 if (adev->flags & AMD_IS_APU) {
d38ceaf9
AD		 1021 /* for APUs if the num crtcs changed but state is the same,
1022 * all we need to do is update the display configuration.
1023 */
1024 if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
1025 /* update display watermarks based on new power state */
1026 amdgpu_display_bandwidth_update(adev);
1027 /* update displays */
1028 amdgpu_dpm_display_configuration_changed(adev);
1029 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1030 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1031 }
1032 return;
1033 } else {
1034 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1035 * nothing to do, if the num crtcs is > 1 and state is the same,
1036 * update display configuration.
1037 */
1038 if (adev->pm.dpm.new_active_crtcs ==
1039 adev->pm.dpm.current_active_crtcs) {
1040 return;
1041 } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
1042 (adev->pm.dpm.new_active_crtc_count > 1)) {
1043 /* update display watermarks based on new power state */
1044 amdgpu_display_bandwidth_update(adev);
1045 /* update displays */
1046 amdgpu_dpm_display_configuration_changed(adev);
1047 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1048 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1049 return;
1050 }
1051 }
1052 }
1053
1054force:
1055 if (amdgpu_dpm == 1) {
1056 printk("switching from power state:\n");
1057 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1058 printk("switching to power state:\n");
1059 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1060 }
1061
d38ceaf9
AD		 1062 /* update whether vce is active */
1063 ps->vce_active = adev->pm.dpm.vce_active;
1064
1065 ret = amdgpu_dpm_pre_set_power_state(adev);
1066 if (ret)
a27de35c 1067 return;
d38ceaf9
AD		 1068
1069 /* update display watermarks based on new power state */
1070 amdgpu_display_bandwidth_update(adev);
d38ceaf9
AD		 1071
1072 /* wait for the rings to drain */
1073 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1074 struct amdgpu_ring *ring = adev->rings[i];
1075 if (ring && ring->ready)
1076 amdgpu_fence_wait_empty(ring);
1077 }
1078
1079 /* program the new power state */
1080 amdgpu_dpm_set_power_state(adev);
1081
1082 /* update current power state */
1083 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
1084
1085 amdgpu_dpm_post_set_power_state(adev);
1086
8e7cedc6
AD		 1087 /* update displays */
1088 amdgpu_dpm_display_configuration_changed(adev);
1089
eda1d1cf
AD		 1090 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1091 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1092
d38ceaf9
AD		 1093 if (adev->pm.funcs->force_performance_level) {
1094 if (adev->pm.dpm.thermal_active) {
1095 enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
1096 /* force low perf level for thermal */
1097 amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
1098 /* save the user's level */
1099 adev->pm.dpm.forced_level = level;
1100 } else {
1101 /* otherwise, user selected level */
1102 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1103 }
1104 }
d38ceaf9
AD		 1105}
1106
1107void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1108{
e61710c5 1109 if (adev->pp_enabled)
d38ceaf9 1110 amdgpu_dpm_powergate_uvd(adev, !enable);
1b5708ff
RZ		 1111 else {
1112 if (adev->pm.funcs->powergate_uvd) {
d38ceaf9 1113 mutex_lock(&adev->pm.mutex);
1b5708ff
RZ		 1114 /* enable/disable UVD */
1115 amdgpu_dpm_powergate_uvd(adev, !enable);
d38ceaf9
AD		 1116 mutex_unlock(&adev->pm.mutex);
1117 } else {
1b5708ff
RZ		 1118 if (enable) {
1119 mutex_lock(&adev->pm.mutex);
1120 adev->pm.dpm.uvd_active = true;
1121 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1122 mutex_unlock(&adev->pm.mutex);
1123 } else {
1124 mutex_lock(&adev->pm.mutex);
1125 adev->pm.dpm.uvd_active = false;
1126 mutex_unlock(&adev->pm.mutex);
1127 }
1128 amdgpu_pm_compute_clocks(adev);
d38ceaf9
AD		 1129 }
1130
d38ceaf9
AD		 1131 }
1132}
1133
1134void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1135{
e61710c5 1136 if (adev->pp_enabled)
b7a07769 1137 amdgpu_dpm_powergate_vce(adev, !enable);
1b5708ff
RZ		 1138 else {
1139 if (adev->pm.funcs->powergate_vce) {
b7a07769 1140 mutex_lock(&adev->pm.mutex);
1b5708ff 1141 amdgpu_dpm_powergate_vce(adev, !enable);
b7a07769
SJ		 1142 mutex_unlock(&adev->pm.mutex);
1143 } else {
1b5708ff
RZ		 1144 if (enable) {
1145 mutex_lock(&adev->pm.mutex);
1146 adev->pm.dpm.vce_active = true;
1147 /* XXX select vce level based on ring/task */
1148 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
1149 mutex_unlock(&adev->pm.mutex);
1150 } else {
1151 mutex_lock(&adev->pm.mutex);
1152 adev->pm.dpm.vce_active = false;
1153 mutex_unlock(&adev->pm.mutex);
1154 }
1155 amdgpu_pm_compute_clocks(adev);
b7a07769 1156 }
b7a07769 1157 }
d38ceaf9
AD		 1158}
1159
1160void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1161{
1162 int i;
1163
e61710c5 1164 if (adev->pp_enabled)
1b5708ff
RZ		 1165 /* TO DO */
1166 return;
1167
1168 for (i = 0; i < adev->pm.dpm.num_ps; i++)
d38ceaf9 1169 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1b5708ff 1170
d38ceaf9
AD		 1171}
1172
1173int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1174{
1175 int ret;
1176
c86f5ebf
AD		 1177 if (adev->pm.sysfs_initialized)
1178 return 0;
1179
e61710c5 1180 if (!adev->pp_enabled) {
1b5708ff
RZ		 1181 if (adev->pm.funcs->get_temperature == NULL)
1182 return 0;
1183 }
1184
d38ceaf9
AD		 1185 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1186 DRIVER_NAME, adev,
1187 hwmon_groups);
1188 if (IS_ERR(adev->pm.int_hwmon_dev)) {
1189 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1190 dev_err(adev->dev,
1191 "Unable to register hwmon device: %d\n", ret);
1192 return ret;
1193 }
1194
1195 ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1196 if (ret) {
1197 DRM_ERROR("failed to create device file for dpm state\n");
1198 return ret;
1199 }
1200 ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1201 if (ret) {
1202 DRM_ERROR("failed to create device file for dpm state\n");
1203 return ret;
1204 }
f3898ea1
EH		 1205
1206 if (adev->pp_enabled) {
1207 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1208 if (ret) {
1209 DRM_ERROR("failed to create device file pp_num_states\n");
1210 return ret;
1211 }
1212 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1213 if (ret) {
1214 DRM_ERROR("failed to create device file pp_cur_state\n");
1215 return ret;
1216 }
1217 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1218 if (ret) {
1219 DRM_ERROR("failed to create device file pp_force_state\n");
1220 return ret;
1221 }
1222 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1223 if (ret) {
1224 DRM_ERROR("failed to create device file pp_table\n");
1225 return ret;
1226 }
f3898ea1 1227 }
c85e299f
EH		 1228
1229 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1230 if (ret) {
1231 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1232 return ret;
1233 }
1234 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1235 if (ret) {
1236 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1237 return ret;
1238 }
1239 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1240 if (ret) {
1241 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1242 return ret;
1243 }
8b2e574d
EH		 1244 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1245 if (ret) {
1246 DRM_ERROR("failed to create device file pp_sclk_od\n");
1247 return ret;
1248 }
f2bdc05f
EH		 1249 ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1250 if (ret) {
1251 DRM_ERROR("failed to create device file pp_mclk_od\n");
1252 return ret;
1253 }
c85e299f 1254
d38ceaf9
AD		 1255 ret = amdgpu_debugfs_pm_init(adev);
1256 if (ret) {
1257 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1258 return ret;
1259 }
1260
c86f5ebf
AD		 1261 adev->pm.sysfs_initialized = true;
1262
d38ceaf9
AD		 1263 return 0;
1264}
1265
1266void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1267{
1268 if (adev->pm.int_hwmon_dev)
1269 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1270 device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1271 device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
f3898ea1
EH		 1272 if (adev->pp_enabled) {
1273 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1274 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1275 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1276 device_remove_file(adev->dev, &dev_attr_pp_table);
f3898ea1 1277 }
c85e299f
EH		 1278 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1279 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1280 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
8b2e574d 1281 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
f2bdc05f 1282 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
d38ceaf9
AD		 1283}
1284
1285void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1286{
1287 struct drm_device *ddev = adev->ddev;
1288 struct drm_crtc *crtc;
1289 struct amdgpu_crtc *amdgpu_crtc;
1290
1291 if (!adev->pm.dpm_enabled)
1292 return;
1293
e61710c5 1294 if (adev->pp_enabled) {
1b5708ff
RZ		 1295 int i = 0;
1296
1297 amdgpu_display_bandwidth_update(adev);
a27de35c
CK		 1298 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1299 struct amdgpu_ring *ring = adev->rings[i];
1300 if (ring && ring->ready)
1301 amdgpu_fence_wait_empty(ring);
1302 }
d38ceaf9 1303
1b5708ff
RZ		 1304 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1305 } else {
1306 mutex_lock(&adev->pm.mutex);
1307 adev->pm.dpm.new_active_crtcs = 0;
1308 adev->pm.dpm.new_active_crtc_count = 0;
1309 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1310 list_for_each_entry(crtc,
1311 &ddev->mode_config.crtc_list, head) {
1312 amdgpu_crtc = to_amdgpu_crtc(crtc);
1313 if (crtc->enabled) {
1314 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1315 adev->pm.dpm.new_active_crtc_count++;
1316 }
d38ceaf9
AD		 1317 }
1318 }
1b5708ff
RZ		 1319 /* update battery/ac status */
1320 if (power_supply_is_system_supplied() > 0)
1321 adev->pm.dpm.ac_power = true;
1322 else
1323 adev->pm.dpm.ac_power = false;
d38ceaf9 1324
1b5708ff 1325 amdgpu_dpm_change_power_state_locked(adev);
d38ceaf9 1326
1b5708ff
RZ		 1327 mutex_unlock(&adev->pm.mutex);
1328 }
d38ceaf9
AD		 1329}
1330
1331/*
1332 * Debugfs info
1333 */
1334#if defined(CONFIG_DEBUG_FS)
1335
1336static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1337{
1338 struct drm_info_node *node = (struct drm_info_node *) m->private;
1339 struct drm_device *dev = node->minor->dev;
1340 struct amdgpu_device *adev = dev->dev_private;
0c67df48 1341 struct drm_device *ddev = adev->ddev;
d38ceaf9 1342
1b5708ff
RZ		 1343 if (!adev->pm.dpm_enabled) {
1344 seq_printf(m, "dpm not enabled\n");
1345 return 0;
1346 }
0c67df48
AD		 1347 if ((adev->flags & AMD_IS_PX) &&
1348 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1349 seq_printf(m, "PX asic powered off\n");
1350 } else if (adev->pp_enabled) {
1b5708ff
RZ		 1351 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1352 } else {
d38ceaf9
AD		 1353 mutex_lock(&adev->pm.mutex);
1354 if (adev->pm.funcs->debugfs_print_current_performance_level)
1355 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1356 else
1357 seq_printf(m, "Debugfs support not implemented for this asic\n");
1358 mutex_unlock(&adev->pm.mutex);
1359 }
1360
1361 return 0;
1362}
1363
06ab6832 1364static const struct drm_info_list amdgpu_pm_info_list[] = {
d38ceaf9
AD		 1365 {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1366};
1367#endif
1368
1369static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1370{
1371#if defined(CONFIG_DEBUG_FS)
1372 return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1373#else
1374 return 0;
1375#endif
1376}
Linux kernel - Deliverables
This page took 0.252865 seconds and 5 git commands to generate.