[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_sync.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Christian König <christian.koenig@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"

struct amdgpu_sync_entry {
	struct hlist_node	node;
	struct fence		*fence;
};

/**
 * amdgpu_sync_create - zero init sync object
 *
 * @sync: sync object to initialize
 *
 * Just clear the sync object for now.
 */
void amdgpu_sync_create(struct amdgpu_sync *sync)
{
	unsigned i;

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		sync->semaphores[i] = NULL;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		sync->sync_to[i] = NULL;

	hash_init(sync->fences);
	sync->last_vm_update = NULL;
}

static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (a_fence)
		return a_fence->ring->adev == adev;

	if (s_fence) {
		struct amdgpu_ring *ring;

		ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
		return ring->adev == adev;
	}

	return false;
}

static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	if (s_fence)
		return s_fence->owner == owner;
	if (a_fence)
		return a_fence->owner == owner;
	return false;
}

/**
 * amdgpu_sync_fence - remember to sync to this fence
 *
 * @sync: sync object to add fence to
 * @fence: fence to sync to
 *
 */
int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
		      struct fence *f)
{
	struct amdgpu_sync_entry *e;
	struct amdgpu_fence *fence;
	struct amdgpu_fence *other;
	struct fence *tmp, *later;

	if (!f)
		return 0;

	if (amdgpu_sync_same_dev(adev, f) &&
	    amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
		if (sync->last_vm_update) {
			tmp = sync->last_vm_update;
			BUG_ON(f->context != tmp->context);
			later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
			sync->last_vm_update = fence_get(later);
			fence_put(tmp);
		} else
			sync->last_vm_update = fence_get(f);
	}

	fence = to_amdgpu_fence(f);
	if (!fence || fence->ring->adev != adev) {
		hash_for_each_possible(sync->fences, e, node, f->context) {
			struct fence *new;
			if (unlikely(e->fence->context != f->context))
				continue;
			new = fence_get(fence_later(e->fence, f));
			if (new) {
				fence_put(e->fence);
				e->fence = new;
			}
			return 0;
		}

		e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
		if (!e)
			return -ENOMEM;

		hash_add(sync->fences, &e->node, f->context);
		e->fence = fence_get(f);
		return 0;
	}

	other = sync->sync_to[fence->ring->idx];
	sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
		amdgpu_fence_later(fence, other));
	amdgpu_fence_unref(&other);

	return 0;
}

static void *amdgpu_sync_get_owner(struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (s_fence)
		return s_fence->owner;
	else if (a_fence)
		return a_fence->owner;
	return AMDGPU_FENCE_OWNER_UNDEFINED;
}

/**
 * amdgpu_sync_resv - use the semaphores to sync to a reservation object
 *
 * @sync: sync object to add fences from reservation object to
 * @resv: reservation object with embedded fence
 * @shared: true if we should only sync to the exclusive fence
 *
 * Sync to the fence using the semaphore objects
 */
int amdgpu_sync_resv(struct amdgpu_device *adev,
		     struct amdgpu_sync *sync,
		     struct reservation_object *resv,
		     void *owner)
{
	struct reservation_object_list *flist;
	struct fence *f;
	void *fence_owner;
	unsigned i;
	int r = 0;

	if (resv == NULL)
		return -EINVAL;

	/* always sync to the exclusive fence */
	f = reservation_object_get_excl(resv);
	r = amdgpu_sync_fence(adev, sync, f);

	flist = reservation_object_get_list(resv);
	if (!flist || r)
		return r;

	for (i = 0; i < flist->shared_count; ++i) {
		f = rcu_dereference_protected(flist->shared[i],
					      reservation_object_held(resv));
		if (amdgpu_sync_same_dev(adev, f)) {
			/* VM updates are only interesting
			 * for other VM updates and moves.
			 */
			fence_owner = amdgpu_sync_get_owner(f);
			if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
			    (fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
			    ((owner == AMDGPU_FENCE_OWNER_VM) !=
			     (fence_owner == AMDGPU_FENCE_OWNER_VM)))
				continue;

			/* Ignore fence from the same owner as
			 * long as it isn't undefined.
			 */
			if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
			    fence_owner == owner)
				continue;
		}

		r = amdgpu_sync_fence(adev, sync, f);
		if (r)
			break;
	}
	return r;
}

struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	struct fence *f;
	int i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {

		f = e->fence;

		hash_del(&e->node);
		kfree(e);

		if (!fence_is_signaled(f))
			return f;

		fence_put(f);
	}
	return NULL;
}

int amdgpu_sync_wait(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	int i, r;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		r = fence_wait(e->fence, false);
		if (r)
			return r;

		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	if (amdgpu_enable_semaphores)
		return 0;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_fence *fence = sync->sync_to[i];
		if (!fence)
			continue;

		r = fence_wait(&fence->base, false);
		if (r)
			return r;
	}

	return 0;
}

/**
 * amdgpu_sync_rings - sync ring to all registered fences
 *
 * @sync: sync object to use
 * @ring: ring that needs sync
 *
 * Ensure that all registered fences are signaled before letting
 * the ring continue. The caller must hold the ring lock.
 */
int amdgpu_sync_rings(struct amdgpu_sync *sync,
		      struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;
	unsigned count = 0;
	int i, r;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_fence *fence = sync->sync_to[i];
		struct amdgpu_semaphore *semaphore;
		struct amdgpu_ring *other = adev->rings[i];

		/* check if we really need to sync */
		if (!amdgpu_fence_need_sync(fence, ring))
			continue;

		/* prevent GPU deadlocks */
		if (!other->ready) {
			dev_err(adev->dev, "Syncing to a disabled ring!");
			return -EINVAL;
		}

		if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores ||
		    (count >= AMDGPU_NUM_SYNCS)) {
			/* not enough room, wait manually */
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}
		r = amdgpu_semaphore_create(adev, &semaphore);
		if (r)
			return r;

		sync->semaphores[count++] = semaphore;

		/* allocate enough space for sync command */
		r = amdgpu_ring_alloc(other, 16);
		if (r)
			return r;

		/* emit the signal semaphore */
		if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
			/* signaling wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		/* we assume caller has already allocated space on waiters ring */
		if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
			/* waiting wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		amdgpu_ring_commit(other);
		amdgpu_fence_note_sync(fence, ring);
	}

	return 0;
}

/**
 * amdgpu_sync_free - free the sync object
 *
 * @adev: amdgpu_device pointer
 * @sync: sync object to use
 * @fence: fence to use for the free
 *
 * Free the sync object by freeing all semaphores in it.
 */
void amdgpu_sync_free(struct amdgpu_device *adev,
		      struct amdgpu_sync *sync,
		      struct fence *fence)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	unsigned i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		amdgpu_fence_unref(&sync->sync_to[i]);

	fence_put(sync->last_vm_update);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Christian König <christian.koenig@amd.com>
	29	*/
	30
	31	#include <drm/drmP.h>
	32	#include "amdgpu.h"
	33	#include "amdgpu_trace.h"
	34
f91b3a69 CK	35	struct amdgpu_sync_entry {
	36	struct hlist_node node;
	37	struct fence *fence;
	38	};
	39
d38ceaf9 AD	40	/**
	41	* amdgpu_sync_create - zero init sync object
	42	*
	43	* @sync: sync object to initialize
	44	*
	45	* Just clear the sync object for now.
	46	*/
	47	void amdgpu_sync_create(struct amdgpu_sync *sync)
	48	{
	49	unsigned i;
	50
	51	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	52	sync->semaphores[i] = NULL;
	53
	54	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	55	sync->sync_to[i] = NULL;
	56
f91b3a69	57	hash_init(sync->fences);
d38ceaf9 AD	58	sync->last_vm_update = NULL;
	59	}
	60
3c62338c CZ	61	static bool amdgpu_sync_same_dev(struct amdgpu_device adev, struct fence f)
	62	{
	63	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	64	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	65
	66	if (a_fence)
	67	return a_fence->ring->adev == adev;
4f839a24 CK	68
	69	if (s_fence) {
	70	struct amdgpu_ring *ring;
	71
	72	ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
	73	return ring->adev == adev;
	74	}
	75
3c62338c CZ	76	return false;
	77	}
	78
	79	static bool amdgpu_sync_test_owner(struct fence f, void owner)
	80	{
	81	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	82	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	83	if (s_fence)
	84	return s_fence->owner == owner;
	85	if (a_fence)
	86	return a_fence->owner == owner;
	87	return false;
	88	}
	89
d38ceaf9	90	/**
91e1a520	91	* amdgpu_sync_fence - remember to sync to this fence
d38ceaf9 AD	92	*
	93	* @sync: sync object to add fence to
	94	* @fence: fence to sync to
	95	*
d38ceaf9	96	*/
91e1a520 CK	97	int amdgpu_sync_fence(struct amdgpu_device adev, struct amdgpu_sync sync,
91e1a520 CK	98	struct fence *f)
d38ceaf9	99	{
f91b3a69	100	struct amdgpu_sync_entry *e;
91e1a520	101	struct amdgpu_fence *fence;
d38ceaf9	102	struct amdgpu_fence *other;
3c62338c	103	struct fence tmp, later;
d38ceaf9	104
91e1a520 CK	105	if (!f)
	106	return 0;
	107
3c62338c CZ	108	if (amdgpu_sync_same_dev(adev, f) &&
	109	amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
	110	if (sync->last_vm_update) {
	111	tmp = sync->last_vm_update;
	112	BUG_ON(f->context != tmp->context);
	113	later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
	114	sync->last_vm_update = fence_get(later);
	115	fence_put(tmp);
	116	} else
	117	sync->last_vm_update = fence_get(f);
	118	}
	119
91e1a520	120	fence = to_amdgpu_fence(f);
f91b3a69 CK	121	if (!fence \|\| fence->ring->adev != adev) {
	122	hash_for_each_possible(sync->fences, e, node, f->context) {
	123	struct fence *new;
	124	if (unlikely(e->fence->context != f->context))
	125	continue;
	126	new = fence_get(fence_later(e->fence, f));
	127	if (new) {
	128	fence_put(e->fence);
	129	e->fence = new;
	130	}
	131	return 0;
	132	}
	133
	134	e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
	135	if (!e)
	136	return -ENOMEM;
	137
	138	hash_add(sync->fences, &e->node, f->context);
	139	e->fence = fence_get(f);
	140	return 0;
	141	}
d38ceaf9 AD	142
	143	other = sync->sync_to[fence->ring->idx];
	144	sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
	145	amdgpu_fence_later(fence, other));
	146	amdgpu_fence_unref(&other);
	147
91e1a520	148	return 0;
d38ceaf9 AD	149	}
d38ceaf9 AD	150
423a9480 CZ	151	static void amdgpu_sync_get_owner(struct fence f)
	152	{
	153	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	154	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	155
	156	if (s_fence)
	157	return s_fence->owner;
	158	else if (a_fence)
	159	return a_fence->owner;
	160	return AMDGPU_FENCE_OWNER_UNDEFINED;
	161	}
	162
d38ceaf9 AD	163	/**
	164	* amdgpu_sync_resv - use the semaphores to sync to a reservation object
	165	*
	166	* @sync: sync object to add fences from reservation object to
	167	* @resv: reservation object with embedded fence
	168	* @shared: true if we should only sync to the exclusive fence
	169	*
	170	* Sync to the fence using the semaphore objects
	171	*/
	172	int amdgpu_sync_resv(struct amdgpu_device *adev,
	173	struct amdgpu_sync *sync,
	174	struct reservation_object *resv,
	175	void *owner)
	176	{
	177	struct reservation_object_list *flist;
	178	struct fence *f;
423a9480	179	void *fence_owner;
d38ceaf9 AD	180	unsigned i;
	181	int r = 0;
	182
4b095304 JZ	183	if (resv == NULL)
	184	return -EINVAL;
	185
d38ceaf9 AD	186	/* always sync to the exclusive fence */
d38ceaf9 AD	187	f = reservation_object_get_excl(resv);
91e1a520	188	r = amdgpu_sync_fence(adev, sync, f);
d38ceaf9 AD	189
	190	flist = reservation_object_get_list(resv);
	191	if (!flist \|\| r)
	192	return r;
	193
	194	for (i = 0; i < flist->shared_count; ++i) {
	195	f = rcu_dereference_protected(flist->shared[i],
	196	reservation_object_held(resv));
423a9480	197	if (amdgpu_sync_same_dev(adev, f)) {
1d3897e0 CK	198	/* VM updates are only interesting
	199	* for other VM updates and moves.
	200	*/
423a9480	201	fence_owner = amdgpu_sync_get_owner(f);
1d3897e0	202	if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
423a9480	203	(fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
1d3897e0	204	((owner == AMDGPU_FENCE_OWNER_VM) !=
423a9480	205	(fence_owner == AMDGPU_FENCE_OWNER_VM)))
91e1a520 CK	206	continue;
91e1a520 CK	207
1d3897e0 CK	208	/* Ignore fence from the same owner as
	209	* long as it isn't undefined.
	210	*/
	211	if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
423a9480	212	fence_owner == owner)
1d3897e0 CK	213	continue;
	214	}
	215
91e1a520 CK	216	r = amdgpu_sync_fence(adev, sync, f);
	217	if (r)
	218	break;
d38ceaf9 AD	219	}
	220	return r;
	221	}
	222
e61235db CK	223	struct fence amdgpu_sync_get_fence(struct amdgpu_sync sync)
	224	{
	225	struct amdgpu_sync_entry *e;
	226	struct hlist_node *tmp;
	227	struct fence *f;
	228	int i;
	229
	230	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	231
	232	f = e->fence;
	233
	234	hash_del(&e->node);
	235	kfree(e);
	236
	237	if (!fence_is_signaled(f))
	238	return f;
	239
	240	fence_put(f);
	241	}
	242	return NULL;
	243	}
	244
f91b3a69 CK	245	int amdgpu_sync_wait(struct amdgpu_sync *sync)
	246	{
	247	struct amdgpu_sync_entry *e;
	248	struct hlist_node *tmp;
	249	int i, r;
	250
	251	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	252	r = fence_wait(e->fence, false);
	253	if (r)
	254	return r;
	255
	256	hash_del(&e->node);
	257	fence_put(e->fence);
	258	kfree(e);
	259	}
3daea9e3 CK	260
	261	if (amdgpu_enable_semaphores)
	262	return 0;
	263
	264	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
	265	struct amdgpu_fence *fence = sync->sync_to[i];
	266	if (!fence)
	267	continue;
	268
	269	r = fence_wait(&fence->base, false);
	270	if (r)
	271	return r;
	272	}
	273
f91b3a69 CK	274	return 0;
	275	}
	276
d38ceaf9 AD	277	/**
	278	* amdgpu_sync_rings - sync ring to all registered fences
	279	*
	280	* @sync: sync object to use
	281	* @ring: ring that needs sync
	282	*
	283	* Ensure that all registered fences are signaled before letting
	284	* the ring continue. The caller must hold the ring lock.
	285	*/
	286	int amdgpu_sync_rings(struct amdgpu_sync *sync,
	287	struct amdgpu_ring *ring)
	288	{
	289	struct amdgpu_device *adev = ring->adev;
	290	unsigned count = 0;
	291	int i, r;
	292
	293	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
	294	struct amdgpu_fence *fence = sync->sync_to[i];
	295	struct amdgpu_semaphore *semaphore;
	296	struct amdgpu_ring *other = adev->rings[i];
	297
	298	/* check if we really need to sync */
	299	if (!amdgpu_fence_need_sync(fence, ring))
	300	continue;
	301
	302	/* prevent GPU deadlocks */
	303	if (!other->ready) {
	304	dev_err(adev->dev, "Syncing to a disabled ring!");
	305	return -EINVAL;
	306	}
	307
3daea9e3 CK	308	if (amdgpu_enable_scheduler \|\| !amdgpu_enable_semaphores \|\|
3daea9e3 CK	309	(count >= AMDGPU_NUM_SYNCS)) {
d38ceaf9	310	/* not enough room, wait manually */
02bc0650	311	r = fence_wait(&fence->base, false);
d38ceaf9 AD	312	if (r)
	313	return r;
	314	continue;
	315	}
	316	r = amdgpu_semaphore_create(adev, &semaphore);
	317	if (r)
	318	return r;
	319
	320	sync->semaphores[count++] = semaphore;
	321
	322	/* allocate enough space for sync command */
	323	r = amdgpu_ring_alloc(other, 16);
	324	if (r)
	325	return r;
	326
	327	/* emit the signal semaphore */
	328	if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
	329	/* signaling wasn't successful wait manually */
	330	amdgpu_ring_undo(other);
02bc0650	331	r = fence_wait(&fence->base, false);
d38ceaf9 AD	332	if (r)
	333	return r;
	334	continue;
	335	}
	336
	337	/* we assume caller has already allocated space on waiters ring */
	338	if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
	339	/* waiting wasn't successful wait manually */
	340	amdgpu_ring_undo(other);
02bc0650	341	r = fence_wait(&fence->base, false);
d38ceaf9 AD	342	if (r)
	343	return r;
	344	continue;
	345	}
	346
	347	amdgpu_ring_commit(other);
	348	amdgpu_fence_note_sync(fence, ring);
	349	}
	350
	351	return 0;
	352	}
	353
	354	/**
	355	* amdgpu_sync_free - free the sync object
	356	*
	357	* @adev: amdgpu_device pointer
	358	* @sync: sync object to use
	359	* @fence: fence to use for the free
	360	*
	361	* Free the sync object by freeing all semaphores in it.
	362	*/
	363	void amdgpu_sync_free(struct amdgpu_device *adev,
	364	struct amdgpu_sync *sync,
4ce9891e	365	struct fence *fence)
d38ceaf9	366	{
f91b3a69 CK	367	struct amdgpu_sync_entry *e;
f91b3a69 CK	368	struct hlist_node *tmp;
d38ceaf9 AD	369	unsigned i;
d38ceaf9 AD	370
f91b3a69 CK	371	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	372	hash_del(&e->node);
	373	fence_put(e->fence);
	374	kfree(e);
	375	}
	376
d38ceaf9 AD	377	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	378	amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
	379
	380	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	381	amdgpu_fence_unref(&sync->sync_to[i]);
	382
3c62338c	383	fence_put(sync->last_vm_update);
d38ceaf9	384	}