[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_sync.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Christian König <christian.koenig@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"

struct amdgpu_sync_entry {
	struct hlist_node	node;
	struct fence		*fence;
};

/**
 * amdgpu_sync_create - zero init sync object
 *
 * @sync: sync object to initialize
 *
 * Just clear the sync object for now.
 */
void amdgpu_sync_create(struct amdgpu_sync *sync)
{
	unsigned i;

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		sync->semaphores[i] = NULL;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		sync->sync_to[i] = NULL;

	hash_init(sync->fences);
	sync->last_vm_update = NULL;
}

static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (a_fence)
		return a_fence->ring->adev == adev;

	if (s_fence) {
		struct amdgpu_ring *ring;

		ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
		return ring->adev == adev;
	}

	return false;
}

static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	if (s_fence)
		return s_fence->owner == owner;
	if (a_fence)
		return a_fence->owner == owner;
	return false;
}

static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence)
{
	if (*keep && fence_is_later(*keep, fence))
		return;

	fence_put(*keep);
	*keep = fence_get(fence);
}

/**
 * amdgpu_sync_fence - remember to sync to this fence
 *
 * @sync: sync object to add fence to
 * @fence: fence to sync to
 *
 */
int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
		      struct fence *f)
{
	struct amdgpu_sync_entry *e;
	struct amdgpu_fence *fence;

	if (!f)
		return 0;

	if (amdgpu_sync_same_dev(adev, f) &&
	    amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM))
		amdgpu_sync_keep_later(&sync->last_vm_update, f);

	fence = to_amdgpu_fence(f);
	if (!fence || fence->ring->adev != adev) {
		hash_for_each_possible(sync->fences, e, node, f->context) {
			if (unlikely(e->fence->context != f->context))
				continue;

			amdgpu_sync_keep_later(&e->fence, f);
			return 0;
		}

		e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
		if (!e)
			return -ENOMEM;

		hash_add(sync->fences, &e->node, f->context);
		e->fence = fence_get(f);
		return 0;
	}

	amdgpu_sync_keep_later(&sync->sync_to[fence->ring->idx], f);

	return 0;
}

static void *amdgpu_sync_get_owner(struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (s_fence)
		return s_fence->owner;
	else if (a_fence)
		return a_fence->owner;
	return AMDGPU_FENCE_OWNER_UNDEFINED;
}

/**
 * amdgpu_sync_resv - use the semaphores to sync to a reservation object
 *
 * @sync: sync object to add fences from reservation object to
 * @resv: reservation object with embedded fence
 * @shared: true if we should only sync to the exclusive fence
 *
 * Sync to the fence using the semaphore objects
 */
int amdgpu_sync_resv(struct amdgpu_device *adev,
		     struct amdgpu_sync *sync,
		     struct reservation_object *resv,
		     void *owner)
{
	struct reservation_object_list *flist;
	struct fence *f;
	void *fence_owner;
	unsigned i;
	int r = 0;

	if (resv == NULL)
		return -EINVAL;

	/* always sync to the exclusive fence */
	f = reservation_object_get_excl(resv);
	r = amdgpu_sync_fence(adev, sync, f);

	flist = reservation_object_get_list(resv);
	if (!flist || r)
		return r;

	for (i = 0; i < flist->shared_count; ++i) {
		f = rcu_dereference_protected(flist->shared[i],
					      reservation_object_held(resv));
		if (amdgpu_sync_same_dev(adev, f)) {
			/* VM updates are only interesting
			 * for other VM updates and moves.
			 */
			fence_owner = amdgpu_sync_get_owner(f);
			if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
			    (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
			    ((owner == AMDGPU_FENCE_OWNER_VM) !=
			     (fence_owner == AMDGPU_FENCE_OWNER_VM)))
				continue;

			/* Ignore fence from the same owner as
			 * long as it isn't undefined.
			 */
			if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
			    fence_owner == owner)
				continue;
		}

		r = amdgpu_sync_fence(adev, sync, f);
		if (r)
			break;
	}
	return r;
}

struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	struct fence *f;
	int i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {

		f = e->fence;

		hash_del(&e->node);
		kfree(e);

		if (!fence_is_signaled(f))
			return f;

		fence_put(f);
	}
	return NULL;
}

int amdgpu_sync_wait(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	int i, r;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		r = fence_wait(e->fence, false);
		if (r)
			return r;

		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	if (amdgpu_enable_semaphores)
		return 0;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct fence *fence = sync->sync_to[i];
		if (!fence)
			continue;

		r = fence_wait(fence, false);
		if (r)
			return r;
	}

	return 0;
}

/**
 * amdgpu_sync_rings - sync ring to all registered fences
 *
 * @sync: sync object to use
 * @ring: ring that needs sync
 *
 * Ensure that all registered fences are signaled before letting
 * the ring continue. The caller must hold the ring lock.
 */
int amdgpu_sync_rings(struct amdgpu_sync *sync,
		      struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;
	unsigned count = 0;
	int i, r;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_ring *other = adev->rings[i];
		struct amdgpu_semaphore *semaphore;
		struct amdgpu_fence *fence;

		if (!sync->sync_to[i])
			continue;

		fence = to_amdgpu_fence(sync->sync_to[i]);

		/* check if we really need to sync */
		if (!amdgpu_fence_need_sync(fence, ring))
			continue;

		/* prevent GPU deadlocks */
		if (!other->ready) {
			dev_err(adev->dev, "Syncing to a disabled ring!");
			return -EINVAL;
		}

		if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores ||
		    (count >= AMDGPU_NUM_SYNCS)) {
			/* not enough room, wait manually */
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}
		r = amdgpu_semaphore_create(adev, &semaphore);
		if (r)
			return r;

		sync->semaphores[count++] = semaphore;

		/* allocate enough space for sync command */
		r = amdgpu_ring_alloc(other, 16);
		if (r)
			return r;

		/* emit the signal semaphore */
		if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
			/* signaling wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		/* we assume caller has already allocated space on waiters ring */
		if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
			/* waiting wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		amdgpu_ring_commit(other);
		amdgpu_fence_note_sync(fence, ring);
	}

	return 0;
}

/**
 * amdgpu_sync_free - free the sync object
 *
 * @adev: amdgpu_device pointer
 * @sync: sync object to use
 * @fence: fence to use for the free
 *
 * Free the sync object by freeing all semaphores in it.
 */
void amdgpu_sync_free(struct amdgpu_device *adev,
		      struct amdgpu_sync *sync,
		      struct fence *fence)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	unsigned i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		fence_put(sync->sync_to[i]);

	fence_put(sync->last_vm_update);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Christian König <christian.koenig@amd.com>
	29	*/
	30
	31	#include <drm/drmP.h>
	32	#include "amdgpu.h"
	33	#include "amdgpu_trace.h"
	34
f91b3a69 CK	35	struct amdgpu_sync_entry {
	36	struct hlist_node node;
	37	struct fence *fence;
	38	};
	39
d38ceaf9 AD	40	/**
	41	* amdgpu_sync_create - zero init sync object
	42	*
	43	* @sync: sync object to initialize
	44	*
	45	* Just clear the sync object for now.
	46	*/
	47	void amdgpu_sync_create(struct amdgpu_sync *sync)
	48	{
	49	unsigned i;
	50
	51	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	52	sync->semaphores[i] = NULL;
	53
	54	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	55	sync->sync_to[i] = NULL;
	56
f91b3a69	57	hash_init(sync->fences);
d38ceaf9 AD	58	sync->last_vm_update = NULL;
	59	}
	60
3c62338c CZ	61	static bool amdgpu_sync_same_dev(struct amdgpu_device adev, struct fence f)
	62	{
	63	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	64	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	65
	66	if (a_fence)
	67	return a_fence->ring->adev == adev;
4f839a24 CK	68
	69	if (s_fence) {
	70	struct amdgpu_ring *ring;
	71
	72	ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
	73	return ring->adev == adev;
	74	}
	75
3c62338c CZ	76	return false;
	77	}
	78
	79	static bool amdgpu_sync_test_owner(struct fence f, void owner)
	80	{
	81	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	82	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	83	if (s_fence)
	84	return s_fence->owner == owner;
	85	if (a_fence)
	86	return a_fence->owner == owner;
	87	return false;
	88	}
	89
24233860 CK	90	static void amdgpu_sync_keep_later(struct fence *keep, struct fence fence)
	91	{
	92	if (keep && fence_is_later(keep, fence))
	93	return;
	94
	95	fence_put(*keep);
	96	*keep = fence_get(fence);
	97	}
	98
d38ceaf9	99	/**
91e1a520	100	* amdgpu_sync_fence - remember to sync to this fence
d38ceaf9 AD	101	*
	102	* @sync: sync object to add fence to
	103	* @fence: fence to sync to
	104	*
d38ceaf9	105	*/
91e1a520 CK	106	int amdgpu_sync_fence(struct amdgpu_device adev, struct amdgpu_sync sync,
91e1a520 CK	107	struct fence *f)
d38ceaf9	108	{
f91b3a69	109	struct amdgpu_sync_entry *e;
91e1a520	110	struct amdgpu_fence *fence;
d38ceaf9	111
91e1a520 CK	112	if (!f)
	113	return 0;
	114
3c62338c	115	if (amdgpu_sync_same_dev(adev, f) &&
24233860 CK	116	amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM))
24233860 CK	117	amdgpu_sync_keep_later(&sync->last_vm_update, f);
3c62338c	118
91e1a520	119	fence = to_amdgpu_fence(f);
f91b3a69 CK	120	if (!fence \|\| fence->ring->adev != adev) {
f91b3a69 CK	121	hash_for_each_possible(sync->fences, e, node, f->context) {
f91b3a69 CK	122	if (unlikely(e->fence->context != f->context))
f91b3a69 CK	123	continue;
24233860 CK	124
24233860 CK	125	amdgpu_sync_keep_later(&e->fence, f);
f91b3a69 CK	126	return 0;
	127	}
	128
	129	e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
	130	if (!e)
	131	return -ENOMEM;
	132
	133	hash_add(sync->fences, &e->node, f->context);
	134	e->fence = fence_get(f);
	135	return 0;
	136	}
d38ceaf9	137
16545c32	138	amdgpu_sync_keep_later(&sync->sync_to[fence->ring->idx], f);
d38ceaf9	139
91e1a520	140	return 0;
d38ceaf9 AD	141	}
d38ceaf9 AD	142
423a9480 CZ	143	static void amdgpu_sync_get_owner(struct fence f)
	144	{
	145	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	146	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	147
	148	if (s_fence)
	149	return s_fence->owner;
	150	else if (a_fence)
	151	return a_fence->owner;
	152	return AMDGPU_FENCE_OWNER_UNDEFINED;
	153	}
	154
d38ceaf9 AD	155	/**
	156	* amdgpu_sync_resv - use the semaphores to sync to a reservation object
	157	*
	158	* @sync: sync object to add fences from reservation object to
	159	* @resv: reservation object with embedded fence
	160	* @shared: true if we should only sync to the exclusive fence
	161	*
	162	* Sync to the fence using the semaphore objects
	163	*/
	164	int amdgpu_sync_resv(struct amdgpu_device *adev,
	165	struct amdgpu_sync *sync,
	166	struct reservation_object *resv,
	167	void *owner)
	168	{
	169	struct reservation_object_list *flist;
	170	struct fence *f;
423a9480	171	void *fence_owner;
d38ceaf9 AD	172	unsigned i;
	173	int r = 0;
	174
4b095304 JZ	175	if (resv == NULL)
	176	return -EINVAL;
	177
d38ceaf9 AD	178	/* always sync to the exclusive fence */
d38ceaf9 AD	179	f = reservation_object_get_excl(resv);
91e1a520	180	r = amdgpu_sync_fence(adev, sync, f);
d38ceaf9 AD	181
	182	flist = reservation_object_get_list(resv);
	183	if (!flist \|\| r)
	184	return r;
	185
	186	for (i = 0; i < flist->shared_count; ++i) {
	187	f = rcu_dereference_protected(flist->shared[i],
	188	reservation_object_held(resv));
423a9480	189	if (amdgpu_sync_same_dev(adev, f)) {
1d3897e0 CK	190	/* VM updates are only interesting
	191	* for other VM updates and moves.
	192	*/
423a9480	193	fence_owner = amdgpu_sync_get_owner(f);
7a91d6cb CK	194	if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
7a91d6cb CK	195	(fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
1d3897e0	196	((owner == AMDGPU_FENCE_OWNER_VM) !=
423a9480	197	(fence_owner == AMDGPU_FENCE_OWNER_VM)))
91e1a520 CK	198	continue;
91e1a520 CK	199
1d3897e0 CK	200	/* Ignore fence from the same owner as
	201	* long as it isn't undefined.
	202	*/
	203	if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
423a9480	204	fence_owner == owner)
1d3897e0 CK	205	continue;
	206	}
	207
91e1a520 CK	208	r = amdgpu_sync_fence(adev, sync, f);
	209	if (r)
	210	break;
d38ceaf9 AD	211	}
	212	return r;
	213	}
	214
e61235db CK	215	struct fence amdgpu_sync_get_fence(struct amdgpu_sync sync)
	216	{
	217	struct amdgpu_sync_entry *e;
	218	struct hlist_node *tmp;
	219	struct fence *f;
	220	int i;
	221
	222	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	223
	224	f = e->fence;
	225
	226	hash_del(&e->node);
	227	kfree(e);
	228
	229	if (!fence_is_signaled(f))
	230	return f;
	231
	232	fence_put(f);
	233	}
	234	return NULL;
	235	}
	236
f91b3a69 CK	237	int amdgpu_sync_wait(struct amdgpu_sync *sync)
	238	{
	239	struct amdgpu_sync_entry *e;
	240	struct hlist_node *tmp;
	241	int i, r;
	242
	243	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	244	r = fence_wait(e->fence, false);
	245	if (r)
	246	return r;
	247
	248	hash_del(&e->node);
	249	fence_put(e->fence);
	250	kfree(e);
	251	}
3daea9e3 CK	252
	253	if (amdgpu_enable_semaphores)
	254	return 0;
	255
	256	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
16545c32	257	struct fence *fence = sync->sync_to[i];
3daea9e3 CK	258	if (!fence)
	259	continue;
	260
16545c32	261	r = fence_wait(fence, false);
3daea9e3 CK	262	if (r)
	263	return r;
	264	}
	265
f91b3a69 CK	266	return 0;
	267	}
	268
d38ceaf9 AD	269	/**
	270	* amdgpu_sync_rings - sync ring to all registered fences
	271	*
	272	* @sync: sync object to use
	273	* @ring: ring that needs sync
	274	*
	275	* Ensure that all registered fences are signaled before letting
	276	* the ring continue. The caller must hold the ring lock.
	277	*/
	278	int amdgpu_sync_rings(struct amdgpu_sync *sync,
	279	struct amdgpu_ring *ring)
	280	{
	281	struct amdgpu_device *adev = ring->adev;
	282	unsigned count = 0;
	283	int i, r;
	284
	285	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
d38ceaf9	286	struct amdgpu_ring *other = adev->rings[i];
16545c32 CK	287	struct amdgpu_semaphore *semaphore;
	288	struct amdgpu_fence *fence;
	289
	290	if (!sync->sync_to[i])
	291	continue;
	292
	293	fence = to_amdgpu_fence(sync->sync_to[i]);
d38ceaf9 AD	294
	295	/* check if we really need to sync */
	296	if (!amdgpu_fence_need_sync(fence, ring))
	297	continue;
	298
	299	/* prevent GPU deadlocks */
	300	if (!other->ready) {
	301	dev_err(adev->dev, "Syncing to a disabled ring!");
	302	return -EINVAL;
	303	}
	304
3daea9e3 CK	305	if (amdgpu_enable_scheduler \|\| !amdgpu_enable_semaphores \|\|
3daea9e3 CK	306	(count >= AMDGPU_NUM_SYNCS)) {
d38ceaf9	307	/* not enough room, wait manually */
02bc0650	308	r = fence_wait(&fence->base, false);
d38ceaf9 AD	309	if (r)
	310	return r;
	311	continue;
	312	}
	313	r = amdgpu_semaphore_create(adev, &semaphore);
	314	if (r)
	315	return r;
	316
	317	sync->semaphores[count++] = semaphore;
	318
	319	/* allocate enough space for sync command */
	320	r = amdgpu_ring_alloc(other, 16);
	321	if (r)
	322	return r;
	323
	324	/* emit the signal semaphore */
	325	if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
	326	/* signaling wasn't successful wait manually */
	327	amdgpu_ring_undo(other);
02bc0650	328	r = fence_wait(&fence->base, false);
d38ceaf9 AD	329	if (r)
	330	return r;
	331	continue;
	332	}
	333
	334	/* we assume caller has already allocated space on waiters ring */
	335	if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
	336	/* waiting wasn't successful wait manually */
	337	amdgpu_ring_undo(other);
02bc0650	338	r = fence_wait(&fence->base, false);
d38ceaf9 AD	339	if (r)
	340	return r;
	341	continue;
	342	}
	343
	344	amdgpu_ring_commit(other);
	345	amdgpu_fence_note_sync(fence, ring);
	346	}
	347
	348	return 0;
	349	}
	350
	351	/**
	352	* amdgpu_sync_free - free the sync object
	353	*
	354	* @adev: amdgpu_device pointer
	355	* @sync: sync object to use
	356	* @fence: fence to use for the free
	357	*
	358	* Free the sync object by freeing all semaphores in it.
	359	*/
	360	void amdgpu_sync_free(struct amdgpu_device *adev,
	361	struct amdgpu_sync *sync,
4ce9891e	362	struct fence *fence)
d38ceaf9	363	{
f91b3a69 CK	364	struct amdgpu_sync_entry *e;
f91b3a69 CK	365	struct hlist_node *tmp;
d38ceaf9 AD	366	unsigned i;
d38ceaf9 AD	367
f91b3a69 CK	368	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	369	hash_del(&e->node);
	370	fence_put(e->fence);
	371	kfree(e);
	372	}
	373
d38ceaf9 AD	374	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	375	amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
	376
	377	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
16545c32	378	fence_put(sync->sync_to[i]);
d38ceaf9	379
3c62338c	380	fence_put(sync->last_vm_update);
d38ceaf9	381	}