[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_test.c

/*
 * Copyright 2009 VMware, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Michel Dänzer
 */
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"

/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
static void amdgpu_do_test_moves(struct amdgpu_device *adev)
{
	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
	struct amdgpu_bo *vram_obj = NULL;
	struct amdgpu_bo **gtt_obj = NULL;
	uint64_t gtt_addr, vram_addr;
	unsigned n, size;
	int i, r;

	size = 1024 * 1024;

	/* Number of tests =
	 * (Total GTT - IB pool - writeback page - ring buffers) / test size
	 */
	n = adev->mc.gtt_size - AMDGPU_IB_POOL_SIZE*64*1024;
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		if (adev->rings[i])
			n -= adev->rings[i]->ring_size;
	if (adev->wb.wb_obj)
		n -= AMDGPU_GPU_PAGE_SIZE;
	if (adev->irq.ih.ring_obj)
		n -= adev->irq.ih.ring_size;
	n /= size;

	gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
	if (!gtt_obj) {
		DRM_ERROR("Failed to allocate %d pointers\n", n);
		r = 1;
		goto out_cleanup;
	}

	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
			     AMDGPU_GEM_DOMAIN_VRAM, 0,
			     NULL, NULL, &vram_obj);
	if (r) {
		DRM_ERROR("Failed to create VRAM object\n");
		goto out_cleanup;
	}
	r = amdgpu_bo_reserve(vram_obj, false);
	if (unlikely(r != 0))
		goto out_unref;
	r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr);
	if (r) {
		DRM_ERROR("Failed to pin VRAM object\n");
		goto out_unres;
	}
	for (i = 0; i < n; i++) {
		void *gtt_map, *vram_map;
		void **gtt_start, **gtt_end;
		void **vram_start, **vram_end;
		struct fence *fence = NULL;

		r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
				     AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
				     NULL, gtt_obj + i);
		if (r) {
			DRM_ERROR("Failed to create GTT object %d\n", i);
			goto out_lclean;
		}

		r = amdgpu_bo_reserve(gtt_obj[i], false);
		if (unlikely(r != 0))
			goto out_lclean_unref;
		r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, &gtt_addr);
		if (r) {
			DRM_ERROR("Failed to pin GTT object %d\n", i);
			goto out_lclean_unres;
		}

		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
		if (r) {
			DRM_ERROR("Failed to map GTT object %d\n", i);
			goto out_lclean_unpin;
		}

		for (gtt_start = gtt_map, gtt_end = gtt_map + size;
		     gtt_start < gtt_end;
		     gtt_start++)
			*gtt_start = gtt_start;

		amdgpu_bo_kunmap(gtt_obj[i]);

		r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr,
				       size, NULL, &fence);

		if (r) {
			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
			goto out_lclean_unpin;
		}

		r = fence_wait(fence, false);
		if (r) {
			DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
			goto out_lclean_unpin;
		}

		fence_put(fence);

		r = amdgpu_bo_kmap(vram_obj, &vram_map);
		if (r) {
			DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
			goto out_lclean_unpin;
		}

		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
		     vram_start = vram_map, vram_end = vram_map + size;
		     vram_start < vram_end;
		     gtt_start++, vram_start++) {
			if (*vram_start != gtt_start) {
				DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
					  "expected 0x%p (GTT/VRAM offset "
					  "0x%16llx/0x%16llx)\n",
					  i, *vram_start, gtt_start,
					  (unsigned long long)
					  (gtt_addr - adev->mc.gtt_start +
					   (void*)gtt_start - gtt_map),
					  (unsigned long long)
					  (vram_addr - adev->mc.vram_start +
					   (void*)gtt_start - gtt_map));
				amdgpu_bo_kunmap(vram_obj);
				goto out_lclean_unpin;
			}
			*vram_start = vram_start;
		}

		amdgpu_bo_kunmap(vram_obj);

		r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr,
				       size, NULL, &fence);

		if (r) {
			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
			goto out_lclean_unpin;
		}

		r = fence_wait(fence, false);
		if (r) {
			DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
			goto out_lclean_unpin;
		}

		fence_put(fence);

		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
		if (r) {
			DRM_ERROR("Failed to map GTT object after copy %d\n", i);
			goto out_lclean_unpin;
		}

		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
		     vram_start = vram_map, vram_end = vram_map + size;
		     gtt_start < gtt_end;
		     gtt_start++, vram_start++) {
			if (*gtt_start != vram_start) {
				DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
					  "expected 0x%p (VRAM/GTT offset "
					  "0x%16llx/0x%16llx)\n",
					  i, *gtt_start, vram_start,
					  (unsigned long long)
					  (vram_addr - adev->mc.vram_start +
					   (void*)vram_start - vram_map),
					  (unsigned long long)
					  (gtt_addr - adev->mc.gtt_start +
					   (void*)vram_start - vram_map));
				amdgpu_bo_kunmap(gtt_obj[i]);
				goto out_lclean_unpin;
			}
		}

		amdgpu_bo_kunmap(gtt_obj[i]);

		DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
			 gtt_addr - adev->mc.gtt_start);
		continue;

out_lclean_unpin:
		amdgpu_bo_unpin(gtt_obj[i]);
out_lclean_unres:
		amdgpu_bo_unreserve(gtt_obj[i]);
out_lclean_unref:
		amdgpu_bo_unref(&gtt_obj[i]);
out_lclean:
		for (--i; i >= 0; --i) {
			amdgpu_bo_unpin(gtt_obj[i]);
			amdgpu_bo_unreserve(gtt_obj[i]);
			amdgpu_bo_unref(&gtt_obj[i]);
		}
		if (fence)
			fence_put(fence);
		break;
	}

	amdgpu_bo_unpin(vram_obj);
out_unres:
	amdgpu_bo_unreserve(vram_obj);
out_unref:
	amdgpu_bo_unref(&vram_obj);
out_cleanup:
	kfree(gtt_obj);
	if (r) {
		printk(KERN_WARNING "Error while testing BO move.\n");
	}
}

void amdgpu_test_moves(struct amdgpu_device *adev)
{
	if (adev->mman.buffer_funcs)
		amdgpu_do_test_moves(adev);
}

static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
					     struct amdgpu_ring *ring,
					     struct fence **fence)
{
	uint32_t handle = ring->idx ^ 0xdeafbeef;
	int r;

	if (ring == &adev->uvd.ring) {
		r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
		if (r) {
			DRM_ERROR("Failed to get dummy create msg\n");
			return r;
		}

		r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
		if (r) {
			DRM_ERROR("Failed to get dummy destroy msg\n");
			return r;
		}

	} else if (ring == &adev->vce.ring[0] ||
		   ring == &adev->vce.ring[1]) {
		r = amdgpu_vce_get_create_msg(ring, handle, NULL);
		if (r) {
			DRM_ERROR("Failed to get dummy create msg\n");
			return r;
		}

		r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
		if (r) {
			DRM_ERROR("Failed to get dummy destroy msg\n");
			return r;
		}
	} else {
		struct amdgpu_fence *a_fence = NULL;
		r = amdgpu_ring_lock(ring, 64);
		if (r) {
			DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
			return r;
		}
		amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence);
		amdgpu_ring_unlock_commit(ring);
		*fence = &a_fence->base;
	}
	return 0;
}

void amdgpu_test_ring_sync(struct amdgpu_device *adev,
			   struct amdgpu_ring *ringA,
			   struct amdgpu_ring *ringB)
{
	struct fence *fence1 = NULL, *fence2 = NULL;
	struct amdgpu_semaphore *semaphore = NULL;
	int r;

	r = amdgpu_semaphore_create(adev, &semaphore);
	if (r) {
		DRM_ERROR("Failed to create semaphore\n");
		goto out_cleanup;
	}

	r = amdgpu_ring_lock(ringA, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_wait(ringA, semaphore);
	amdgpu_ring_unlock_commit(ringA);

	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
	if (r)
		goto out_cleanup;

	r = amdgpu_ring_lock(ringA, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_wait(ringA, semaphore);
	amdgpu_ring_unlock_commit(ringA);

	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
	if (r)
		goto out_cleanup;

	mdelay(1000);

	if (fence_is_signaled(fence1)) {
		DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
		goto out_cleanup;
	}

	r = amdgpu_ring_lock(ringB, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring B %p\n", ringB);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_signal(ringB, semaphore);
	amdgpu_ring_unlock_commit(ringB);

	r = fence_wait(fence1, false);
	if (r) {
		DRM_ERROR("Failed to wait for sync fence 1\n");
		goto out_cleanup;
	}

	mdelay(1000);

	if (fence_is_signaled(fence2)) {
		DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
		goto out_cleanup;
	}

	r = amdgpu_ring_lock(ringB, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring B %p\n", ringB);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_signal(ringB, semaphore);
	amdgpu_ring_unlock_commit(ringB);

	r = fence_wait(fence2, false);
	if (r) {
		DRM_ERROR("Failed to wait for sync fence 1\n");
		goto out_cleanup;
	}

out_cleanup:
	amdgpu_semaphore_free(adev, &semaphore, NULL);

	if (fence1)
		fence_put(fence1);

	if (fence2)
		fence_put(fence2);

	if (r)
		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
}

static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
			    struct amdgpu_ring *ringA,
			    struct amdgpu_ring *ringB,
			    struct amdgpu_ring *ringC)
{
	struct fence *fenceA = NULL, *fenceB = NULL;
	struct amdgpu_semaphore *semaphore = NULL;
	bool sigA, sigB;
	int i, r;

	r = amdgpu_semaphore_create(adev, &semaphore);
	if (r) {
		DRM_ERROR("Failed to create semaphore\n");
		goto out_cleanup;
	}

	r = amdgpu_ring_lock(ringA, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_wait(ringA, semaphore);
	amdgpu_ring_unlock_commit(ringA);

	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
	if (r)
		goto out_cleanup;

	r = amdgpu_ring_lock(ringB, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_wait(ringB, semaphore);
	amdgpu_ring_unlock_commit(ringB);
	r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
	if (r)
		goto out_cleanup;

	mdelay(1000);

	if (fence_is_signaled(fenceA)) {
		DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
		goto out_cleanup;
	}
	if (fence_is_signaled(fenceB)) {
		DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
		goto out_cleanup;
	}

	r = amdgpu_ring_lock(ringC, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring B %p\n", ringC);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_signal(ringC, semaphore);
	amdgpu_ring_unlock_commit(ringC);

	for (i = 0; i < 30; ++i) {
		mdelay(100);
		sigA = fence_is_signaled(fenceA);
		sigB = fence_is_signaled(fenceB);
		if (sigA || sigB)
			break;
	}

	if (!sigA && !sigB) {
		DRM_ERROR("Neither fence A nor B has been signaled\n");
		goto out_cleanup;
	} else if (sigA && sigB) {
		DRM_ERROR("Both fence A and B has been signaled\n");
		goto out_cleanup;
	}

	DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');

	r = amdgpu_ring_lock(ringC, 64);
	if (r) {
		DRM_ERROR("Failed to lock ring B %p\n", ringC);
		goto out_cleanup;
	}
	amdgpu_semaphore_emit_signal(ringC, semaphore);
	amdgpu_ring_unlock_commit(ringC);

	mdelay(1000);

	r = fence_wait(fenceA, false);
	if (r) {
		DRM_ERROR("Failed to wait for sync fence A\n");
		goto out_cleanup;
	}
	r = fence_wait(fenceB, false);
	if (r) {
		DRM_ERROR("Failed to wait for sync fence B\n");
		goto out_cleanup;
	}

out_cleanup:
	amdgpu_semaphore_free(adev, &semaphore, NULL);

	if (fenceA)
		fence_put(fenceA);

	if (fenceB)
		fence_put(fenceB);

	if (r)
		printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
}

static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
				      struct amdgpu_ring *ringB)
{
	if (ringA == &ringA->adev->vce.ring[0] &&
	    ringB == &ringB->adev->vce.ring[1])
		return false;

	return true;
}

void amdgpu_test_syncing(struct amdgpu_device *adev)
{
	int i, j, k;

	for (i = 1; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_ring *ringA = adev->rings[i];
		if (!ringA || !ringA->ready)
			continue;

		for (j = 0; j < i; ++j) {
			struct amdgpu_ring *ringB = adev->rings[j];
			if (!ringB || !ringB->ready)
				continue;

			if (!amdgpu_test_sync_possible(ringA, ringB))
				continue;

			DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
			amdgpu_test_ring_sync(adev, ringA, ringB);

			DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
			amdgpu_test_ring_sync(adev, ringB, ringA);

			for (k = 0; k < j; ++k) {
				struct amdgpu_ring *ringC = adev->rings[k];
				if (!ringC || !ringC->ready)
					continue;

				if (!amdgpu_test_sync_possible(ringA, ringC))
					continue;

				if (!amdgpu_test_sync_possible(ringB, ringC))
					continue;

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
				amdgpu_test_ring_sync2(adev, ringA, ringB, ringC);

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
				amdgpu_test_ring_sync2(adev, ringA, ringC, ringB);

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
				amdgpu_test_ring_sync2(adev, ringB, ringA, ringC);

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
				amdgpu_test_ring_sync2(adev, ringB, ringC, ringA);

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
				amdgpu_test_ring_sync2(adev, ringC, ringA, ringB);

				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
				amdgpu_test_ring_sync2(adev, ringC, ringB, ringA);
			}
		}
	}
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2009 VMware, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Michel Dänzer
	23	*/
	24	#include <drm/drmP.h>
	25	#include <drm/amdgpu_drm.h>
	26	#include "amdgpu.h"
	27	#include "amdgpu_uvd.h"
	28	#include "amdgpu_vce.h"
	29
	30	/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
	31	static void amdgpu_do_test_moves(struct amdgpu_device *adev)
	32	{
	33	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
	34	struct amdgpu_bo *vram_obj = NULL;
	35	struct amdgpu_bo **gtt_obj = NULL;
	36	uint64_t gtt_addr, vram_addr;
	37	unsigned n, size;
	38	int i, r;
	39
	40	size = 1024 * 1024;
	41
	42	/* Number of tests =
	43	* (Total GTT - IB pool - writeback page - ring buffers) / test size
	44	*/
	45	n = adev->mc.gtt_size - AMDGPU_IB_POOL_SIZE641024;
	46	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	47	if (adev->rings[i])
	48	n -= adev->rings[i]->ring_size;
	49	if (adev->wb.wb_obj)
	50	n -= AMDGPU_GPU_PAGE_SIZE;
	51	if (adev->irq.ih.ring_obj)
	52	n -= adev->irq.ih.ring_size;
	53	n /= size;
	54
	55	gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
	56	if (!gtt_obj) {
	57	DRM_ERROR("Failed to allocate %d pointers\n", n);
	58	r = 1;
	59	goto out_cleanup;
	60	}
	61
72d7668b CK	62	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
	63	AMDGPU_GEM_DOMAIN_VRAM, 0,
	64	NULL, NULL, &vram_obj);
d38ceaf9 AD	65	if (r) {
	66	DRM_ERROR("Failed to create VRAM object\n");
	67	goto out_cleanup;
	68	}
	69	r = amdgpu_bo_reserve(vram_obj, false);
	70	if (unlikely(r != 0))
	71	goto out_unref;
	72	r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr);
	73	if (r) {
	74	DRM_ERROR("Failed to pin VRAM object\n");
	75	goto out_unres;
	76	}
	77	for (i = 0; i < n; i++) {
	78	void gtt_map, vram_map;
	79	void gtt_start, gtt_end;
	80	void vram_start, vram_end;
c7ae72c0	81	struct fence *fence = NULL;
d38ceaf9 AD	82
d38ceaf9 AD	83	r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
72d7668b CK	84	AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
72d7668b CK	85	NULL, gtt_obj + i);
d38ceaf9 AD	86	if (r) {
	87	DRM_ERROR("Failed to create GTT object %d\n", i);
	88	goto out_lclean;
	89	}
	90
	91	r = amdgpu_bo_reserve(gtt_obj[i], false);
	92	if (unlikely(r != 0))
	93	goto out_lclean_unref;
	94	r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, &gtt_addr);
	95	if (r) {
	96	DRM_ERROR("Failed to pin GTT object %d\n", i);
	97	goto out_lclean_unres;
	98	}
	99
	100	r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
	101	if (r) {
	102	DRM_ERROR("Failed to map GTT object %d\n", i);
	103	goto out_lclean_unpin;
	104	}
	105
	106	for (gtt_start = gtt_map, gtt_end = gtt_map + size;
	107	gtt_start < gtt_end;
	108	gtt_start++)
	109	*gtt_start = gtt_start;
	110
	111	amdgpu_bo_kunmap(gtt_obj[i]);
	112
	113	r = amdgpu_copy_buffer(ring, gtt_addr, vram_addr,
	114	size, NULL, &fence);
	115
	116	if (r) {
	117	DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
	118	goto out_lclean_unpin;
	119	}
	120
c7ae72c0	121	r = fence_wait(fence, false);
d38ceaf9 AD	122	if (r) {
	123	DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
	124	goto out_lclean_unpin;
	125	}
	126
c7ae72c0	127	fence_put(fence);
d38ceaf9 AD	128
	129	r = amdgpu_bo_kmap(vram_obj, &vram_map);
	130	if (r) {
	131	DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
	132	goto out_lclean_unpin;
	133	}
	134
	135	for (gtt_start = gtt_map, gtt_end = gtt_map + size,
	136	vram_start = vram_map, vram_end = vram_map + size;
	137	vram_start < vram_end;
	138	gtt_start++, vram_start++) {
	139	if (*vram_start != gtt_start) {
	140	DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
	141	"expected 0x%p (GTT/VRAM offset "
	142	"0x%16llx/0x%16llx)\n",
	143	i, *vram_start, gtt_start,
	144	(unsigned long long)
	145	(gtt_addr - adev->mc.gtt_start +
	146	(void*)gtt_start - gtt_map),
	147	(unsigned long long)
	148	(vram_addr - adev->mc.vram_start +
	149	(void*)gtt_start - gtt_map));
	150	amdgpu_bo_kunmap(vram_obj);
	151	goto out_lclean_unpin;
	152	}
	153	*vram_start = vram_start;
	154	}
	155
	156	amdgpu_bo_kunmap(vram_obj);
	157
	158	r = amdgpu_copy_buffer(ring, vram_addr, gtt_addr,
	159	size, NULL, &fence);
	160
	161	if (r) {
	162	DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
	163	goto out_lclean_unpin;
	164	}
	165
c7ae72c0	166	r = fence_wait(fence, false);
d38ceaf9 AD	167	if (r) {
	168	DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
	169	goto out_lclean_unpin;
	170	}
	171
c7ae72c0	172	fence_put(fence);
d38ceaf9 AD	173
	174	r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
	175	if (r) {
	176	DRM_ERROR("Failed to map GTT object after copy %d\n", i);
	177	goto out_lclean_unpin;
	178	}
	179
	180	for (gtt_start = gtt_map, gtt_end = gtt_map + size,
	181	vram_start = vram_map, vram_end = vram_map + size;
	182	gtt_start < gtt_end;
	183	gtt_start++, vram_start++) {
	184	if (*gtt_start != vram_start) {
	185	DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
	186	"expected 0x%p (VRAM/GTT offset "
	187	"0x%16llx/0x%16llx)\n",
	188	i, *gtt_start, vram_start,
	189	(unsigned long long)
	190	(vram_addr - adev->mc.vram_start +
	191	(void*)vram_start - vram_map),
	192	(unsigned long long)
	193	(gtt_addr - adev->mc.gtt_start +
	194	(void*)vram_start - vram_map));
	195	amdgpu_bo_kunmap(gtt_obj[i]);
	196	goto out_lclean_unpin;
	197	}
	198	}
	199
	200	amdgpu_bo_kunmap(gtt_obj[i]);
	201
	202	DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
	203	gtt_addr - adev->mc.gtt_start);
	204	continue;
	205
	206	out_lclean_unpin:
	207	amdgpu_bo_unpin(gtt_obj[i]);
	208	out_lclean_unres:
	209	amdgpu_bo_unreserve(gtt_obj[i]);
	210	out_lclean_unref:
	211	amdgpu_bo_unref(&gtt_obj[i]);
	212	out_lclean:
	213	for (--i; i >= 0; --i) {
	214	amdgpu_bo_unpin(gtt_obj[i]);
	215	amdgpu_bo_unreserve(gtt_obj[i]);
	216	amdgpu_bo_unref(&gtt_obj[i]);
	217	}
	218	if (fence)
c7ae72c0	219	fence_put(fence);
d38ceaf9 AD	220	break;
	221	}
	222
	223	amdgpu_bo_unpin(vram_obj);
	224	out_unres:
	225	amdgpu_bo_unreserve(vram_obj);
	226	out_unref:
	227	amdgpu_bo_unref(&vram_obj);
	228	out_cleanup:
	229	kfree(gtt_obj);
	230	if (r) {
	231	printk(KERN_WARNING "Error while testing BO move.\n");
	232	}
	233	}
	234
	235	void amdgpu_test_moves(struct amdgpu_device *adev)
	236	{
	237	if (adev->mman.buffer_funcs)
	238	amdgpu_do_test_moves(adev);
	239	}
	240
	241	static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev,
	242	struct amdgpu_ring *ring,
6863bc8b	243	struct fence **fence)
d38ceaf9 AD	244	{
	245	uint32_t handle = ring->idx ^ 0xdeafbeef;
	246	int r;
	247
	248	if (ring == &adev->uvd.ring) {
	249	r = amdgpu_uvd_get_create_msg(ring, handle, NULL);
	250	if (r) {
	251	DRM_ERROR("Failed to get dummy create msg\n");
	252	return r;
	253	}
	254
6863bc8b	255	r = amdgpu_uvd_get_destroy_msg(ring, handle, fence);
d38ceaf9 AD	256	if (r) {
	257	DRM_ERROR("Failed to get dummy destroy msg\n");
	258	return r;
	259	}
	260
	261	} else if (ring == &adev->vce.ring[0] \|\|
	262	ring == &adev->vce.ring[1]) {
	263	r = amdgpu_vce_get_create_msg(ring, handle, NULL);
	264	if (r) {
	265	DRM_ERROR("Failed to get dummy create msg\n");
	266	return r;
	267	}
	268
6863bc8b	269	r = amdgpu_vce_get_destroy_msg(ring, handle, fence);
d38ceaf9 AD	270	if (r) {
	271	DRM_ERROR("Failed to get dummy destroy msg\n");
	272	return r;
	273	}
d38ceaf9	274	} else {
6863bc8b	275	struct amdgpu_fence *a_fence = NULL;
d38ceaf9 AD	276	r = amdgpu_ring_lock(ring, 64);
	277	if (r) {
	278	DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
	279	return r;
	280	}
6863bc8b	281	amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence);
d38ceaf9	282	amdgpu_ring_unlock_commit(ring);
6863bc8b	283	*fence = &a_fence->base;
d38ceaf9 AD	284	}
	285	return 0;
	286	}
	287
	288	void amdgpu_test_ring_sync(struct amdgpu_device *adev,
	289	struct amdgpu_ring *ringA,
	290	struct amdgpu_ring *ringB)
	291	{
6863bc8b	292	struct fence fence1 = NULL, fence2 = NULL;
d38ceaf9 AD	293	struct amdgpu_semaphore *semaphore = NULL;
	294	int r;
	295
	296	r = amdgpu_semaphore_create(adev, &semaphore);
	297	if (r) {
	298	DRM_ERROR("Failed to create semaphore\n");
	299	goto out_cleanup;
	300	}
	301
	302	r = amdgpu_ring_lock(ringA, 64);
	303	if (r) {
	304	DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
	305	goto out_cleanup;
	306	}
	307	amdgpu_semaphore_emit_wait(ringA, semaphore);
	308	amdgpu_ring_unlock_commit(ringA);
	309
	310	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1);
	311	if (r)
	312	goto out_cleanup;
	313
	314	r = amdgpu_ring_lock(ringA, 64);
	315	if (r) {
	316	DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
	317	goto out_cleanup;
	318	}
	319	amdgpu_semaphore_emit_wait(ringA, semaphore);
	320	amdgpu_ring_unlock_commit(ringA);
	321
	322	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2);
	323	if (r)
	324	goto out_cleanup;
	325
	326	mdelay(1000);
	327
6863bc8b	328	if (fence_is_signaled(fence1)) {
d38ceaf9 AD	329	DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
	330	goto out_cleanup;
	331	}
	332
	333	r = amdgpu_ring_lock(ringB, 64);
	334	if (r) {
	335	DRM_ERROR("Failed to lock ring B %p\n", ringB);
	336	goto out_cleanup;
	337	}
	338	amdgpu_semaphore_emit_signal(ringB, semaphore);
	339	amdgpu_ring_unlock_commit(ringB);
	340
6863bc8b	341	r = fence_wait(fence1, false);
d38ceaf9 AD	342	if (r) {
	343	DRM_ERROR("Failed to wait for sync fence 1\n");
	344	goto out_cleanup;
	345	}
	346
	347	mdelay(1000);
	348
6863bc8b	349	if (fence_is_signaled(fence2)) {
d38ceaf9 AD	350	DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
	351	goto out_cleanup;
	352	}
	353
	354	r = amdgpu_ring_lock(ringB, 64);
	355	if (r) {
	356	DRM_ERROR("Failed to lock ring B %p\n", ringB);
	357	goto out_cleanup;
	358	}
	359	amdgpu_semaphore_emit_signal(ringB, semaphore);
	360	amdgpu_ring_unlock_commit(ringB);
	361
6863bc8b	362	r = fence_wait(fence2, false);
d38ceaf9 AD	363	if (r) {
	364	DRM_ERROR("Failed to wait for sync fence 1\n");
	365	goto out_cleanup;
	366	}
	367
	368	out_cleanup:
	369	amdgpu_semaphore_free(adev, &semaphore, NULL);
	370
	371	if (fence1)
6863bc8b	372	fence_put(fence1);
d38ceaf9 AD	373
d38ceaf9 AD	374	if (fence2)
6863bc8b	375	fence_put(fence2);
d38ceaf9 AD	376
	377	if (r)
	378	printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
	379	}
	380
	381	static void amdgpu_test_ring_sync2(struct amdgpu_device *adev,
	382	struct amdgpu_ring *ringA,
	383	struct amdgpu_ring *ringB,
	384	struct amdgpu_ring *ringC)
	385	{
6863bc8b	386	struct fence fenceA = NULL, fenceB = NULL;
d38ceaf9 AD	387	struct amdgpu_semaphore *semaphore = NULL;
	388	bool sigA, sigB;
	389	int i, r;
	390
	391	r = amdgpu_semaphore_create(adev, &semaphore);
	392	if (r) {
	393	DRM_ERROR("Failed to create semaphore\n");
	394	goto out_cleanup;
	395	}
	396
	397	r = amdgpu_ring_lock(ringA, 64);
	398	if (r) {
	399	DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
	400	goto out_cleanup;
	401	}
	402	amdgpu_semaphore_emit_wait(ringA, semaphore);
	403	amdgpu_ring_unlock_commit(ringA);
	404
	405	r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA);
	406	if (r)
	407	goto out_cleanup;
	408
	409	r = amdgpu_ring_lock(ringB, 64);
	410	if (r) {
	411	DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
	412	goto out_cleanup;
	413	}
	414	amdgpu_semaphore_emit_wait(ringB, semaphore);
	415	amdgpu_ring_unlock_commit(ringB);
	416	r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB);
	417	if (r)
	418	goto out_cleanup;
	419
	420	mdelay(1000);
	421
6863bc8b	422	if (fence_is_signaled(fenceA)) {
d38ceaf9 AD	423	DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
	424	goto out_cleanup;
	425	}
6863bc8b	426	if (fence_is_signaled(fenceB)) {
d38ceaf9 AD	427	DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
	428	goto out_cleanup;
	429	}
	430
	431	r = amdgpu_ring_lock(ringC, 64);
	432	if (r) {
	433	DRM_ERROR("Failed to lock ring B %p\n", ringC);
	434	goto out_cleanup;
	435	}
	436	amdgpu_semaphore_emit_signal(ringC, semaphore);
	437	amdgpu_ring_unlock_commit(ringC);
	438
	439	for (i = 0; i < 30; ++i) {
	440	mdelay(100);
6863bc8b CZ	441	sigA = fence_is_signaled(fenceA);
6863bc8b CZ	442	sigB = fence_is_signaled(fenceB);
d38ceaf9 AD	443	if (sigA \|\| sigB)
	444	break;
	445	}
	446
	447	if (!sigA && !sigB) {
	448	DRM_ERROR("Neither fence A nor B has been signaled\n");
	449	goto out_cleanup;
	450	} else if (sigA && sigB) {
	451	DRM_ERROR("Both fence A and B has been signaled\n");
	452	goto out_cleanup;
	453	}
	454
	455	DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
	456
	457	r = amdgpu_ring_lock(ringC, 64);
	458	if (r) {
	459	DRM_ERROR("Failed to lock ring B %p\n", ringC);
	460	goto out_cleanup;
	461	}
	462	amdgpu_semaphore_emit_signal(ringC, semaphore);
	463	amdgpu_ring_unlock_commit(ringC);
	464
	465	mdelay(1000);
	466
6863bc8b	467	r = fence_wait(fenceA, false);
d38ceaf9 AD	468	if (r) {
	469	DRM_ERROR("Failed to wait for sync fence A\n");
	470	goto out_cleanup;
	471	}
6863bc8b	472	r = fence_wait(fenceB, false);
d38ceaf9 AD	473	if (r) {
	474	DRM_ERROR("Failed to wait for sync fence B\n");
	475	goto out_cleanup;
	476	}
	477
	478	out_cleanup:
	479	amdgpu_semaphore_free(adev, &semaphore, NULL);
	480
	481	if (fenceA)
6863bc8b	482	fence_put(fenceA);
d38ceaf9 AD	483
d38ceaf9 AD	484	if (fenceB)
6863bc8b	485	fence_put(fenceB);
d38ceaf9 AD	486
	487	if (r)
	488	printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
	489	}
	490
	491	static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA,
	492	struct amdgpu_ring *ringB)
	493	{
	494	if (ringA == &ringA->adev->vce.ring[0] &&
	495	ringB == &ringB->adev->vce.ring[1])
	496	return false;
	497
	498	return true;
	499	}
	500
	501	void amdgpu_test_syncing(struct amdgpu_device *adev)
	502	{
	503	int i, j, k;
	504
	505	for (i = 1; i < AMDGPU_MAX_RINGS; ++i) {
	506	struct amdgpu_ring *ringA = adev->rings[i];
	507	if (!ringA \|\| !ringA->ready)
	508	continue;
	509
	510	for (j = 0; j < i; ++j) {
	511	struct amdgpu_ring *ringB = adev->rings[j];
	512	if (!ringB \|\| !ringB->ready)
	513	continue;
	514
	515	if (!amdgpu_test_sync_possible(ringA, ringB))
	516	continue;
	517
	518	DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
	519	amdgpu_test_ring_sync(adev, ringA, ringB);
	520
	521	DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
	522	amdgpu_test_ring_sync(adev, ringB, ringA);
	523
	524	for (k = 0; k < j; ++k) {
	525	struct amdgpu_ring *ringC = adev->rings[k];
	526	if (!ringC \|\| !ringC->ready)
	527	continue;
	528
	529	if (!amdgpu_test_sync_possible(ringA, ringC))
	530	continue;
	531
	532	if (!amdgpu_test_sync_possible(ringB, ringC))
	533	continue;
	534
	535	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
	536	amdgpu_test_ring_sync2(adev, ringA, ringB, ringC);
	537
	538	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
	539	amdgpu_test_ring_sync2(adev, ringA, ringC, ringB);
	540
	541	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
	542	amdgpu_test_ring_sync2(adev, ringB, ringA, ringC);
	543
	544	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
	545	amdgpu_test_ring_sync2(adev, ringB, ringC, ringA);
	546
	547	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
	548	amdgpu_test_ring_sync2(adev, ringC, ringA, ringB);
	549
550	DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
551	amdgpu_test_ring_sync2(adev, ringC, ringB, ringA);
552	}
553	}
554	}
555	}