Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <ttm/ttm_bo_api.h> | |
33 | #include <ttm/ttm_bo_driver.h> | |
34 | #include <ttm/ttm_placement.h> | |
35 | #include <ttm/ttm_module.h> | |
36 | #include <ttm/ttm_page_alloc.h> | |
a693e050 | 37 | #include <ttm/ttm_memory.h> |
d38ceaf9 AD |
38 | #include <drm/drmP.h> |
39 | #include <drm/amdgpu_drm.h> | |
40 | #include <linux/seq_file.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/swiotlb.h> | |
43 | #include <linux/swap.h> | |
44 | #include <linux/pagemap.h> | |
45 | #include <linux/debugfs.h> | |
46 | #include "amdgpu.h" | |
47 | #include "bif/bif_4_1_d.h" | |
48 | ||
49 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
50 | ||
51 | static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); | |
52 | static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); | |
53 | ||
54 | static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev) | |
55 | { | |
56 | struct amdgpu_mman *mman; | |
57 | struct amdgpu_device *adev; | |
58 | ||
59 | mman = container_of(bdev, struct amdgpu_mman, bdev); | |
60 | adev = container_of(mman, struct amdgpu_device, mman); | |
61 | return adev; | |
62 | } | |
63 | ||
64 | ||
65 | /* | |
66 | * Global memory. | |
67 | */ | |
68 | static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref) | |
69 | { | |
70 | return ttm_mem_global_init(ref->object); | |
71 | } | |
72 | ||
73 | static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref) | |
74 | { | |
75 | ttm_mem_global_release(ref->object); | |
76 | } | |
77 | ||
a693e050 | 78 | int amdgpu_ttm_global_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
79 | { |
80 | struct drm_global_reference *global_ref; | |
703297c1 CK |
81 | struct amdgpu_ring *ring; |
82 | struct amd_sched_rq *rq; | |
d38ceaf9 AD |
83 | int r; |
84 | ||
85 | adev->mman.mem_global_referenced = false; | |
86 | global_ref = &adev->mman.mem_global_ref; | |
87 | global_ref->global_type = DRM_GLOBAL_TTM_MEM; | |
88 | global_ref->size = sizeof(struct ttm_mem_global); | |
89 | global_ref->init = &amdgpu_ttm_mem_global_init; | |
90 | global_ref->release = &amdgpu_ttm_mem_global_release; | |
91 | r = drm_global_item_ref(global_ref); | |
92 | if (r != 0) { | |
93 | DRM_ERROR("Failed setting up TTM memory accounting " | |
94 | "subsystem.\n"); | |
95 | return r; | |
96 | } | |
97 | ||
98 | adev->mman.bo_global_ref.mem_glob = | |
99 | adev->mman.mem_global_ref.object; | |
100 | global_ref = &adev->mman.bo_global_ref.ref; | |
101 | global_ref->global_type = DRM_GLOBAL_TTM_BO; | |
102 | global_ref->size = sizeof(struct ttm_bo_global); | |
103 | global_ref->init = &ttm_bo_global_init; | |
104 | global_ref->release = &ttm_bo_global_release; | |
105 | r = drm_global_item_ref(global_ref); | |
106 | if (r != 0) { | |
107 | DRM_ERROR("Failed setting up TTM BO subsystem.\n"); | |
108 | drm_global_item_unref(&adev->mman.mem_global_ref); | |
109 | return r; | |
110 | } | |
111 | ||
703297c1 CK |
112 | ring = adev->mman.buffer_funcs_ring; |
113 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; | |
114 | r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, | |
115 | rq, amdgpu_sched_jobs); | |
116 | if (r != 0) { | |
117 | DRM_ERROR("Failed setting up TTM BO move run queue.\n"); | |
118 | drm_global_item_unref(&adev->mman.mem_global_ref); | |
119 | drm_global_item_unref(&adev->mman.bo_global_ref.ref); | |
120 | return r; | |
121 | } | |
122 | ||
d38ceaf9 | 123 | adev->mman.mem_global_referenced = true; |
703297c1 | 124 | |
d38ceaf9 AD |
125 | return 0; |
126 | } | |
127 | ||
128 | static void amdgpu_ttm_global_fini(struct amdgpu_device *adev) | |
129 | { | |
130 | if (adev->mman.mem_global_referenced) { | |
703297c1 CK |
131 | amd_sched_entity_fini(adev->mman.entity.sched, |
132 | &adev->mman.entity); | |
d38ceaf9 AD |
133 | drm_global_item_unref(&adev->mman.bo_global_ref.ref); |
134 | drm_global_item_unref(&adev->mman.mem_global_ref); | |
135 | adev->mman.mem_global_referenced = false; | |
136 | } | |
137 | } | |
138 | ||
139 | static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
145 | struct ttm_mem_type_manager *man) | |
146 | { | |
147 | struct amdgpu_device *adev; | |
148 | ||
149 | adev = amdgpu_get_adev(bdev); | |
150 | ||
151 | switch (type) { | |
152 | case TTM_PL_SYSTEM: | |
153 | /* System memory */ | |
154 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
155 | man->available_caching = TTM_PL_MASK_CACHING; | |
156 | man->default_caching = TTM_PL_FLAG_CACHED; | |
157 | break; | |
158 | case TTM_PL_TT: | |
159 | man->func = &ttm_bo_manager_func; | |
160 | man->gpu_offset = adev->mc.gtt_start; | |
161 | man->available_caching = TTM_PL_MASK_CACHING; | |
162 | man->default_caching = TTM_PL_FLAG_CACHED; | |
163 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; | |
164 | break; | |
165 | case TTM_PL_VRAM: | |
166 | /* "On-card" video ram */ | |
167 | man->func = &ttm_bo_manager_func; | |
168 | man->gpu_offset = adev->mc.vram_start; | |
169 | man->flags = TTM_MEMTYPE_FLAG_FIXED | | |
170 | TTM_MEMTYPE_FLAG_MAPPABLE; | |
171 | man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; | |
172 | man->default_caching = TTM_PL_FLAG_WC; | |
173 | break; | |
174 | case AMDGPU_PL_GDS: | |
175 | case AMDGPU_PL_GWS: | |
176 | case AMDGPU_PL_OA: | |
177 | /* On-chip GDS memory*/ | |
178 | man->func = &ttm_bo_manager_func; | |
179 | man->gpu_offset = 0; | |
180 | man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA; | |
181 | man->available_caching = TTM_PL_FLAG_UNCACHED; | |
182 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
183 | break; | |
184 | default: | |
185 | DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); | |
186 | return -EINVAL; | |
187 | } | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static void amdgpu_evict_flags(struct ttm_buffer_object *bo, | |
192 | struct ttm_placement *placement) | |
193 | { | |
194 | struct amdgpu_bo *rbo; | |
195 | static struct ttm_place placements = { | |
196 | .fpfn = 0, | |
197 | .lpfn = 0, | |
198 | .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM | |
199 | }; | |
200 | ||
201 | if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) { | |
202 | placement->placement = &placements; | |
203 | placement->busy_placement = &placements; | |
204 | placement->num_placement = 1; | |
205 | placement->num_busy_placement = 1; | |
206 | return; | |
207 | } | |
208 | rbo = container_of(bo, struct amdgpu_bo, tbo); | |
209 | switch (bo->mem.mem_type) { | |
210 | case TTM_PL_VRAM: | |
211 | if (rbo->adev->mman.buffer_funcs_ring->ready == false) | |
212 | amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); | |
213 | else | |
214 | amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT); | |
215 | break; | |
216 | case TTM_PL_TT: | |
217 | default: | |
218 | amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU); | |
219 | } | |
220 | *placement = rbo->placement; | |
221 | } | |
222 | ||
223 | static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
224 | { | |
225 | struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo); | |
226 | ||
054892ed JG |
227 | if (amdgpu_ttm_tt_get_usermm(bo->ttm)) |
228 | return -EPERM; | |
d38ceaf9 AD |
229 | return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); |
230 | } | |
231 | ||
232 | static void amdgpu_move_null(struct ttm_buffer_object *bo, | |
233 | struct ttm_mem_reg *new_mem) | |
234 | { | |
235 | struct ttm_mem_reg *old_mem = &bo->mem; | |
236 | ||
237 | BUG_ON(old_mem->mm_node != NULL); | |
238 | *old_mem = *new_mem; | |
239 | new_mem->mm_node = NULL; | |
240 | } | |
241 | ||
242 | static int amdgpu_move_blit(struct ttm_buffer_object *bo, | |
243 | bool evict, bool no_wait_gpu, | |
244 | struct ttm_mem_reg *new_mem, | |
245 | struct ttm_mem_reg *old_mem) | |
246 | { | |
247 | struct amdgpu_device *adev; | |
248 | struct amdgpu_ring *ring; | |
249 | uint64_t old_start, new_start; | |
c7ae72c0 | 250 | struct fence *fence; |
d38ceaf9 AD |
251 | int r; |
252 | ||
253 | adev = amdgpu_get_adev(bo->bdev); | |
254 | ring = adev->mman.buffer_funcs_ring; | |
815d27a4 CK |
255 | old_start = (u64)old_mem->start << PAGE_SHIFT; |
256 | new_start = (u64)new_mem->start << PAGE_SHIFT; | |
d38ceaf9 AD |
257 | |
258 | switch (old_mem->mem_type) { | |
259 | case TTM_PL_VRAM: | |
d38ceaf9 | 260 | case TTM_PL_TT: |
27798e07 | 261 | old_start += bo->bdev->man[old_mem->mem_type].gpu_offset; |
d38ceaf9 AD |
262 | break; |
263 | default: | |
264 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
265 | return -EINVAL; | |
266 | } | |
267 | switch (new_mem->mem_type) { | |
268 | case TTM_PL_VRAM: | |
d38ceaf9 | 269 | case TTM_PL_TT: |
27798e07 | 270 | new_start += bo->bdev->man[new_mem->mem_type].gpu_offset; |
d38ceaf9 AD |
271 | break; |
272 | default: | |
273 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | |
274 | return -EINVAL; | |
275 | } | |
276 | if (!ring->ready) { | |
277 | DRM_ERROR("Trying to move memory with ring turned off.\n"); | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0); | |
282 | ||
283 | r = amdgpu_copy_buffer(ring, old_start, new_start, | |
284 | new_mem->num_pages * PAGE_SIZE, /* bytes */ | |
e24db985 | 285 | bo->resv, &fence, false); |
ce64bc25 CK |
286 | if (r) |
287 | return r; | |
288 | ||
289 | r = ttm_bo_pipeline_move(bo, fence, evict, new_mem); | |
c7ae72c0 | 290 | fence_put(fence); |
d38ceaf9 AD |
291 | return r; |
292 | } | |
293 | ||
294 | static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, | |
295 | bool evict, bool interruptible, | |
296 | bool no_wait_gpu, | |
297 | struct ttm_mem_reg *new_mem) | |
298 | { | |
299 | struct amdgpu_device *adev; | |
300 | struct ttm_mem_reg *old_mem = &bo->mem; | |
301 | struct ttm_mem_reg tmp_mem; | |
302 | struct ttm_place placements; | |
303 | struct ttm_placement placement; | |
304 | int r; | |
305 | ||
306 | adev = amdgpu_get_adev(bo->bdev); | |
307 | tmp_mem = *new_mem; | |
308 | tmp_mem.mm_node = NULL; | |
309 | placement.num_placement = 1; | |
310 | placement.placement = &placements; | |
311 | placement.num_busy_placement = 1; | |
312 | placement.busy_placement = &placements; | |
313 | placements.fpfn = 0; | |
314 | placements.lpfn = 0; | |
315 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
316 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
317 | interruptible, no_wait_gpu); | |
318 | if (unlikely(r)) { | |
319 | return r; | |
320 | } | |
321 | ||
322 | r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); | |
323 | if (unlikely(r)) { | |
324 | goto out_cleanup; | |
325 | } | |
326 | ||
327 | r = ttm_tt_bind(bo->ttm, &tmp_mem); | |
328 | if (unlikely(r)) { | |
329 | goto out_cleanup; | |
330 | } | |
331 | r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); | |
332 | if (unlikely(r)) { | |
333 | goto out_cleanup; | |
334 | } | |
4e2f0caa | 335 | r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); |
d38ceaf9 AD |
336 | out_cleanup: |
337 | ttm_bo_mem_put(bo, &tmp_mem); | |
338 | return r; | |
339 | } | |
340 | ||
341 | static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, | |
342 | bool evict, bool interruptible, | |
343 | bool no_wait_gpu, | |
344 | struct ttm_mem_reg *new_mem) | |
345 | { | |
346 | struct amdgpu_device *adev; | |
347 | struct ttm_mem_reg *old_mem = &bo->mem; | |
348 | struct ttm_mem_reg tmp_mem; | |
349 | struct ttm_placement placement; | |
350 | struct ttm_place placements; | |
351 | int r; | |
352 | ||
353 | adev = amdgpu_get_adev(bo->bdev); | |
354 | tmp_mem = *new_mem; | |
355 | tmp_mem.mm_node = NULL; | |
356 | placement.num_placement = 1; | |
357 | placement.placement = &placements; | |
358 | placement.num_busy_placement = 1; | |
359 | placement.busy_placement = &placements; | |
360 | placements.fpfn = 0; | |
361 | placements.lpfn = 0; | |
362 | placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
363 | r = ttm_bo_mem_space(bo, &placement, &tmp_mem, | |
364 | interruptible, no_wait_gpu); | |
365 | if (unlikely(r)) { | |
366 | return r; | |
367 | } | |
4e2f0caa | 368 | r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); |
d38ceaf9 AD |
369 | if (unlikely(r)) { |
370 | goto out_cleanup; | |
371 | } | |
372 | r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); | |
373 | if (unlikely(r)) { | |
374 | goto out_cleanup; | |
375 | } | |
376 | out_cleanup: | |
377 | ttm_bo_mem_put(bo, &tmp_mem); | |
378 | return r; | |
379 | } | |
380 | ||
381 | static int amdgpu_bo_move(struct ttm_buffer_object *bo, | |
382 | bool evict, bool interruptible, | |
383 | bool no_wait_gpu, | |
384 | struct ttm_mem_reg *new_mem) | |
385 | { | |
386 | struct amdgpu_device *adev; | |
104ece97 | 387 | struct amdgpu_bo *abo; |
d38ceaf9 AD |
388 | struct ttm_mem_reg *old_mem = &bo->mem; |
389 | int r; | |
390 | ||
104ece97 MD |
391 | /* Can't move a pinned BO */ |
392 | abo = container_of(bo, struct amdgpu_bo, tbo); | |
393 | if (WARN_ON_ONCE(abo->pin_count > 0)) | |
394 | return -EINVAL; | |
395 | ||
d38ceaf9 | 396 | adev = amdgpu_get_adev(bo->bdev); |
dbd5ed60 CK |
397 | |
398 | /* remember the eviction */ | |
399 | if (evict) | |
400 | atomic64_inc(&adev->num_evictions); | |
401 | ||
d38ceaf9 AD |
402 | if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { |
403 | amdgpu_move_null(bo, new_mem); | |
404 | return 0; | |
405 | } | |
406 | if ((old_mem->mem_type == TTM_PL_TT && | |
407 | new_mem->mem_type == TTM_PL_SYSTEM) || | |
408 | (old_mem->mem_type == TTM_PL_SYSTEM && | |
409 | new_mem->mem_type == TTM_PL_TT)) { | |
410 | /* bind is enough */ | |
411 | amdgpu_move_null(bo, new_mem); | |
412 | return 0; | |
413 | } | |
414 | if (adev->mman.buffer_funcs == NULL || | |
415 | adev->mman.buffer_funcs_ring == NULL || | |
416 | !adev->mman.buffer_funcs_ring->ready) { | |
417 | /* use memcpy */ | |
418 | goto memcpy; | |
419 | } | |
420 | ||
421 | if (old_mem->mem_type == TTM_PL_VRAM && | |
422 | new_mem->mem_type == TTM_PL_SYSTEM) { | |
423 | r = amdgpu_move_vram_ram(bo, evict, interruptible, | |
424 | no_wait_gpu, new_mem); | |
425 | } else if (old_mem->mem_type == TTM_PL_SYSTEM && | |
426 | new_mem->mem_type == TTM_PL_VRAM) { | |
427 | r = amdgpu_move_ram_vram(bo, evict, interruptible, | |
428 | no_wait_gpu, new_mem); | |
429 | } else { | |
430 | r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); | |
431 | } | |
432 | ||
433 | if (r) { | |
434 | memcpy: | |
4499f2ac | 435 | r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); |
d38ceaf9 AD |
436 | if (r) { |
437 | return r; | |
438 | } | |
439 | } | |
440 | ||
441 | /* update statistics */ | |
442 | atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved); | |
443 | return 0; | |
444 | } | |
445 | ||
446 | static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
447 | { | |
448 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
449 | struct amdgpu_device *adev = amdgpu_get_adev(bdev); | |
450 | ||
451 | mem->bus.addr = NULL; | |
452 | mem->bus.offset = 0; | |
453 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
454 | mem->bus.base = 0; | |
455 | mem->bus.is_iomem = false; | |
456 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
457 | return -EINVAL; | |
458 | switch (mem->mem_type) { | |
459 | case TTM_PL_SYSTEM: | |
460 | /* system memory */ | |
461 | return 0; | |
462 | case TTM_PL_TT: | |
463 | break; | |
464 | case TTM_PL_VRAM: | |
465 | mem->bus.offset = mem->start << PAGE_SHIFT; | |
466 | /* check if it's visible */ | |
467 | if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) | |
468 | return -EINVAL; | |
469 | mem->bus.base = adev->mc.aper_base; | |
470 | mem->bus.is_iomem = true; | |
471 | #ifdef __alpha__ | |
472 | /* | |
473 | * Alpha: use bus.addr to hold the ioremap() return, | |
474 | * so we can modify bus.base below. | |
475 | */ | |
476 | if (mem->placement & TTM_PL_FLAG_WC) | |
477 | mem->bus.addr = | |
478 | ioremap_wc(mem->bus.base + mem->bus.offset, | |
479 | mem->bus.size); | |
480 | else | |
481 | mem->bus.addr = | |
482 | ioremap_nocache(mem->bus.base + mem->bus.offset, | |
483 | mem->bus.size); | |
484 | ||
485 | /* | |
486 | * Alpha: Use just the bus offset plus | |
487 | * the hose/domain memory base for bus.base. | |
488 | * It then can be used to build PTEs for VRAM | |
489 | * access, as done in ttm_bo_vm_fault(). | |
490 | */ | |
491 | mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + | |
492 | adev->ddev->hose->dense_mem_base; | |
493 | #endif | |
494 | break; | |
495 | default: | |
496 | return -EINVAL; | |
497 | } | |
498 | return 0; | |
499 | } | |
500 | ||
501 | static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
502 | { | |
503 | } | |
504 | ||
505 | /* | |
506 | * TTM backend functions. | |
507 | */ | |
637dd3b5 CK |
508 | struct amdgpu_ttm_gup_task_list { |
509 | struct list_head list; | |
510 | struct task_struct *task; | |
511 | }; | |
512 | ||
d38ceaf9 | 513 | struct amdgpu_ttm_tt { |
637dd3b5 CK |
514 | struct ttm_dma_tt ttm; |
515 | struct amdgpu_device *adev; | |
516 | u64 offset; | |
517 | uint64_t userptr; | |
518 | struct mm_struct *usermm; | |
519 | uint32_t userflags; | |
520 | spinlock_t guptasklock; | |
521 | struct list_head guptasks; | |
2f568dbd | 522 | atomic_t mmu_invalidations; |
d38ceaf9 AD |
523 | }; |
524 | ||
2f568dbd | 525 | int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) |
d38ceaf9 | 526 | { |
d38ceaf9 | 527 | struct amdgpu_ttm_tt *gtt = (void *)ttm; |
d38ceaf9 | 528 | int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); |
2f568dbd CK |
529 | unsigned pinned = 0; |
530 | int r; | |
d38ceaf9 AD |
531 | |
532 | if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { | |
2f568dbd | 533 | /* check that we only use anonymous memory |
d38ceaf9 AD |
534 | to prevent problems with writeback */ |
535 | unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; | |
536 | struct vm_area_struct *vma; | |
537 | ||
538 | vma = find_vma(gtt->usermm, gtt->userptr); | |
539 | if (!vma || vma->vm_file || vma->vm_end < end) | |
540 | return -EPERM; | |
541 | } | |
542 | ||
543 | do { | |
544 | unsigned num_pages = ttm->num_pages - pinned; | |
545 | uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; | |
2f568dbd | 546 | struct page **p = pages + pinned; |
637dd3b5 CK |
547 | struct amdgpu_ttm_gup_task_list guptask; |
548 | ||
549 | guptask.task = current; | |
550 | spin_lock(>t->guptasklock); | |
551 | list_add(&guptask.list, >t->guptasks); | |
552 | spin_unlock(>t->guptasklock); | |
d38ceaf9 | 553 | |
266c73b7 | 554 | r = get_user_pages(userptr, num_pages, write, 0, p, NULL); |
637dd3b5 CK |
555 | |
556 | spin_lock(>t->guptasklock); | |
557 | list_del(&guptask.list); | |
558 | spin_unlock(>t->guptasklock); | |
d38ceaf9 | 559 | |
d38ceaf9 AD |
560 | if (r < 0) |
561 | goto release_pages; | |
562 | ||
563 | pinned += r; | |
564 | ||
565 | } while (pinned < ttm->num_pages); | |
566 | ||
2f568dbd CK |
567 | return 0; |
568 | ||
569 | release_pages: | |
570 | release_pages(pages, pinned, 0); | |
571 | return r; | |
572 | } | |
573 | ||
574 | /* prepare the sg table with the user pages */ | |
575 | static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) | |
576 | { | |
577 | struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); | |
578 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
579 | unsigned nents; | |
580 | int r; | |
581 | ||
582 | int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
583 | enum dma_data_direction direction = write ? | |
584 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
585 | ||
d38ceaf9 AD |
586 | r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, |
587 | ttm->num_pages << PAGE_SHIFT, | |
588 | GFP_KERNEL); | |
589 | if (r) | |
590 | goto release_sg; | |
591 | ||
592 | r = -ENOMEM; | |
593 | nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
594 | if (nents != ttm->sg->nents) | |
595 | goto release_sg; | |
596 | ||
597 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
598 | gtt->ttm.dma_address, ttm->num_pages); | |
599 | ||
600 | return 0; | |
601 | ||
602 | release_sg: | |
603 | kfree(ttm->sg); | |
d38ceaf9 AD |
604 | return r; |
605 | } | |
606 | ||
607 | static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) | |
608 | { | |
609 | struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev); | |
610 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
dd08fae1 | 611 | struct sg_page_iter sg_iter; |
d38ceaf9 AD |
612 | |
613 | int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
614 | enum dma_data_direction direction = write ? | |
615 | DMA_BIDIRECTIONAL : DMA_TO_DEVICE; | |
616 | ||
617 | /* double check that we don't free the table twice */ | |
618 | if (!ttm->sg->sgl) | |
619 | return; | |
620 | ||
621 | /* free the sg table and pages again */ | |
622 | dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction); | |
623 | ||
dd08fae1 | 624 | for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { |
625 | struct page *page = sg_page_iter_page(&sg_iter); | |
d38ceaf9 AD |
626 | if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) |
627 | set_page_dirty(page); | |
628 | ||
629 | mark_page_accessed(page); | |
09cbfeaf | 630 | put_page(page); |
d38ceaf9 AD |
631 | } |
632 | ||
633 | sg_free_table(ttm->sg); | |
634 | } | |
635 | ||
636 | static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, | |
637 | struct ttm_mem_reg *bo_mem) | |
638 | { | |
639 | struct amdgpu_ttm_tt *gtt = (void*)ttm; | |
640 | uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); | |
641 | int r; | |
642 | ||
e2f784fa CZ |
643 | if (gtt->userptr) { |
644 | r = amdgpu_ttm_tt_pin_userptr(ttm); | |
645 | if (r) { | |
646 | DRM_ERROR("failed to pin userptr\n"); | |
647 | return r; | |
648 | } | |
649 | } | |
d38ceaf9 AD |
650 | gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); |
651 | if (!ttm->num_pages) { | |
652 | WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", | |
653 | ttm->num_pages, bo_mem, ttm); | |
654 | } | |
655 | ||
656 | if (bo_mem->mem_type == AMDGPU_PL_GDS || | |
657 | bo_mem->mem_type == AMDGPU_PL_GWS || | |
658 | bo_mem->mem_type == AMDGPU_PL_OA) | |
659 | return -EINVAL; | |
660 | ||
661 | r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, | |
662 | ttm->pages, gtt->ttm.dma_address, flags); | |
663 | ||
664 | if (r) { | |
665 | DRM_ERROR("failed to bind %lu pages at 0x%08X\n", | |
666 | ttm->num_pages, (unsigned)gtt->offset); | |
667 | return r; | |
668 | } | |
669 | return 0; | |
670 | } | |
671 | ||
672 | static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) | |
673 | { | |
674 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
675 | ||
676 | /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ | |
677 | if (gtt->adev->gart.ready) | |
678 | amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); | |
679 | ||
680 | if (gtt->userptr) | |
681 | amdgpu_ttm_tt_unpin_userptr(ttm); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm) | |
687 | { | |
688 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
689 | ||
690 | ttm_dma_tt_fini(>t->ttm); | |
691 | kfree(gtt); | |
692 | } | |
693 | ||
694 | static struct ttm_backend_func amdgpu_backend_func = { | |
695 | .bind = &amdgpu_ttm_backend_bind, | |
696 | .unbind = &amdgpu_ttm_backend_unbind, | |
697 | .destroy = &amdgpu_ttm_backend_destroy, | |
698 | }; | |
699 | ||
700 | static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, | |
701 | unsigned long size, uint32_t page_flags, | |
702 | struct page *dummy_read_page) | |
703 | { | |
704 | struct amdgpu_device *adev; | |
705 | struct amdgpu_ttm_tt *gtt; | |
706 | ||
707 | adev = amdgpu_get_adev(bdev); | |
708 | ||
709 | gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); | |
710 | if (gtt == NULL) { | |
711 | return NULL; | |
712 | } | |
713 | gtt->ttm.ttm.func = &amdgpu_backend_func; | |
714 | gtt->adev = adev; | |
715 | if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { | |
716 | kfree(gtt); | |
717 | return NULL; | |
718 | } | |
719 | return >t->ttm.ttm; | |
720 | } | |
721 | ||
722 | static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) | |
723 | { | |
724 | struct amdgpu_device *adev; | |
725 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
726 | unsigned i; | |
727 | int r; | |
728 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); | |
729 | ||
730 | if (ttm->state != tt_unpopulated) | |
731 | return 0; | |
732 | ||
733 | if (gtt && gtt->userptr) { | |
5f0b34cc | 734 | ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); |
d38ceaf9 AD |
735 | if (!ttm->sg) |
736 | return -ENOMEM; | |
737 | ||
738 | ttm->page_flags |= TTM_PAGE_FLAG_SG; | |
739 | ttm->state = tt_unbound; | |
740 | return 0; | |
741 | } | |
742 | ||
743 | if (slave && ttm->sg) { | |
744 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
745 | gtt->ttm.dma_address, ttm->num_pages); | |
746 | ttm->state = tt_unbound; | |
747 | return 0; | |
748 | } | |
749 | ||
750 | adev = amdgpu_get_adev(ttm->bdev); | |
751 | ||
752 | #ifdef CONFIG_SWIOTLB | |
753 | if (swiotlb_nr_tbl()) { | |
754 | return ttm_dma_populate(>t->ttm, adev->dev); | |
755 | } | |
756 | #endif | |
757 | ||
758 | r = ttm_pool_populate(ttm); | |
759 | if (r) { | |
760 | return r; | |
761 | } | |
762 | ||
763 | for (i = 0; i < ttm->num_pages; i++) { | |
764 | gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i], | |
765 | 0, PAGE_SIZE, | |
766 | PCI_DMA_BIDIRECTIONAL); | |
767 | if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) { | |
09ccbb74 | 768 | while (i--) { |
d38ceaf9 AD |
769 | pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], |
770 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
771 | gtt->ttm.dma_address[i] = 0; | |
772 | } | |
773 | ttm_pool_unpopulate(ttm); | |
774 | return -EFAULT; | |
775 | } | |
776 | } | |
777 | return 0; | |
778 | } | |
779 | ||
780 | static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
781 | { | |
782 | struct amdgpu_device *adev; | |
783 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
784 | unsigned i; | |
785 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); | |
786 | ||
787 | if (gtt && gtt->userptr) { | |
788 | kfree(ttm->sg); | |
789 | ttm->page_flags &= ~TTM_PAGE_FLAG_SG; | |
790 | return; | |
791 | } | |
792 | ||
793 | if (slave) | |
794 | return; | |
795 | ||
796 | adev = amdgpu_get_adev(ttm->bdev); | |
797 | ||
798 | #ifdef CONFIG_SWIOTLB | |
799 | if (swiotlb_nr_tbl()) { | |
800 | ttm_dma_unpopulate(>t->ttm, adev->dev); | |
801 | return; | |
802 | } | |
803 | #endif | |
804 | ||
805 | for (i = 0; i < ttm->num_pages; i++) { | |
806 | if (gtt->ttm.dma_address[i]) { | |
807 | pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i], | |
808 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
809 | } | |
810 | } | |
811 | ||
812 | ttm_pool_unpopulate(ttm); | |
813 | } | |
814 | ||
815 | int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, | |
816 | uint32_t flags) | |
817 | { | |
818 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
819 | ||
820 | if (gtt == NULL) | |
821 | return -EINVAL; | |
822 | ||
823 | gtt->userptr = addr; | |
824 | gtt->usermm = current->mm; | |
825 | gtt->userflags = flags; | |
637dd3b5 CK |
826 | spin_lock_init(>t->guptasklock); |
827 | INIT_LIST_HEAD(>t->guptasks); | |
2f568dbd | 828 | atomic_set(>t->mmu_invalidations, 0); |
637dd3b5 | 829 | |
d38ceaf9 AD |
830 | return 0; |
831 | } | |
832 | ||
cc325d19 | 833 | struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) |
d38ceaf9 AD |
834 | { |
835 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
836 | ||
837 | if (gtt == NULL) | |
cc325d19 | 838 | return NULL; |
d38ceaf9 | 839 | |
cc325d19 | 840 | return gtt->usermm; |
d38ceaf9 AD |
841 | } |
842 | ||
cc1de6e8 CK |
843 | bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, |
844 | unsigned long end) | |
845 | { | |
846 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
637dd3b5 | 847 | struct amdgpu_ttm_gup_task_list *entry; |
cc1de6e8 CK |
848 | unsigned long size; |
849 | ||
637dd3b5 | 850 | if (gtt == NULL || !gtt->userptr) |
cc1de6e8 CK |
851 | return false; |
852 | ||
853 | size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE; | |
854 | if (gtt->userptr > end || gtt->userptr + size <= start) | |
855 | return false; | |
856 | ||
637dd3b5 CK |
857 | spin_lock(>t->guptasklock); |
858 | list_for_each_entry(entry, >t->guptasks, list) { | |
859 | if (entry->task == current) { | |
860 | spin_unlock(>t->guptasklock); | |
861 | return false; | |
862 | } | |
863 | } | |
864 | spin_unlock(>t->guptasklock); | |
865 | ||
2f568dbd CK |
866 | atomic_inc(>t->mmu_invalidations); |
867 | ||
cc1de6e8 CK |
868 | return true; |
869 | } | |
870 | ||
2f568dbd CK |
871 | bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, |
872 | int *last_invalidated) | |
873 | { | |
874 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
875 | int prev_invalidated = *last_invalidated; | |
876 | ||
877 | *last_invalidated = atomic_read(>t->mmu_invalidations); | |
878 | return prev_invalidated != *last_invalidated; | |
879 | } | |
880 | ||
d38ceaf9 AD |
881 | bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) |
882 | { | |
883 | struct amdgpu_ttm_tt *gtt = (void *)ttm; | |
884 | ||
885 | if (gtt == NULL) | |
886 | return false; | |
887 | ||
888 | return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); | |
889 | } | |
890 | ||
891 | uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, | |
892 | struct ttm_mem_reg *mem) | |
893 | { | |
894 | uint32_t flags = 0; | |
895 | ||
896 | if (mem && mem->mem_type != TTM_PL_SYSTEM) | |
897 | flags |= AMDGPU_PTE_VALID; | |
898 | ||
6d99905a | 899 | if (mem && mem->mem_type == TTM_PL_TT) { |
d38ceaf9 AD |
900 | flags |= AMDGPU_PTE_SYSTEM; |
901 | ||
6d99905a CK |
902 | if (ttm->caching_state == tt_cached) |
903 | flags |= AMDGPU_PTE_SNOOPED; | |
904 | } | |
d38ceaf9 | 905 | |
8f3c1629 | 906 | if (adev->asic_type >= CHIP_TONGA) |
d38ceaf9 AD |
907 | flags |= AMDGPU_PTE_EXECUTABLE; |
908 | ||
909 | flags |= AMDGPU_PTE_READABLE; | |
910 | ||
911 | if (!amdgpu_ttm_tt_is_readonly(ttm)) | |
912 | flags |= AMDGPU_PTE_WRITEABLE; | |
913 | ||
914 | return flags; | |
915 | } | |
916 | ||
29b3259a CK |
917 | static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo) |
918 | { | |
919 | struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); | |
920 | unsigned i, j; | |
921 | ||
922 | for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { | |
923 | struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; | |
924 | ||
925 | for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) | |
926 | if (&tbo->lru == lru->lru[j]) | |
927 | lru->lru[j] = tbo->lru.prev; | |
928 | ||
929 | if (&tbo->swap == lru->swap_lru) | |
930 | lru->swap_lru = tbo->swap.prev; | |
931 | } | |
932 | } | |
933 | ||
934 | static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo) | |
935 | { | |
936 | struct amdgpu_device *adev = amdgpu_get_adev(tbo->bdev); | |
937 | unsigned log2_size = min(ilog2(tbo->num_pages), | |
938 | AMDGPU_TTM_LRU_SIZE - 1); | |
939 | ||
940 | return &adev->mman.log2_size[log2_size]; | |
941 | } | |
942 | ||
943 | static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo) | |
944 | { | |
945 | struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); | |
946 | struct list_head *res = lru->lru[tbo->mem.mem_type]; | |
947 | ||
948 | lru->lru[tbo->mem.mem_type] = &tbo->lru; | |
56615387 CK |
949 | while ((++lru)->lru[tbo->mem.mem_type] == res) |
950 | lru->lru[tbo->mem.mem_type] = &tbo->lru; | |
29b3259a CK |
951 | |
952 | return res; | |
953 | } | |
954 | ||
955 | static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo) | |
956 | { | |
957 | struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo); | |
958 | struct list_head *res = lru->swap_lru; | |
959 | ||
960 | lru->swap_lru = &tbo->swap; | |
56615387 CK |
961 | while ((++lru)->swap_lru == res) |
962 | lru->swap_lru = &tbo->swap; | |
29b3259a CK |
963 | |
964 | return res; | |
965 | } | |
966 | ||
d38ceaf9 AD |
967 | static struct ttm_bo_driver amdgpu_bo_driver = { |
968 | .ttm_tt_create = &amdgpu_ttm_tt_create, | |
969 | .ttm_tt_populate = &amdgpu_ttm_tt_populate, | |
970 | .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, | |
971 | .invalidate_caches = &amdgpu_invalidate_caches, | |
972 | .init_mem_type = &amdgpu_init_mem_type, | |
973 | .evict_flags = &amdgpu_evict_flags, | |
974 | .move = &amdgpu_bo_move, | |
975 | .verify_access = &amdgpu_verify_access, | |
976 | .move_notify = &amdgpu_bo_move_notify, | |
977 | .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify, | |
978 | .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, | |
979 | .io_mem_free = &amdgpu_ttm_io_mem_free, | |
29b3259a CK |
980 | .lru_removal = &amdgpu_ttm_lru_removal, |
981 | .lru_tail = &amdgpu_ttm_lru_tail, | |
982 | .swap_lru_tail = &amdgpu_ttm_swap_lru_tail, | |
d38ceaf9 AD |
983 | }; |
984 | ||
985 | int amdgpu_ttm_init(struct amdgpu_device *adev) | |
986 | { | |
29b3259a | 987 | unsigned i, j; |
d38ceaf9 AD |
988 | int r; |
989 | ||
d38ceaf9 AD |
990 | /* No others user of address space so set it to 0 */ |
991 | r = ttm_bo_device_init(&adev->mman.bdev, | |
992 | adev->mman.bo_global_ref.ref.object, | |
993 | &amdgpu_bo_driver, | |
994 | adev->ddev->anon_inode->i_mapping, | |
995 | DRM_FILE_PAGE_OFFSET, | |
996 | adev->need_dma32); | |
997 | if (r) { | |
998 | DRM_ERROR("failed initializing buffer object driver(%d).\n", r); | |
999 | return r; | |
1000 | } | |
29b3259a CK |
1001 | |
1002 | for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) { | |
1003 | struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i]; | |
1004 | ||
1005 | for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) | |
1006 | lru->lru[j] = &adev->mman.bdev.man[j].lru; | |
1007 | lru->swap_lru = &adev->mman.bdev.glob->swap_lru; | |
1008 | } | |
1009 | ||
56615387 CK |
1010 | for (j = 0; j < TTM_NUM_MEM_TYPES; ++j) |
1011 | adev->mman.guard.lru[j] = NULL; | |
1012 | adev->mman.guard.swap_lru = NULL; | |
1013 | ||
d38ceaf9 AD |
1014 | adev->mman.initialized = true; |
1015 | r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, | |
1016 | adev->mc.real_vram_size >> PAGE_SHIFT); | |
1017 | if (r) { | |
1018 | DRM_ERROR("Failed initializing VRAM heap.\n"); | |
1019 | return r; | |
1020 | } | |
1021 | /* Change the size here instead of the init above so only lpfn is affected */ | |
1022 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
1023 | ||
1024 | r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true, | |
857d913d AD |
1025 | AMDGPU_GEM_DOMAIN_VRAM, |
1026 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, | |
72d7668b | 1027 | NULL, NULL, &adev->stollen_vga_memory); |
d38ceaf9 AD |
1028 | if (r) { |
1029 | return r; | |
1030 | } | |
1031 | r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); | |
1032 | if (r) | |
1033 | return r; | |
1034 | r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); | |
1035 | amdgpu_bo_unreserve(adev->stollen_vga_memory); | |
1036 | if (r) { | |
1037 | amdgpu_bo_unref(&adev->stollen_vga_memory); | |
1038 | return r; | |
1039 | } | |
1040 | DRM_INFO("amdgpu: %uM of VRAM memory ready\n", | |
1041 | (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); | |
1042 | r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, | |
1043 | adev->mc.gtt_size >> PAGE_SHIFT); | |
1044 | if (r) { | |
1045 | DRM_ERROR("Failed initializing GTT heap.\n"); | |
1046 | return r; | |
1047 | } | |
1048 | DRM_INFO("amdgpu: %uM of GTT memory ready.\n", | |
1049 | (unsigned)(adev->mc.gtt_size / (1024 * 1024))); | |
1050 | ||
1051 | adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT; | |
1052 | adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT; | |
1053 | adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT; | |
1054 | adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT; | |
1055 | adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT; | |
1056 | adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT; | |
1057 | adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT; | |
1058 | adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT; | |
1059 | adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT; | |
1060 | /* GDS Memory */ | |
1061 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, | |
1062 | adev->gds.mem.total_size >> PAGE_SHIFT); | |
1063 | if (r) { | |
1064 | DRM_ERROR("Failed initializing GDS heap.\n"); | |
1065 | return r; | |
1066 | } | |
1067 | ||
1068 | /* GWS */ | |
1069 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, | |
1070 | adev->gds.gws.total_size >> PAGE_SHIFT); | |
1071 | if (r) { | |
1072 | DRM_ERROR("Failed initializing gws heap.\n"); | |
1073 | return r; | |
1074 | } | |
1075 | ||
1076 | /* OA */ | |
1077 | r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, | |
1078 | adev->gds.oa.total_size >> PAGE_SHIFT); | |
1079 | if (r) { | |
1080 | DRM_ERROR("Failed initializing oa heap.\n"); | |
1081 | return r; | |
1082 | } | |
1083 | ||
1084 | r = amdgpu_ttm_debugfs_init(adev); | |
1085 | if (r) { | |
1086 | DRM_ERROR("Failed to init debugfs\n"); | |
1087 | return r; | |
1088 | } | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | void amdgpu_ttm_fini(struct amdgpu_device *adev) | |
1093 | { | |
1094 | int r; | |
1095 | ||
1096 | if (!adev->mman.initialized) | |
1097 | return; | |
1098 | amdgpu_ttm_debugfs_fini(adev); | |
1099 | if (adev->stollen_vga_memory) { | |
1100 | r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); | |
1101 | if (r == 0) { | |
1102 | amdgpu_bo_unpin(adev->stollen_vga_memory); | |
1103 | amdgpu_bo_unreserve(adev->stollen_vga_memory); | |
1104 | } | |
1105 | amdgpu_bo_unref(&adev->stollen_vga_memory); | |
1106 | } | |
1107 | ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); | |
1108 | ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); | |
1109 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS); | |
1110 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS); | |
1111 | ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); | |
1112 | ttm_bo_device_release(&adev->mman.bdev); | |
1113 | amdgpu_gart_fini(adev); | |
1114 | amdgpu_ttm_global_fini(adev); | |
1115 | adev->mman.initialized = false; | |
1116 | DRM_INFO("amdgpu: ttm finalized\n"); | |
1117 | } | |
1118 | ||
1119 | /* this should only be called at bootup or when userspace | |
1120 | * isn't running */ | |
1121 | void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size) | |
1122 | { | |
1123 | struct ttm_mem_type_manager *man; | |
1124 | ||
1125 | if (!adev->mman.initialized) | |
1126 | return; | |
1127 | ||
1128 | man = &adev->mman.bdev.man[TTM_PL_VRAM]; | |
1129 | /* this just adjusts TTM size idea, which sets lpfn to the correct value */ | |
1130 | man->size = size >> PAGE_SHIFT; | |
1131 | } | |
1132 | ||
d38ceaf9 AD |
1133 | int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) |
1134 | { | |
1135 | struct drm_file *file_priv; | |
1136 | struct amdgpu_device *adev; | |
d38ceaf9 | 1137 | |
e176fe17 | 1138 | if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) |
d38ceaf9 | 1139 | return -EINVAL; |
d38ceaf9 AD |
1140 | |
1141 | file_priv = filp->private_data; | |
1142 | adev = file_priv->minor->dev->dev_private; | |
e176fe17 | 1143 | if (adev == NULL) |
d38ceaf9 | 1144 | return -EINVAL; |
e176fe17 CK |
1145 | |
1146 | return ttm_bo_mmap(filp, vma, &adev->mman.bdev); | |
d38ceaf9 AD |
1147 | } |
1148 | ||
1149 | int amdgpu_copy_buffer(struct amdgpu_ring *ring, | |
1150 | uint64_t src_offset, | |
1151 | uint64_t dst_offset, | |
1152 | uint32_t byte_count, | |
1153 | struct reservation_object *resv, | |
e24db985 | 1154 | struct fence **fence, bool direct_submit) |
d38ceaf9 AD |
1155 | { |
1156 | struct amdgpu_device *adev = ring->adev; | |
d71518b5 CK |
1157 | struct amdgpu_job *job; |
1158 | ||
d38ceaf9 AD |
1159 | uint32_t max_bytes; |
1160 | unsigned num_loops, num_dw; | |
1161 | unsigned i; | |
1162 | int r; | |
1163 | ||
d38ceaf9 AD |
1164 | max_bytes = adev->mman.buffer_funcs->copy_max_bytes; |
1165 | num_loops = DIV_ROUND_UP(byte_count, max_bytes); | |
1166 | num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw; | |
1167 | ||
c7ae72c0 CZ |
1168 | /* for IB padding */ |
1169 | while (num_dw & 0x7) | |
1170 | num_dw++; | |
1171 | ||
d71518b5 CK |
1172 | r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); |
1173 | if (r) | |
9066b0c3 | 1174 | return r; |
c7ae72c0 CZ |
1175 | |
1176 | if (resv) { | |
e86f9cee | 1177 | r = amdgpu_sync_resv(adev, &job->sync, resv, |
c7ae72c0 CZ |
1178 | AMDGPU_FENCE_OWNER_UNDEFINED); |
1179 | if (r) { | |
1180 | DRM_ERROR("sync failed (%d).\n", r); | |
1181 | goto error_free; | |
1182 | } | |
d38ceaf9 | 1183 | } |
d38ceaf9 AD |
1184 | |
1185 | for (i = 0; i < num_loops; i++) { | |
1186 | uint32_t cur_size_in_bytes = min(byte_count, max_bytes); | |
1187 | ||
d71518b5 CK |
1188 | amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, |
1189 | dst_offset, cur_size_in_bytes); | |
d38ceaf9 AD |
1190 | |
1191 | src_offset += cur_size_in_bytes; | |
1192 | dst_offset += cur_size_in_bytes; | |
1193 | byte_count -= cur_size_in_bytes; | |
1194 | } | |
1195 | ||
d71518b5 CK |
1196 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
1197 | WARN_ON(job->ibs[0].length_dw > num_dw); | |
e24db985 CZ |
1198 | if (direct_submit) { |
1199 | r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, | |
1200 | NULL, NULL, fence); | |
1201 | job->fence = fence_get(*fence); | |
1202 | if (r) | |
1203 | DRM_ERROR("Error scheduling IBs (%d)\n", r); | |
1204 | amdgpu_job_free(job); | |
1205 | } else { | |
1206 | r = amdgpu_job_submit(job, ring, &adev->mman.entity, | |
1207 | AMDGPU_FENCE_OWNER_UNDEFINED, fence); | |
1208 | if (r) | |
1209 | goto error_free; | |
1210 | } | |
d38ceaf9 | 1211 | |
e24db985 | 1212 | return r; |
d71518b5 | 1213 | |
c7ae72c0 | 1214 | error_free: |
d71518b5 | 1215 | amdgpu_job_free(job); |
c7ae72c0 | 1216 | return r; |
d38ceaf9 AD |
1217 | } |
1218 | ||
59b4a977 FC |
1219 | int amdgpu_fill_buffer(struct amdgpu_bo *bo, |
1220 | uint32_t src_data, | |
1221 | struct reservation_object *resv, | |
1222 | struct fence **fence) | |
1223 | { | |
1224 | struct amdgpu_device *adev = bo->adev; | |
1225 | struct amdgpu_job *job; | |
1226 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
1227 | ||
1228 | uint32_t max_bytes, byte_count; | |
1229 | uint64_t dst_offset; | |
1230 | unsigned int num_loops, num_dw; | |
1231 | unsigned int i; | |
1232 | int r; | |
1233 | ||
1234 | byte_count = bo->tbo.num_pages << PAGE_SHIFT; | |
1235 | max_bytes = adev->mman.buffer_funcs->fill_max_bytes; | |
1236 | num_loops = DIV_ROUND_UP(byte_count, max_bytes); | |
1237 | num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; | |
1238 | ||
1239 | /* for IB padding */ | |
1240 | while (num_dw & 0x7) | |
1241 | num_dw++; | |
1242 | ||
1243 | r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job); | |
1244 | if (r) | |
1245 | return r; | |
1246 | ||
1247 | if (resv) { | |
1248 | r = amdgpu_sync_resv(adev, &job->sync, resv, | |
1249 | AMDGPU_FENCE_OWNER_UNDEFINED); | |
1250 | if (r) { | |
1251 | DRM_ERROR("sync failed (%d).\n", r); | |
1252 | goto error_free; | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | dst_offset = bo->tbo.mem.start << PAGE_SHIFT; | |
1257 | for (i = 0; i < num_loops; i++) { | |
1258 | uint32_t cur_size_in_bytes = min(byte_count, max_bytes); | |
1259 | ||
1260 | amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, | |
1261 | dst_offset, cur_size_in_bytes); | |
1262 | ||
1263 | dst_offset += cur_size_in_bytes; | |
1264 | byte_count -= cur_size_in_bytes; | |
1265 | } | |
1266 | ||
d71518b5 CK |
1267 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
1268 | WARN_ON(job->ibs[0].length_dw > num_dw); | |
703297c1 | 1269 | r = amdgpu_job_submit(job, ring, &adev->mman.entity, |
59b4a977 | 1270 | AMDGPU_FENCE_OWNER_UNDEFINED, fence); |
c7ae72c0 CZ |
1271 | if (r) |
1272 | goto error_free; | |
d38ceaf9 AD |
1273 | |
1274 | return 0; | |
d71518b5 | 1275 | |
c7ae72c0 | 1276 | error_free: |
d71518b5 | 1277 | amdgpu_job_free(job); |
c7ae72c0 | 1278 | return r; |
d38ceaf9 AD |
1279 | } |
1280 | ||
1281 | #if defined(CONFIG_DEBUG_FS) | |
1282 | ||
1283 | static int amdgpu_mm_dump_table(struct seq_file *m, void *data) | |
1284 | { | |
1285 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
1286 | unsigned ttm_pl = *(int *)node->info_ent->data; | |
1287 | struct drm_device *dev = node->minor->dev; | |
1288 | struct amdgpu_device *adev = dev->dev_private; | |
1289 | struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; | |
1290 | int ret; | |
1291 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
1292 | ||
1293 | spin_lock(&glob->lru_lock); | |
1294 | ret = drm_mm_dump_table(m, mm); | |
1295 | spin_unlock(&glob->lru_lock); | |
a2ef8a97 | 1296 | if (ttm_pl == TTM_PL_VRAM) |
e1b35f61 | 1297 | seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", |
a2ef8a97 | 1298 | adev->mman.bdev.man[ttm_pl].size, |
e1b35f61 AB |
1299 | (u64)atomic64_read(&adev->vram_usage) >> 20, |
1300 | (u64)atomic64_read(&adev->vram_vis_usage) >> 20); | |
d38ceaf9 AD |
1301 | return ret; |
1302 | } | |
1303 | ||
1304 | static int ttm_pl_vram = TTM_PL_VRAM; | |
1305 | static int ttm_pl_tt = TTM_PL_TT; | |
1306 | ||
06ab6832 | 1307 | static const struct drm_info_list amdgpu_ttm_debugfs_list[] = { |
d38ceaf9 AD |
1308 | {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram}, |
1309 | {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt}, | |
1310 | {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, | |
1311 | #ifdef CONFIG_SWIOTLB | |
1312 | {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} | |
1313 | #endif | |
1314 | }; | |
1315 | ||
1316 | static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, | |
1317 | size_t size, loff_t *pos) | |
1318 | { | |
1319 | struct amdgpu_device *adev = f->f_inode->i_private; | |
1320 | ssize_t result = 0; | |
1321 | int r; | |
1322 | ||
1323 | if (size & 0x3 || *pos & 0x3) | |
1324 | return -EINVAL; | |
1325 | ||
1326 | while (size) { | |
1327 | unsigned long flags; | |
1328 | uint32_t value; | |
1329 | ||
1330 | if (*pos >= adev->mc.mc_vram_size) | |
1331 | return result; | |
1332 | ||
1333 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
1334 | WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); | |
1335 | WREG32(mmMM_INDEX_HI, *pos >> 31); | |
1336 | value = RREG32(mmMM_DATA); | |
1337 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
1338 | ||
1339 | r = put_user(value, (uint32_t *)buf); | |
1340 | if (r) | |
1341 | return r; | |
1342 | ||
1343 | result += 4; | |
1344 | buf += 4; | |
1345 | *pos += 4; | |
1346 | size -= 4; | |
1347 | } | |
1348 | ||
1349 | return result; | |
1350 | } | |
1351 | ||
1352 | static const struct file_operations amdgpu_ttm_vram_fops = { | |
1353 | .owner = THIS_MODULE, | |
1354 | .read = amdgpu_ttm_vram_read, | |
1355 | .llseek = default_llseek | |
1356 | }; | |
1357 | ||
a1d29476 CK |
1358 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS |
1359 | ||
d38ceaf9 AD |
1360 | static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf, |
1361 | size_t size, loff_t *pos) | |
1362 | { | |
1363 | struct amdgpu_device *adev = f->f_inode->i_private; | |
1364 | ssize_t result = 0; | |
1365 | int r; | |
1366 | ||
1367 | while (size) { | |
1368 | loff_t p = *pos / PAGE_SIZE; | |
1369 | unsigned off = *pos & ~PAGE_MASK; | |
1370 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); | |
1371 | struct page *page; | |
1372 | void *ptr; | |
1373 | ||
1374 | if (p >= adev->gart.num_cpu_pages) | |
1375 | return result; | |
1376 | ||
1377 | page = adev->gart.pages[p]; | |
1378 | if (page) { | |
1379 | ptr = kmap(page); | |
1380 | ptr += off; | |
1381 | ||
1382 | r = copy_to_user(buf, ptr, cur_size); | |
1383 | kunmap(adev->gart.pages[p]); | |
1384 | } else | |
1385 | r = clear_user(buf, cur_size); | |
1386 | ||
1387 | if (r) | |
1388 | return -EFAULT; | |
1389 | ||
1390 | result += cur_size; | |
1391 | buf += cur_size; | |
1392 | *pos += cur_size; | |
1393 | size -= cur_size; | |
1394 | } | |
1395 | ||
1396 | return result; | |
1397 | } | |
1398 | ||
1399 | static const struct file_operations amdgpu_ttm_gtt_fops = { | |
1400 | .owner = THIS_MODULE, | |
1401 | .read = amdgpu_ttm_gtt_read, | |
1402 | .llseek = default_llseek | |
1403 | }; | |
1404 | ||
1405 | #endif | |
1406 | ||
a1d29476 CK |
1407 | #endif |
1408 | ||
d38ceaf9 AD |
1409 | static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) |
1410 | { | |
1411 | #if defined(CONFIG_DEBUG_FS) | |
1412 | unsigned count; | |
1413 | ||
1414 | struct drm_minor *minor = adev->ddev->primary; | |
1415 | struct dentry *ent, *root = minor->debugfs_root; | |
1416 | ||
1417 | ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root, | |
1418 | adev, &amdgpu_ttm_vram_fops); | |
1419 | if (IS_ERR(ent)) | |
1420 | return PTR_ERR(ent); | |
1421 | i_size_write(ent->d_inode, adev->mc.mc_vram_size); | |
1422 | adev->mman.vram = ent; | |
1423 | ||
a1d29476 | 1424 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS |
d38ceaf9 AD |
1425 | ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root, |
1426 | adev, &amdgpu_ttm_gtt_fops); | |
1427 | if (IS_ERR(ent)) | |
1428 | return PTR_ERR(ent); | |
1429 | i_size_write(ent->d_inode, adev->mc.gtt_size); | |
1430 | adev->mman.gtt = ent; | |
1431 | ||
a1d29476 | 1432 | #endif |
d38ceaf9 AD |
1433 | count = ARRAY_SIZE(amdgpu_ttm_debugfs_list); |
1434 | ||
1435 | #ifdef CONFIG_SWIOTLB | |
1436 | if (!swiotlb_nr_tbl()) | |
1437 | --count; | |
1438 | #endif | |
1439 | ||
1440 | return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count); | |
1441 | #else | |
1442 | ||
1443 | return 0; | |
1444 | #endif | |
1445 | } | |
1446 | ||
1447 | static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev) | |
1448 | { | |
1449 | #if defined(CONFIG_DEBUG_FS) | |
1450 | ||
1451 | debugfs_remove(adev->mman.vram); | |
1452 | adev->mman.vram = NULL; | |
1453 | ||
a1d29476 | 1454 | #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS |
d38ceaf9 AD |
1455 | debugfs_remove(adev->mman.gtt); |
1456 | adev->mman.gtt = NULL; | |
1457 | #endif | |
a1d29476 CK |
1458 | |
1459 | #endif | |
d38ceaf9 | 1460 | } |
a693e050 KW |
1461 | |
1462 | u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev) | |
1463 | { | |
1464 | return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object); | |
1465 | } |