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drm/amdgpu: remove AMDGPU_GEM_CREATE_CPU_GTT_UC
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "bif/bif_4_1_d.h"
47
48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
51static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
52
53static struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
54{
55 struct amdgpu_mman *mman;
56 struct amdgpu_device *adev;
57
58 mman = container_of(bdev, struct amdgpu_mman, bdev);
59 adev = container_of(mman, struct amdgpu_device, mman);
60 return adev;
61}
62
63
64/*
65 * Global memory.
66 */
67static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
68{
69 return ttm_mem_global_init(ref->object);
70}
71
72static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
73{
74 ttm_mem_global_release(ref->object);
75}
76
77static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
78{
79 struct drm_global_reference *global_ref;
80 int r;
81
82 adev->mman.mem_global_referenced = false;
83 global_ref = &adev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &amdgpu_ttm_mem_global_init;
87 global_ref->release = &amdgpu_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
89 if (r != 0) {
90 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
92 return r;
93 }
94
95 adev->mman.bo_global_ref.mem_glob =
96 adev->mman.mem_global_ref.object;
97 global_ref = &adev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&adev->mman.mem_global_ref);
106 return r;
107 }
108
109 adev->mman.mem_global_referenced = true;
110 return 0;
111}
112
113static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
114{
115 if (adev->mman.mem_global_referenced) {
116 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&adev->mman.mem_global_ref);
118 adev->mman.mem_global_referenced = false;
119 }
120}
121
122static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123{
124 return 0;
125}
126
127static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129{
130 struct amdgpu_device *adev;
131
132 adev = amdgpu_get_adev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = adev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
147 break;
148 case TTM_PL_VRAM:
149 /* "On-card" video ram */
150 man->func = &ttm_bo_manager_func;
151 man->gpu_offset = adev->mc.vram_start;
152 man->flags = TTM_MEMTYPE_FLAG_FIXED |
153 TTM_MEMTYPE_FLAG_MAPPABLE;
154 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
155 man->default_caching = TTM_PL_FLAG_WC;
156 break;
157 case AMDGPU_PL_GDS:
158 case AMDGPU_PL_GWS:
159 case AMDGPU_PL_OA:
160 /* On-chip GDS memory*/
161 man->func = &ttm_bo_manager_func;
162 man->gpu_offset = 0;
163 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
164 man->available_caching = TTM_PL_FLAG_UNCACHED;
165 man->default_caching = TTM_PL_FLAG_UNCACHED;
166 break;
167 default:
168 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
169 return -EINVAL;
170 }
171 return 0;
172}
173
174static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
175 struct ttm_placement *placement)
176{
177 struct amdgpu_bo *rbo;
178 static struct ttm_place placements = {
179 .fpfn = 0,
180 .lpfn = 0,
181 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
182 };
183
184 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
185 placement->placement = &placements;
186 placement->busy_placement = &placements;
187 placement->num_placement = 1;
188 placement->num_busy_placement = 1;
189 return;
190 }
191 rbo = container_of(bo, struct amdgpu_bo, tbo);
192 switch (bo->mem.mem_type) {
193 case TTM_PL_VRAM:
194 if (rbo->adev->mman.buffer_funcs_ring->ready == false)
195 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
196 else
197 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_GTT);
198 break;
199 case TTM_PL_TT:
200 default:
201 amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_CPU);
202 }
203 *placement = rbo->placement;
204}
205
206static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
207{
208 struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
209
210 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
211}
212
213static void amdgpu_move_null(struct ttm_buffer_object *bo,
214 struct ttm_mem_reg *new_mem)
215{
216 struct ttm_mem_reg *old_mem = &bo->mem;
217
218 BUG_ON(old_mem->mm_node != NULL);
219 *old_mem = *new_mem;
220 new_mem->mm_node = NULL;
221}
222
223static int amdgpu_move_blit(struct ttm_buffer_object *bo,
224 bool evict, bool no_wait_gpu,
225 struct ttm_mem_reg *new_mem,
226 struct ttm_mem_reg *old_mem)
227{
228 struct amdgpu_device *adev;
229 struct amdgpu_ring *ring;
230 uint64_t old_start, new_start;
231 struct amdgpu_fence *fence;
232 int r;
233
234 adev = amdgpu_get_adev(bo->bdev);
235 ring = adev->mman.buffer_funcs_ring;
236 old_start = old_mem->start << PAGE_SHIFT;
237 new_start = new_mem->start << PAGE_SHIFT;
238
239 switch (old_mem->mem_type) {
240 case TTM_PL_VRAM:
241 old_start += adev->mc.vram_start;
242 break;
243 case TTM_PL_TT:
244 old_start += adev->mc.gtt_start;
245 break;
246 default:
247 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
248 return -EINVAL;
249 }
250 switch (new_mem->mem_type) {
251 case TTM_PL_VRAM:
252 new_start += adev->mc.vram_start;
253 break;
254 case TTM_PL_TT:
255 new_start += adev->mc.gtt_start;
256 break;
257 default:
258 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
259 return -EINVAL;
260 }
261 if (!ring->ready) {
262 DRM_ERROR("Trying to move memory with ring turned off.\n");
263 return -EINVAL;
264 }
265
266 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
267
268 r = amdgpu_copy_buffer(ring, old_start, new_start,
269 new_mem->num_pages * PAGE_SIZE, /* bytes */
270 bo->resv, &fence);
271 /* FIXME: handle copy error */
272 r = ttm_bo_move_accel_cleanup(bo, &fence->base,
273 evict, no_wait_gpu, new_mem);
274 amdgpu_fence_unref(&fence);
275 return r;
276}
277
278static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
279 bool evict, bool interruptible,
280 bool no_wait_gpu,
281 struct ttm_mem_reg *new_mem)
282{
283 struct amdgpu_device *adev;
284 struct ttm_mem_reg *old_mem = &bo->mem;
285 struct ttm_mem_reg tmp_mem;
286 struct ttm_place placements;
287 struct ttm_placement placement;
288 int r;
289
290 adev = amdgpu_get_adev(bo->bdev);
291 tmp_mem = *new_mem;
292 tmp_mem.mm_node = NULL;
293 placement.num_placement = 1;
294 placement.placement = &placements;
295 placement.num_busy_placement = 1;
296 placement.busy_placement = &placements;
297 placements.fpfn = 0;
298 placements.lpfn = 0;
299 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
300 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
301 interruptible, no_wait_gpu);
302 if (unlikely(r)) {
303 return r;
304 }
305
306 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
307 if (unlikely(r)) {
308 goto out_cleanup;
309 }
310
311 r = ttm_tt_bind(bo->ttm, &tmp_mem);
312 if (unlikely(r)) {
313 goto out_cleanup;
314 }
315 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
316 if (unlikely(r)) {
317 goto out_cleanup;
318 }
319 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
320out_cleanup:
321 ttm_bo_mem_put(bo, &tmp_mem);
322 return r;
323}
324
325static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
326 bool evict, bool interruptible,
327 bool no_wait_gpu,
328 struct ttm_mem_reg *new_mem)
329{
330 struct amdgpu_device *adev;
331 struct ttm_mem_reg *old_mem = &bo->mem;
332 struct ttm_mem_reg tmp_mem;
333 struct ttm_placement placement;
334 struct ttm_place placements;
335 int r;
336
337 adev = amdgpu_get_adev(bo->bdev);
338 tmp_mem = *new_mem;
339 tmp_mem.mm_node = NULL;
340 placement.num_placement = 1;
341 placement.placement = &placements;
342 placement.num_busy_placement = 1;
343 placement.busy_placement = &placements;
344 placements.fpfn = 0;
345 placements.lpfn = 0;
346 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
347 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
348 interruptible, no_wait_gpu);
349 if (unlikely(r)) {
350 return r;
351 }
352 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
353 if (unlikely(r)) {
354 goto out_cleanup;
355 }
356 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
357 if (unlikely(r)) {
358 goto out_cleanup;
359 }
360out_cleanup:
361 ttm_bo_mem_put(bo, &tmp_mem);
362 return r;
363}
364
365static int amdgpu_bo_move(struct ttm_buffer_object *bo,
366 bool evict, bool interruptible,
367 bool no_wait_gpu,
368 struct ttm_mem_reg *new_mem)
369{
370 struct amdgpu_device *adev;
371 struct ttm_mem_reg *old_mem = &bo->mem;
372 int r;
373
374 adev = amdgpu_get_adev(bo->bdev);
375 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
376 amdgpu_move_null(bo, new_mem);
377 return 0;
378 }
379 if ((old_mem->mem_type == TTM_PL_TT &&
380 new_mem->mem_type == TTM_PL_SYSTEM) ||
381 (old_mem->mem_type == TTM_PL_SYSTEM &&
382 new_mem->mem_type == TTM_PL_TT)) {
383 /* bind is enough */
384 amdgpu_move_null(bo, new_mem);
385 return 0;
386 }
387 if (adev->mman.buffer_funcs == NULL ||
388 adev->mman.buffer_funcs_ring == NULL ||
389 !adev->mman.buffer_funcs_ring->ready) {
390 /* use memcpy */
391 goto memcpy;
392 }
393
394 if (old_mem->mem_type == TTM_PL_VRAM &&
395 new_mem->mem_type == TTM_PL_SYSTEM) {
396 r = amdgpu_move_vram_ram(bo, evict, interruptible,
397 no_wait_gpu, new_mem);
398 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
399 new_mem->mem_type == TTM_PL_VRAM) {
400 r = amdgpu_move_ram_vram(bo, evict, interruptible,
401 no_wait_gpu, new_mem);
402 } else {
403 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
404 }
405
406 if (r) {
407memcpy:
408 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
409 if (r) {
410 return r;
411 }
412 }
413
414 /* update statistics */
415 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
416 return 0;
417}
418
419static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
420{
421 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
422 struct amdgpu_device *adev = amdgpu_get_adev(bdev);
423
424 mem->bus.addr = NULL;
425 mem->bus.offset = 0;
426 mem->bus.size = mem->num_pages << PAGE_SHIFT;
427 mem->bus.base = 0;
428 mem->bus.is_iomem = false;
429 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
430 return -EINVAL;
431 switch (mem->mem_type) {
432 case TTM_PL_SYSTEM:
433 /* system memory */
434 return 0;
435 case TTM_PL_TT:
436 break;
437 case TTM_PL_VRAM:
438 mem->bus.offset = mem->start << PAGE_SHIFT;
439 /* check if it's visible */
440 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
441 return -EINVAL;
442 mem->bus.base = adev->mc.aper_base;
443 mem->bus.is_iomem = true;
444#ifdef __alpha__
445 /*
446 * Alpha: use bus.addr to hold the ioremap() return,
447 * so we can modify bus.base below.
448 */
449 if (mem->placement & TTM_PL_FLAG_WC)
450 mem->bus.addr =
451 ioremap_wc(mem->bus.base + mem->bus.offset,
452 mem->bus.size);
453 else
454 mem->bus.addr =
455 ioremap_nocache(mem->bus.base + mem->bus.offset,
456 mem->bus.size);
457
458 /*
459 * Alpha: Use just the bus offset plus
460 * the hose/domain memory base for bus.base.
461 * It then can be used to build PTEs for VRAM
462 * access, as done in ttm_bo_vm_fault().
463 */
464 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
465 adev->ddev->hose->dense_mem_base;
466#endif
467 break;
468 default:
469 return -EINVAL;
470 }
471 return 0;
472}
473
474static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
475{
476}
477
478/*
479 * TTM backend functions.
480 */
481struct amdgpu_ttm_tt {
482 struct ttm_dma_tt ttm;
483 struct amdgpu_device *adev;
484 u64 offset;
485 uint64_t userptr;
486 struct mm_struct *usermm;
487 uint32_t userflags;
488};
489
490/* prepare the sg table with the user pages */
491static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
492{
493 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
494 struct amdgpu_ttm_tt *gtt = (void *)ttm;
495 unsigned pinned = 0, nents;
496 int r;
497
498 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
499 enum dma_data_direction direction = write ?
500 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
501
502 if (current->mm != gtt->usermm)
503 return -EPERM;
504
505 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
506 /* check that we only pin down anonymous memory
507 to prevent problems with writeback */
508 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
509 struct vm_area_struct *vma;
510
511 vma = find_vma(gtt->usermm, gtt->userptr);
512 if (!vma || vma->vm_file || vma->vm_end < end)
513 return -EPERM;
514 }
515
516 do {
517 unsigned num_pages = ttm->num_pages - pinned;
518 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
519 struct page **pages = ttm->pages + pinned;
520
521 r = get_user_pages(current, current->mm, userptr, num_pages,
522 write, 0, pages, NULL);
523 if (r < 0)
524 goto release_pages;
525
526 pinned += r;
527
528 } while (pinned < ttm->num_pages);
529
530 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
531 ttm->num_pages << PAGE_SHIFT,
532 GFP_KERNEL);
533 if (r)
534 goto release_sg;
535
536 r = -ENOMEM;
537 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
538 if (nents != ttm->sg->nents)
539 goto release_sg;
540
541 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
542 gtt->ttm.dma_address, ttm->num_pages);
543
544 return 0;
545
546release_sg:
547 kfree(ttm->sg);
548
549release_pages:
550 release_pages(ttm->pages, pinned, 0);
551 return r;
552}
553
554static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
555{
556 struct amdgpu_device *adev = amdgpu_get_adev(ttm->bdev);
557 struct amdgpu_ttm_tt *gtt = (void *)ttm;
558 struct scatterlist *sg;
559 int i;
560
561 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
562 enum dma_data_direction direction = write ?
563 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
564
565 /* double check that we don't free the table twice */
566 if (!ttm->sg->sgl)
567 return;
568
569 /* free the sg table and pages again */
570 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
571
572 for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) {
573 struct page *page = sg_page(sg);
574
575 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
576 set_page_dirty(page);
577
578 mark_page_accessed(page);
579 page_cache_release(page);
580 }
581
582 sg_free_table(ttm->sg);
583}
584
585static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
586 struct ttm_mem_reg *bo_mem)
587{
588 struct amdgpu_ttm_tt *gtt = (void*)ttm;
589 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
590 int r;
591
592 if (gtt->userptr)
593 amdgpu_ttm_tt_pin_userptr(ttm);
594
595 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
596 if (!ttm->num_pages) {
597 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
598 ttm->num_pages, bo_mem, ttm);
599 }
600
601 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
602 bo_mem->mem_type == AMDGPU_PL_GWS ||
603 bo_mem->mem_type == AMDGPU_PL_OA)
604 return -EINVAL;
605
606 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
607 ttm->pages, gtt->ttm.dma_address, flags);
608
609 if (r) {
610 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
611 ttm->num_pages, (unsigned)gtt->offset);
612 return r;
613 }
614 return 0;
615}
616
617static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
618{
619 struct amdgpu_ttm_tt *gtt = (void *)ttm;
620
621 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
622 if (gtt->adev->gart.ready)
623 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
624
625 if (gtt->userptr)
626 amdgpu_ttm_tt_unpin_userptr(ttm);
627
628 return 0;
629}
630
631static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
632{
633 struct amdgpu_ttm_tt *gtt = (void *)ttm;
634
635 ttm_dma_tt_fini(&gtt->ttm);
636 kfree(gtt);
637}
638
639static struct ttm_backend_func amdgpu_backend_func = {
640 .bind = &amdgpu_ttm_backend_bind,
641 .unbind = &amdgpu_ttm_backend_unbind,
642 .destroy = &amdgpu_ttm_backend_destroy,
643};
644
645static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
646 unsigned long size, uint32_t page_flags,
647 struct page *dummy_read_page)
648{
649 struct amdgpu_device *adev;
650 struct amdgpu_ttm_tt *gtt;
651
652 adev = amdgpu_get_adev(bdev);
653
654 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
655 if (gtt == NULL) {
656 return NULL;
657 }
658 gtt->ttm.ttm.func = &amdgpu_backend_func;
659 gtt->adev = adev;
660 if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
661 kfree(gtt);
662 return NULL;
663 }
664 return &gtt->ttm.ttm;
665}
666
667static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
668{
669 struct amdgpu_device *adev;
670 struct amdgpu_ttm_tt *gtt = (void *)ttm;
671 unsigned i;
672 int r;
673 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
674
675 if (ttm->state != tt_unpopulated)
676 return 0;
677
678 if (gtt && gtt->userptr) {
679 ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL);
680 if (!ttm->sg)
681 return -ENOMEM;
682
683 ttm->page_flags |= TTM_PAGE_FLAG_SG;
684 ttm->state = tt_unbound;
685 return 0;
686 }
687
688 if (slave && ttm->sg) {
689 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
690 gtt->ttm.dma_address, ttm->num_pages);
691 ttm->state = tt_unbound;
692 return 0;
693 }
694
695 adev = amdgpu_get_adev(ttm->bdev);
696
697#ifdef CONFIG_SWIOTLB
698 if (swiotlb_nr_tbl()) {
699 return ttm_dma_populate(&gtt->ttm, adev->dev);
700 }
701#endif
702
703 r = ttm_pool_populate(ttm);
704 if (r) {
705 return r;
706 }
707
708 for (i = 0; i < ttm->num_pages; i++) {
709 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
710 0, PAGE_SIZE,
711 PCI_DMA_BIDIRECTIONAL);
712 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
713 while (--i) {
714 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
715 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
716 gtt->ttm.dma_address[i] = 0;
717 }
718 ttm_pool_unpopulate(ttm);
719 return -EFAULT;
720 }
721 }
722 return 0;
723}
724
725static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
726{
727 struct amdgpu_device *adev;
728 struct amdgpu_ttm_tt *gtt = (void *)ttm;
729 unsigned i;
730 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
731
732 if (gtt && gtt->userptr) {
733 kfree(ttm->sg);
734 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
735 return;
736 }
737
738 if (slave)
739 return;
740
741 adev = amdgpu_get_adev(ttm->bdev);
742
743#ifdef CONFIG_SWIOTLB
744 if (swiotlb_nr_tbl()) {
745 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
746 return;
747 }
748#endif
749
750 for (i = 0; i < ttm->num_pages; i++) {
751 if (gtt->ttm.dma_address[i]) {
752 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
753 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
754 }
755 }
756
757 ttm_pool_unpopulate(ttm);
758}
759
760int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
761 uint32_t flags)
762{
763 struct amdgpu_ttm_tt *gtt = (void *)ttm;
764
765 if (gtt == NULL)
766 return -EINVAL;
767
768 gtt->userptr = addr;
769 gtt->usermm = current->mm;
770 gtt->userflags = flags;
771 return 0;
772}
773
774bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm)
775{
776 struct amdgpu_ttm_tt *gtt = (void *)ttm;
777
778 if (gtt == NULL)
779 return false;
780
781 return !!gtt->userptr;
782}
783
784bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
785{
786 struct amdgpu_ttm_tt *gtt = (void *)ttm;
787
788 if (gtt == NULL)
789 return false;
790
791 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
792}
793
794uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
795 struct ttm_mem_reg *mem)
796{
797 uint32_t flags = 0;
798
799 if (mem && mem->mem_type != TTM_PL_SYSTEM)
800 flags |= AMDGPU_PTE_VALID;
801
802 if (mem && mem->mem_type == TTM_PL_TT)
803 flags |= AMDGPU_PTE_SYSTEM;
804
805 if (!ttm || ttm->caching_state == tt_cached)
806 flags |= AMDGPU_PTE_SNOOPED;
807
808 if (adev->asic_type >= CHIP_TOPAZ)
809 flags |= AMDGPU_PTE_EXECUTABLE;
810
811 flags |= AMDGPU_PTE_READABLE;
812
813 if (!amdgpu_ttm_tt_is_readonly(ttm))
814 flags |= AMDGPU_PTE_WRITEABLE;
815
816 return flags;
817}
818
819static struct ttm_bo_driver amdgpu_bo_driver = {
820 .ttm_tt_create = &amdgpu_ttm_tt_create,
821 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
822 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
823 .invalidate_caches = &amdgpu_invalidate_caches,
824 .init_mem_type = &amdgpu_init_mem_type,
825 .evict_flags = &amdgpu_evict_flags,
826 .move = &amdgpu_bo_move,
827 .verify_access = &amdgpu_verify_access,
828 .move_notify = &amdgpu_bo_move_notify,
829 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
830 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
831 .io_mem_free = &amdgpu_ttm_io_mem_free,
832};
833
834int amdgpu_ttm_init(struct amdgpu_device *adev)
835{
836 int r;
837
838 r = amdgpu_ttm_global_init(adev);
839 if (r) {
840 return r;
841 }
842 /* No others user of address space so set it to 0 */
843 r = ttm_bo_device_init(&adev->mman.bdev,
844 adev->mman.bo_global_ref.ref.object,
845 &amdgpu_bo_driver,
846 adev->ddev->anon_inode->i_mapping,
847 DRM_FILE_PAGE_OFFSET,
848 adev->need_dma32);
849 if (r) {
850 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
851 return r;
852 }
853 adev->mman.initialized = true;
854 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
855 adev->mc.real_vram_size >> PAGE_SHIFT);
856 if (r) {
857 DRM_ERROR("Failed initializing VRAM heap.\n");
858 return r;
859 }
860 /* Change the size here instead of the init above so only lpfn is affected */
861 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
862
863 r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
864 AMDGPU_GEM_DOMAIN_VRAM, 0,
865 NULL, &adev->stollen_vga_memory);
866 if (r) {
867 return r;
868 }
869 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
870 if (r)
871 return r;
872 r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
873 amdgpu_bo_unreserve(adev->stollen_vga_memory);
874 if (r) {
875 amdgpu_bo_unref(&adev->stollen_vga_memory);
876 return r;
877 }
878 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
879 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
880 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
881 adev->mc.gtt_size >> PAGE_SHIFT);
882 if (r) {
883 DRM_ERROR("Failed initializing GTT heap.\n");
884 return r;
885 }
886 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
887 (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
888
889 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
890 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
891 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
892 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
893 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
894 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
895 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
896 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
897 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
898 /* GDS Memory */
899 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
900 adev->gds.mem.total_size >> PAGE_SHIFT);
901 if (r) {
902 DRM_ERROR("Failed initializing GDS heap.\n");
903 return r;
904 }
905
906 /* GWS */
907 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
908 adev->gds.gws.total_size >> PAGE_SHIFT);
909 if (r) {
910 DRM_ERROR("Failed initializing gws heap.\n");
911 return r;
912 }
913
914 /* OA */
915 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
916 adev->gds.oa.total_size >> PAGE_SHIFT);
917 if (r) {
918 DRM_ERROR("Failed initializing oa heap.\n");
919 return r;
920 }
921
922 r = amdgpu_ttm_debugfs_init(adev);
923 if (r) {
924 DRM_ERROR("Failed to init debugfs\n");
925 return r;
926 }
927 return 0;
928}
929
930void amdgpu_ttm_fini(struct amdgpu_device *adev)
931{
932 int r;
933
934 if (!adev->mman.initialized)
935 return;
936 amdgpu_ttm_debugfs_fini(adev);
937 if (adev->stollen_vga_memory) {
938 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
939 if (r == 0) {
940 amdgpu_bo_unpin(adev->stollen_vga_memory);
941 amdgpu_bo_unreserve(adev->stollen_vga_memory);
942 }
943 amdgpu_bo_unref(&adev->stollen_vga_memory);
944 }
945 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
946 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
947 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
948 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
949 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
950 ttm_bo_device_release(&adev->mman.bdev);
951 amdgpu_gart_fini(adev);
952 amdgpu_ttm_global_fini(adev);
953 adev->mman.initialized = false;
954 DRM_INFO("amdgpu: ttm finalized\n");
955}
956
957/* this should only be called at bootup or when userspace
958 * isn't running */
959void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
960{
961 struct ttm_mem_type_manager *man;
962
963 if (!adev->mman.initialized)
964 return;
965
966 man = &adev->mman.bdev.man[TTM_PL_VRAM];
967 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
968 man->size = size >> PAGE_SHIFT;
969}
970
971static struct vm_operations_struct amdgpu_ttm_vm_ops;
972static const struct vm_operations_struct *ttm_vm_ops = NULL;
973
974static int amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
975{
976 struct ttm_buffer_object *bo;
977 struct amdgpu_device *adev;
978 int r;
979
980 bo = (struct ttm_buffer_object *)vma->vm_private_data;
981 if (bo == NULL) {
982 return VM_FAULT_NOPAGE;
983 }
984 adev = amdgpu_get_adev(bo->bdev);
985 down_read(&adev->pm.mclk_lock);
986 r = ttm_vm_ops->fault(vma, vmf);
987 up_read(&adev->pm.mclk_lock);
988 return r;
989}
990
991int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
992{
993 struct drm_file *file_priv;
994 struct amdgpu_device *adev;
995 int r;
996
997 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
998 return -EINVAL;
999 }
1000
1001 file_priv = filp->private_data;
1002 adev = file_priv->minor->dev->dev_private;
1003 if (adev == NULL) {
1004 return -EINVAL;
1005 }
1006 r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1007 if (unlikely(r != 0)) {
1008 return r;
1009 }
1010 if (unlikely(ttm_vm_ops == NULL)) {
1011 ttm_vm_ops = vma->vm_ops;
1012 amdgpu_ttm_vm_ops = *ttm_vm_ops;
1013 amdgpu_ttm_vm_ops.fault = &amdgpu_ttm_fault;
1014 }
1015 vma->vm_ops = &amdgpu_ttm_vm_ops;
1016 return 0;
1017}
1018
1019int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1020 uint64_t src_offset,
1021 uint64_t dst_offset,
1022 uint32_t byte_count,
1023 struct reservation_object *resv,
1024 struct amdgpu_fence **fence)
1025{
1026 struct amdgpu_device *adev = ring->adev;
1027 struct amdgpu_sync sync;
1028 uint32_t max_bytes;
1029 unsigned num_loops, num_dw;
1030 unsigned i;
1031 int r;
1032
1033 /* sync other rings */
1034 amdgpu_sync_create(&sync);
1035 if (resv) {
1036 r = amdgpu_sync_resv(adev, &sync, resv, false);
1037 if (r) {
1038 DRM_ERROR("sync failed (%d).\n", r);
1039 amdgpu_sync_free(adev, &sync, NULL);
1040 return r;
1041 }
1042 }
1043
1044 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1045 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1046 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1047
1048 /* for fence and sync */
1049 num_dw += 64 + AMDGPU_NUM_SYNCS * 8;
1050
1051 r = amdgpu_ring_lock(ring, num_dw);
1052 if (r) {
1053 DRM_ERROR("ring lock failed (%d).\n", r);
1054 amdgpu_sync_free(adev, &sync, NULL);
1055 return r;
1056 }
1057
1058 amdgpu_sync_rings(&sync, ring);
1059
1060 for (i = 0; i < num_loops; i++) {
1061 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1062
1063 amdgpu_emit_copy_buffer(adev, ring, src_offset, dst_offset,
1064 cur_size_in_bytes);
1065
1066 src_offset += cur_size_in_bytes;
1067 dst_offset += cur_size_in_bytes;
1068 byte_count -= cur_size_in_bytes;
1069 }
1070
1071 r = amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_MOVE, fence);
1072 if (r) {
1073 amdgpu_ring_unlock_undo(ring);
1074 amdgpu_sync_free(adev, &sync, NULL);
1075 return r;
1076 }
1077
1078 amdgpu_ring_unlock_commit(ring);
1079 amdgpu_sync_free(adev, &sync, *fence);
1080
1081 return 0;
1082}
1083
1084#if defined(CONFIG_DEBUG_FS)
1085
1086static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1087{
1088 struct drm_info_node *node = (struct drm_info_node *)m->private;
1089 unsigned ttm_pl = *(int *)node->info_ent->data;
1090 struct drm_device *dev = node->minor->dev;
1091 struct amdgpu_device *adev = dev->dev_private;
1092 struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1093 int ret;
1094 struct ttm_bo_global *glob = adev->mman.bdev.glob;
1095
1096 spin_lock(&glob->lru_lock);
1097 ret = drm_mm_dump_table(m, mm);
1098 spin_unlock(&glob->lru_lock);
1099 return ret;
1100}
1101
1102static int ttm_pl_vram = TTM_PL_VRAM;
1103static int ttm_pl_tt = TTM_PL_TT;
1104
1105static struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1106 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1107 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1108 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1109#ifdef CONFIG_SWIOTLB
1110 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1111#endif
1112};
1113
1114static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1115 size_t size, loff_t *pos)
1116{
1117 struct amdgpu_device *adev = f->f_inode->i_private;
1118 ssize_t result = 0;
1119 int r;
1120
1121 if (size & 0x3 || *pos & 0x3)
1122 return -EINVAL;
1123
1124 while (size) {
1125 unsigned long flags;
1126 uint32_t value;
1127
1128 if (*pos >= adev->mc.mc_vram_size)
1129 return result;
1130
1131 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1132 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1133 WREG32(mmMM_INDEX_HI, *pos >> 31);
1134 value = RREG32(mmMM_DATA);
1135 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1136
1137 r = put_user(value, (uint32_t *)buf);
1138 if (r)
1139 return r;
1140
1141 result += 4;
1142 buf += 4;
1143 *pos += 4;
1144 size -= 4;
1145 }
1146
1147 return result;
1148}
1149
1150static const struct file_operations amdgpu_ttm_vram_fops = {
1151 .owner = THIS_MODULE,
1152 .read = amdgpu_ttm_vram_read,
1153 .llseek = default_llseek
1154};
1155
1156static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1157 size_t size, loff_t *pos)
1158{
1159 struct amdgpu_device *adev = f->f_inode->i_private;
1160 ssize_t result = 0;
1161 int r;
1162
1163 while (size) {
1164 loff_t p = *pos / PAGE_SIZE;
1165 unsigned off = *pos & ~PAGE_MASK;
1166 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1167 struct page *page;
1168 void *ptr;
1169
1170 if (p >= adev->gart.num_cpu_pages)
1171 return result;
1172
1173 page = adev->gart.pages[p];
1174 if (page) {
1175 ptr = kmap(page);
1176 ptr += off;
1177
1178 r = copy_to_user(buf, ptr, cur_size);
1179 kunmap(adev->gart.pages[p]);
1180 } else
1181 r = clear_user(buf, cur_size);
1182
1183 if (r)
1184 return -EFAULT;
1185
1186 result += cur_size;
1187 buf += cur_size;
1188 *pos += cur_size;
1189 size -= cur_size;
1190 }
1191
1192 return result;
1193}
1194
1195static const struct file_operations amdgpu_ttm_gtt_fops = {
1196 .owner = THIS_MODULE,
1197 .read = amdgpu_ttm_gtt_read,
1198 .llseek = default_llseek
1199};
1200
1201#endif
1202
1203static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1204{
1205#if defined(CONFIG_DEBUG_FS)
1206 unsigned count;
1207
1208 struct drm_minor *minor = adev->ddev->primary;
1209 struct dentry *ent, *root = minor->debugfs_root;
1210
1211 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1212 adev, &amdgpu_ttm_vram_fops);
1213 if (IS_ERR(ent))
1214 return PTR_ERR(ent);
1215 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1216 adev->mman.vram = ent;
1217
1218 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1219 adev, &amdgpu_ttm_gtt_fops);
1220 if (IS_ERR(ent))
1221 return PTR_ERR(ent);
1222 i_size_write(ent->d_inode, adev->mc.gtt_size);
1223 adev->mman.gtt = ent;
1224
1225 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1226
1227#ifdef CONFIG_SWIOTLB
1228 if (!swiotlb_nr_tbl())
1229 --count;
1230#endif
1231
1232 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1233#else
1234
1235 return 0;
1236#endif
1237}
1238
1239static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1240{
1241#if defined(CONFIG_DEBUG_FS)
1242
1243 debugfs_remove(adev->mman.vram);
1244 adev->mman.vram = NULL;
1245
1246 debugfs_remove(adev->mman.gtt);
1247 adev->mman.gtt = NULL;
1248#endif
1249}
Linux kernel - Deliverables
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