Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * amdgpu_vm_num_pde - return the number of page directory entries | |
55 | * | |
56 | * @adev: amdgpu_device pointer | |
57 | * | |
58 | * Calculate the number of page directory entries (cayman+). | |
59 | */ | |
60 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
61 | { | |
62 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
63 | } | |
64 | ||
65 | /** | |
66 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
67 | * | |
68 | * @adev: amdgpu_device pointer | |
69 | * | |
70 | * Calculate the size of the page directory in bytes (cayman+). | |
71 | */ | |
72 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
73 | { | |
74 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
75 | } | |
76 | ||
77 | /** | |
56467ebf | 78 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
79 | * |
80 | * @vm: vm providing the BOs | |
3c0eea6c | 81 | * @validated: head of validation list |
56467ebf CK |
82 | * @entry: entry to add |
83 | * | |
84 | * Add the page directory to the list of BOs to | |
85 | * validate for command submission. | |
86 | */ | |
87 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, | |
88 | struct list_head *validated, | |
89 | struct amdgpu_bo_list_entry *entry) | |
90 | { | |
91 | entry->robj = vm->page_directory; | |
92 | entry->prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
93 | entry->allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
94 | entry->priority = 0; | |
95 | entry->tv.bo = &vm->page_directory->tbo; | |
96 | entry->tv.shared = true; | |
97 | list_add(&entry->tv.head, validated); | |
98 | } | |
99 | ||
100 | /** | |
101 | * amdgpu_vm_get_bos - add the vm BOs to a validation list | |
102 | * | |
103 | * @vm: vm providing the BOs | |
3c0eea6c | 104 | * @duplicates: head of duplicates list |
d38ceaf9 AD |
105 | * |
106 | * Add the page directory to the list of BOs to | |
107 | * validate for command submission (cayman+). | |
108 | */ | |
56467ebf CK |
109 | struct amdgpu_bo_list_entry *amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, |
110 | struct list_head *duplicates) | |
d38ceaf9 AD |
111 | { |
112 | struct amdgpu_bo_list_entry *list; | |
113 | unsigned i, idx; | |
114 | ||
56467ebf | 115 | list = drm_malloc_ab(vm->max_pde_used + 1, |
d38ceaf9 | 116 | sizeof(struct amdgpu_bo_list_entry)); |
56467ebf | 117 | if (!list) |
d38ceaf9 AD |
118 | return NULL; |
119 | ||
120 | /* add the vm page table to the list */ | |
56467ebf | 121 | for (i = 0, idx = 0; i <= vm->max_pde_used; i++) { |
d38ceaf9 AD |
122 | if (!vm->page_tables[i].bo) |
123 | continue; | |
124 | ||
125 | list[idx].robj = vm->page_tables[i].bo; | |
126 | list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
127 | list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
128 | list[idx].priority = 0; | |
129 | list[idx].tv.bo = &list[idx].robj->tbo; | |
130 | list[idx].tv.shared = true; | |
3c0eea6c | 131 | list_add(&list[idx++].tv.head, duplicates); |
d38ceaf9 AD |
132 | } |
133 | ||
134 | return list; | |
135 | } | |
136 | ||
137 | /** | |
138 | * amdgpu_vm_grab_id - allocate the next free VMID | |
139 | * | |
d38ceaf9 | 140 | * @vm: vm to allocate id for |
7f8a5290 CK |
141 | * @ring: ring we want to submit job to |
142 | * @sync: sync object where we add dependencies | |
d38ceaf9 | 143 | * |
7f8a5290 | 144 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 145 | * |
7f8a5290 | 146 | * Global mutex must be locked! |
d38ceaf9 | 147 | */ |
7f8a5290 CK |
148 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
149 | struct amdgpu_sync *sync) | |
d38ceaf9 | 150 | { |
d5283298 | 151 | struct fence *best[AMDGPU_MAX_RINGS] = {}; |
d38ceaf9 AD |
152 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; |
153 | struct amdgpu_device *adev = ring->adev; | |
154 | ||
155 | unsigned choices[2] = {}; | |
156 | unsigned i; | |
157 | ||
158 | /* check if the id is still valid */ | |
1c16c0a7 CK |
159 | if (vm_id->id) { |
160 | unsigned id = vm_id->id; | |
161 | long owner; | |
162 | ||
163 | owner = atomic_long_read(&adev->vm_manager.ids[id].owner); | |
164 | if (owner == (long)vm) { | |
165 | trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); | |
166 | return 0; | |
167 | } | |
39ff8449 | 168 | } |
d38ceaf9 AD |
169 | |
170 | /* we definately need to flush */ | |
171 | vm_id->pd_gpu_addr = ~0ll; | |
172 | ||
173 | /* skip over VMID 0, since it is the system VM */ | |
174 | for (i = 1; i < adev->vm_manager.nvm; ++i) { | |
1c16c0a7 | 175 | struct fence *fence = adev->vm_manager.ids[i].active; |
d5283298 | 176 | struct amdgpu_ring *fring; |
d38ceaf9 AD |
177 | |
178 | if (fence == NULL) { | |
179 | /* found a free one */ | |
180 | vm_id->id = i; | |
181 | trace_amdgpu_vm_grab_id(i, ring->idx); | |
7f8a5290 | 182 | return 0; |
d38ceaf9 AD |
183 | } |
184 | ||
d5283298 CK |
185 | fring = amdgpu_ring_from_fence(fence); |
186 | if (best[fring->idx] == NULL || | |
187 | fence_is_later(best[fring->idx], fence)) { | |
188 | best[fring->idx] = fence; | |
189 | choices[fring == ring ? 0 : 1] = i; | |
d38ceaf9 AD |
190 | } |
191 | } | |
192 | ||
193 | for (i = 0; i < 2; ++i) { | |
194 | if (choices[i]) { | |
d5283298 | 195 | struct fence *fence; |
7f8a5290 | 196 | |
1c16c0a7 | 197 | fence = adev->vm_manager.ids[choices[i]].active; |
d38ceaf9 | 198 | vm_id->id = choices[i]; |
7f8a5290 | 199 | |
d38ceaf9 | 200 | trace_amdgpu_vm_grab_id(choices[i], ring->idx); |
d5283298 | 201 | return amdgpu_sync_fence(ring->adev, sync, fence); |
d38ceaf9 AD |
202 | } |
203 | } | |
204 | ||
205 | /* should never happen */ | |
206 | BUG(); | |
7f8a5290 | 207 | return -EINVAL; |
d38ceaf9 AD |
208 | } |
209 | ||
210 | /** | |
211 | * amdgpu_vm_flush - hardware flush the vm | |
212 | * | |
213 | * @ring: ring to use for flush | |
214 | * @vm: vm we want to flush | |
215 | * @updates: last vm update that we waited for | |
216 | * | |
217 | * Flush the vm (cayman+). | |
218 | * | |
219 | * Global and local mutex must be locked! | |
220 | */ | |
221 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
222 | struct amdgpu_vm *vm, | |
3c62338c | 223 | struct fence *updates) |
d38ceaf9 AD |
224 | { |
225 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
226 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; | |
3c62338c | 227 | struct fence *flushed_updates = vm_id->flushed_updates; |
b56c2285 | 228 | bool is_later; |
3c62338c | 229 | |
b56c2285 CK |
230 | if (!flushed_updates) |
231 | is_later = true; | |
232 | else if (!updates) | |
233 | is_later = false; | |
234 | else | |
235 | is_later = fence_is_later(updates, flushed_updates); | |
d38ceaf9 | 236 | |
b56c2285 | 237 | if (pd_addr != vm_id->pd_gpu_addr || is_later) { |
d38ceaf9 | 238 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); |
b56c2285 | 239 | if (is_later) { |
3c62338c CZ |
240 | vm_id->flushed_updates = fence_get(updates); |
241 | fence_put(flushed_updates); | |
242 | } | |
d38ceaf9 AD |
243 | vm_id->pd_gpu_addr = pd_addr; |
244 | amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); | |
245 | } | |
246 | } | |
247 | ||
248 | /** | |
249 | * amdgpu_vm_fence - remember fence for vm | |
250 | * | |
251 | * @adev: amdgpu_device pointer | |
252 | * @vm: vm we want to fence | |
253 | * @fence: fence to remember | |
254 | * | |
255 | * Fence the vm (cayman+). | |
256 | * Set the fence used to protect page table and id. | |
257 | * | |
258 | * Global and local mutex must be locked! | |
259 | */ | |
260 | void amdgpu_vm_fence(struct amdgpu_device *adev, | |
261 | struct amdgpu_vm *vm, | |
16ae42fe | 262 | struct fence *fence) |
d38ceaf9 | 263 | { |
16ae42fe CK |
264 | struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence); |
265 | unsigned vm_id = vm->ids[ring->idx].id; | |
d38ceaf9 | 266 | |
1c16c0a7 CK |
267 | fence_put(adev->vm_manager.ids[vm_id].active); |
268 | adev->vm_manager.ids[vm_id].active = fence_get(fence); | |
269 | atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm); | |
d38ceaf9 AD |
270 | } |
271 | ||
272 | /** | |
273 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
274 | * | |
275 | * @vm: requested vm | |
276 | * @bo: requested buffer object | |
277 | * | |
278 | * Find @bo inside the requested vm (cayman+). | |
279 | * Search inside the @bos vm list for the requested vm | |
280 | * Returns the found bo_va or NULL if none is found | |
281 | * | |
282 | * Object has to be reserved! | |
283 | */ | |
284 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
285 | struct amdgpu_bo *bo) | |
286 | { | |
287 | struct amdgpu_bo_va *bo_va; | |
288 | ||
289 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
290 | if (bo_va->vm == vm) { | |
291 | return bo_va; | |
292 | } | |
293 | } | |
294 | return NULL; | |
295 | } | |
296 | ||
297 | /** | |
298 | * amdgpu_vm_update_pages - helper to call the right asic function | |
299 | * | |
300 | * @adev: amdgpu_device pointer | |
301 | * @ib: indirect buffer to fill with commands | |
302 | * @pe: addr of the page entry | |
303 | * @addr: dst addr to write into pe | |
304 | * @count: number of page entries to update | |
305 | * @incr: increase next addr by incr bytes | |
306 | * @flags: hw access flags | |
307 | * @gtt_flags: GTT hw access flags | |
308 | * | |
309 | * Traces the parameters and calls the right asic functions | |
310 | * to setup the page table using the DMA. | |
311 | */ | |
312 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
313 | struct amdgpu_ib *ib, | |
314 | uint64_t pe, uint64_t addr, | |
315 | unsigned count, uint32_t incr, | |
316 | uint32_t flags, uint32_t gtt_flags) | |
317 | { | |
318 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
319 | ||
320 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
321 | uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; | |
322 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); | |
323 | ||
324 | } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { | |
325 | amdgpu_vm_write_pte(adev, ib, pe, addr, | |
326 | count, incr, flags); | |
327 | ||
328 | } else { | |
329 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
330 | count, incr, flags); | |
331 | } | |
332 | } | |
333 | ||
4c7eb91c | 334 | int amdgpu_vm_free_job(struct amdgpu_job *job) |
d5fc5e82 CZ |
335 | { |
336 | int i; | |
4c7eb91c JZ |
337 | for (i = 0; i < job->num_ibs; i++) |
338 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
339 | kfree(job->ibs); | |
d5fc5e82 CZ |
340 | return 0; |
341 | } | |
342 | ||
d38ceaf9 AD |
343 | /** |
344 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
345 | * | |
346 | * @adev: amdgpu_device pointer | |
347 | * @bo: bo to clear | |
ef9f0a83 CZ |
348 | * |
349 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
350 | */ |
351 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
352 | struct amdgpu_bo *bo) | |
353 | { | |
354 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
4af9f07c | 355 | struct fence *fence = NULL; |
d5fc5e82 | 356 | struct amdgpu_ib *ib; |
d38ceaf9 AD |
357 | unsigned entries; |
358 | uint64_t addr; | |
359 | int r; | |
360 | ||
ca952613 | 361 | r = reservation_object_reserve_shared(bo->tbo.resv); |
362 | if (r) | |
363 | return r; | |
364 | ||
d38ceaf9 AD |
365 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
366 | if (r) | |
ef9f0a83 | 367 | goto error; |
d38ceaf9 AD |
368 | |
369 | addr = amdgpu_bo_gpu_offset(bo); | |
370 | entries = amdgpu_bo_size(bo) / 8; | |
371 | ||
d5fc5e82 CZ |
372 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
373 | if (!ib) | |
ef9f0a83 | 374 | goto error; |
d38ceaf9 | 375 | |
d5fc5e82 | 376 | r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); |
d38ceaf9 AD |
377 | if (r) |
378 | goto error_free; | |
379 | ||
d5fc5e82 CZ |
380 | ib->length_dw = 0; |
381 | ||
382 | amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0); | |
383 | amdgpu_vm_pad_ib(adev, ib); | |
384 | WARN_ON(ib->length_dw > 64); | |
4af9f07c CZ |
385 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
386 | &amdgpu_vm_free_job, | |
387 | AMDGPU_FENCE_OWNER_VM, | |
388 | &fence); | |
389 | if (!r) | |
390 | amdgpu_bo_fence(bo, fence, true); | |
281b4223 | 391 | fence_put(fence); |
ef9f0a83 | 392 | if (amdgpu_enable_scheduler) |
d5fc5e82 | 393 | return 0; |
ef9f0a83 | 394 | |
d38ceaf9 | 395 | error_free: |
d5fc5e82 CZ |
396 | amdgpu_ib_free(adev, ib); |
397 | kfree(ib); | |
d38ceaf9 | 398 | |
ef9f0a83 | 399 | error: |
d38ceaf9 AD |
400 | return r; |
401 | } | |
402 | ||
403 | /** | |
404 | * amdgpu_vm_map_gart - get the physical address of a gart page | |
405 | * | |
406 | * @adev: amdgpu_device pointer | |
407 | * @addr: the unmapped addr | |
408 | * | |
409 | * Look up the physical address of the page that the pte resolves | |
410 | * to (cayman+). | |
411 | * Returns the physical address of the page. | |
412 | */ | |
413 | uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) | |
414 | { | |
415 | uint64_t result; | |
416 | ||
417 | /* page table offset */ | |
418 | result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; | |
419 | ||
420 | /* in case cpu page size != gpu page size*/ | |
421 | result |= addr & (~PAGE_MASK); | |
422 | ||
423 | return result; | |
424 | } | |
425 | ||
426 | /** | |
427 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
428 | * | |
429 | * @adev: amdgpu_device pointer | |
430 | * @vm: requested vm | |
431 | * @start: start of GPU address range | |
432 | * @end: end of GPU address range | |
433 | * | |
434 | * Allocates new page tables if necessary | |
435 | * and updates the page directory (cayman+). | |
436 | * Returns 0 for success, error for failure. | |
437 | * | |
438 | * Global and local mutex must be locked! | |
439 | */ | |
440 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
441 | struct amdgpu_vm *vm) | |
442 | { | |
443 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
444 | struct amdgpu_bo *pd = vm->page_directory; | |
445 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
446 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
447 | uint64_t last_pde = ~0, last_pt = ~0; | |
448 | unsigned count = 0, pt_idx, ndw; | |
d5fc5e82 | 449 | struct amdgpu_ib *ib; |
4af9f07c | 450 | struct fence *fence = NULL; |
d5fc5e82 | 451 | |
d38ceaf9 AD |
452 | int r; |
453 | ||
454 | /* padding, etc. */ | |
455 | ndw = 64; | |
456 | ||
457 | /* assume the worst case */ | |
458 | ndw += vm->max_pde_used * 6; | |
459 | ||
460 | /* update too big for an IB */ | |
461 | if (ndw > 0xfffff) | |
462 | return -ENOMEM; | |
463 | ||
d5fc5e82 CZ |
464 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
465 | if (!ib) | |
466 | return -ENOMEM; | |
467 | ||
468 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
7a574557 SM |
469 | if (r) { |
470 | kfree(ib); | |
d38ceaf9 | 471 | return r; |
7a574557 | 472 | } |
d5fc5e82 | 473 | ib->length_dw = 0; |
d38ceaf9 AD |
474 | |
475 | /* walk over the address space and update the page directory */ | |
476 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
477 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; | |
478 | uint64_t pde, pt; | |
479 | ||
480 | if (bo == NULL) | |
481 | continue; | |
482 | ||
483 | pt = amdgpu_bo_gpu_offset(bo); | |
484 | if (vm->page_tables[pt_idx].addr == pt) | |
485 | continue; | |
486 | vm->page_tables[pt_idx].addr = pt; | |
487 | ||
488 | pde = pd_addr + pt_idx * 8; | |
489 | if (((last_pde + 8 * count) != pde) || | |
490 | ((last_pt + incr * count) != pt)) { | |
491 | ||
492 | if (count) { | |
d5fc5e82 | 493 | amdgpu_vm_update_pages(adev, ib, last_pde, |
d38ceaf9 AD |
494 | last_pt, count, incr, |
495 | AMDGPU_PTE_VALID, 0); | |
496 | } | |
497 | ||
498 | count = 1; | |
499 | last_pde = pde; | |
500 | last_pt = pt; | |
501 | } else { | |
502 | ++count; | |
503 | } | |
504 | } | |
505 | ||
506 | if (count) | |
d5fc5e82 | 507 | amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, |
d38ceaf9 AD |
508 | incr, AMDGPU_PTE_VALID, 0); |
509 | ||
d5fc5e82 CZ |
510 | if (ib->length_dw != 0) { |
511 | amdgpu_vm_pad_ib(adev, ib); | |
512 | amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); | |
513 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
514 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
515 | &amdgpu_vm_free_job, | |
516 | AMDGPU_FENCE_OWNER_VM, | |
517 | &fence); | |
518 | if (r) | |
519 | goto error_free; | |
05906dec | 520 | |
4af9f07c | 521 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
522 | fence_put(vm->page_directory_fence); |
523 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 524 | fence_put(fence); |
d38ceaf9 | 525 | } |
d5fc5e82 CZ |
526 | |
527 | if (!amdgpu_enable_scheduler || ib->length_dw == 0) { | |
528 | amdgpu_ib_free(adev, ib); | |
529 | kfree(ib); | |
530 | } | |
d38ceaf9 AD |
531 | |
532 | return 0; | |
d5fc5e82 CZ |
533 | |
534 | error_free: | |
d5fc5e82 CZ |
535 | amdgpu_ib_free(adev, ib); |
536 | kfree(ib); | |
4af9f07c | 537 | return r; |
d38ceaf9 AD |
538 | } |
539 | ||
540 | /** | |
541 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
542 | * | |
543 | * @adev: amdgpu_device pointer | |
544 | * @ib: IB for the update | |
545 | * @pe_start: first PTE to handle | |
546 | * @pe_end: last PTE to handle | |
547 | * @addr: addr those PTEs should point to | |
548 | * @flags: hw mapping flags | |
549 | * @gtt_flags: GTT hw mapping flags | |
550 | * | |
551 | * Global and local mutex must be locked! | |
552 | */ | |
553 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
554 | struct amdgpu_ib *ib, | |
555 | uint64_t pe_start, uint64_t pe_end, | |
556 | uint64_t addr, uint32_t flags, | |
557 | uint32_t gtt_flags) | |
558 | { | |
559 | /** | |
560 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
561 | * field in the PTE. When this field is set to a non-zero value, page | |
562 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
563 | * flags are considered valid for all PTEs within the fragment range | |
564 | * and corresponding mappings are assumed to be physically contiguous. | |
565 | * | |
566 | * The L1 TLB can store a single PTE for the whole fragment, | |
567 | * significantly increasing the space available for translation | |
568 | * caching. This leads to large improvements in throughput when the | |
569 | * TLB is under pressure. | |
570 | * | |
571 | * The L2 TLB distributes small and large fragments into two | |
572 | * asymmetric partitions. The large fragment cache is significantly | |
573 | * larger. Thus, we try to use large fragments wherever possible. | |
574 | * Userspace can support this by aligning virtual base address and | |
575 | * allocation size to the fragment size. | |
576 | */ | |
577 | ||
578 | /* SI and newer are optimized for 64KB */ | |
579 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
580 | uint64_t frag_align = 0x80; | |
581 | ||
582 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
583 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
584 | ||
585 | unsigned count; | |
586 | ||
587 | /* system pages are non continuously */ | |
588 | if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) || | |
589 | (frag_start >= frag_end)) { | |
590 | ||
591 | count = (pe_end - pe_start) / 8; | |
592 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
593 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
594 | return; | |
595 | } | |
596 | ||
597 | /* handle the 4K area at the beginning */ | |
598 | if (pe_start != frag_start) { | |
599 | count = (frag_start - pe_start) / 8; | |
600 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
601 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
602 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
603 | } | |
604 | ||
605 | /* handle the area in the middle */ | |
606 | count = (frag_end - frag_start) / 8; | |
607 | amdgpu_vm_update_pages(adev, ib, frag_start, addr, count, | |
608 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags, | |
609 | gtt_flags); | |
610 | ||
611 | /* handle the 4K area at the end */ | |
612 | if (frag_end != pe_end) { | |
613 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
614 | count = (pe_end - frag_end) / 8; | |
615 | amdgpu_vm_update_pages(adev, ib, frag_end, addr, count, | |
616 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
617 | } | |
618 | } | |
619 | ||
620 | /** | |
621 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
622 | * | |
623 | * @adev: amdgpu_device pointer | |
624 | * @vm: requested vm | |
625 | * @start: start of GPU address range | |
626 | * @end: end of GPU address range | |
627 | * @dst: destination address to map to | |
628 | * @flags: mapping flags | |
629 | * | |
630 | * Update the page tables in the range @start - @end (cayman+). | |
631 | * | |
632 | * Global and local mutex must be locked! | |
633 | */ | |
634 | static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | |
635 | struct amdgpu_vm *vm, | |
636 | struct amdgpu_ib *ib, | |
637 | uint64_t start, uint64_t end, | |
638 | uint64_t dst, uint32_t flags, | |
639 | uint32_t gtt_flags) | |
640 | { | |
641 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; | |
642 | uint64_t last_pte = ~0, last_dst = ~0; | |
a60c4232 | 643 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
644 | unsigned count = 0; |
645 | uint64_t addr; | |
646 | ||
a60c4232 CK |
647 | /* sync to everything on unmapping */ |
648 | if (!(flags & AMDGPU_PTE_VALID)) | |
649 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
650 | ||
d38ceaf9 AD |
651 | /* walk over the address space and update the page tables */ |
652 | for (addr = start; addr < end; ) { | |
653 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
654 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo; | |
655 | unsigned nptes; | |
656 | uint64_t pte; | |
657 | int r; | |
658 | ||
a60c4232 | 659 | amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner); |
d38ceaf9 AD |
660 | r = reservation_object_reserve_shared(pt->tbo.resv); |
661 | if (r) | |
662 | return r; | |
663 | ||
664 | if ((addr & ~mask) == (end & ~mask)) | |
665 | nptes = end - addr; | |
666 | else | |
667 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
668 | ||
669 | pte = amdgpu_bo_gpu_offset(pt); | |
670 | pte += (addr & mask) * 8; | |
671 | ||
672 | if ((last_pte + 8 * count) != pte) { | |
673 | ||
674 | if (count) { | |
675 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
676 | last_pte + 8 * count, | |
677 | last_dst, flags, | |
678 | gtt_flags); | |
679 | } | |
680 | ||
681 | count = nptes; | |
682 | last_pte = pte; | |
683 | last_dst = dst; | |
684 | } else { | |
685 | count += nptes; | |
686 | } | |
687 | ||
688 | addr += nptes; | |
689 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
690 | } | |
691 | ||
692 | if (count) { | |
693 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
694 | last_pte + 8 * count, | |
695 | last_dst, flags, gtt_flags); | |
696 | } | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
d38ceaf9 AD |
701 | /** |
702 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
703 | * | |
704 | * @adev: amdgpu_device pointer | |
705 | * @vm: requested vm | |
706 | * @mapping: mapped range and flags to use for the update | |
707 | * @addr: addr to set the area to | |
708 | * @gtt_flags: flags as they are used for GTT | |
709 | * @fence: optional resulting fence | |
710 | * | |
711 | * Fill in the page table entries for @mapping. | |
712 | * Returns 0 for success, -EINVAL for failure. | |
713 | * | |
714 | * Object have to be reserved and mutex must be locked! | |
715 | */ | |
716 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
717 | struct amdgpu_vm *vm, | |
718 | struct amdgpu_bo_va_mapping *mapping, | |
719 | uint64_t addr, uint32_t gtt_flags, | |
bb1e38a4 | 720 | struct fence **fence) |
d38ceaf9 AD |
721 | { |
722 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
723 | unsigned nptes, ncmds, ndw; | |
724 | uint32_t flags = gtt_flags; | |
d5fc5e82 | 725 | struct amdgpu_ib *ib; |
4af9f07c | 726 | struct fence *f = NULL; |
d38ceaf9 AD |
727 | int r; |
728 | ||
729 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
730 | * but in case of something, we filter the flags in first place | |
731 | */ | |
732 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
733 | flags &= ~AMDGPU_PTE_READABLE; | |
734 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
735 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
736 | ||
737 | trace_amdgpu_vm_bo_update(mapping); | |
738 | ||
739 | nptes = mapping->it.last - mapping->it.start + 1; | |
740 | ||
741 | /* | |
742 | * reserve space for one command every (1 << BLOCK_SIZE) | |
743 | * entries or 2k dwords (whatever is smaller) | |
744 | */ | |
745 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
746 | ||
747 | /* padding, etc. */ | |
748 | ndw = 64; | |
749 | ||
750 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
751 | /* only copy commands needed */ | |
752 | ndw += ncmds * 7; | |
753 | ||
754 | } else if (flags & AMDGPU_PTE_SYSTEM) { | |
755 | /* header for write data commands */ | |
756 | ndw += ncmds * 4; | |
757 | ||
758 | /* body of write data command */ | |
759 | ndw += nptes * 2; | |
760 | ||
761 | } else { | |
762 | /* set page commands needed */ | |
763 | ndw += ncmds * 10; | |
764 | ||
765 | /* two extra commands for begin/end of fragment */ | |
766 | ndw += 2 * 10; | |
767 | } | |
768 | ||
769 | /* update too big for an IB */ | |
770 | if (ndw > 0xfffff) | |
771 | return -ENOMEM; | |
772 | ||
d5fc5e82 CZ |
773 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
774 | if (!ib) | |
775 | return -ENOMEM; | |
776 | ||
777 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
778 | if (r) { | |
779 | kfree(ib); | |
d38ceaf9 | 780 | return r; |
d5fc5e82 CZ |
781 | } |
782 | ||
783 | ib->length_dw = 0; | |
d38ceaf9 | 784 | |
d5fc5e82 | 785 | r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start, |
d38ceaf9 AD |
786 | mapping->it.last + 1, addr + mapping->offset, |
787 | flags, gtt_flags); | |
788 | ||
789 | if (r) { | |
d5fc5e82 CZ |
790 | amdgpu_ib_free(adev, ib); |
791 | kfree(ib); | |
d38ceaf9 AD |
792 | return r; |
793 | } | |
794 | ||
d5fc5e82 CZ |
795 | amdgpu_vm_pad_ib(adev, ib); |
796 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
797 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
798 | &amdgpu_vm_free_job, | |
799 | AMDGPU_FENCE_OWNER_VM, | |
800 | &f); | |
801 | if (r) | |
802 | goto error_free; | |
d38ceaf9 | 803 | |
bf60efd3 | 804 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
805 | if (fence) { |
806 | fence_put(*fence); | |
807 | *fence = fence_get(f); | |
808 | } | |
281b4223 | 809 | fence_put(f); |
4af9f07c | 810 | if (!amdgpu_enable_scheduler) { |
d5fc5e82 CZ |
811 | amdgpu_ib_free(adev, ib); |
812 | kfree(ib); | |
813 | } | |
d38ceaf9 | 814 | return 0; |
d5fc5e82 CZ |
815 | |
816 | error_free: | |
d5fc5e82 CZ |
817 | amdgpu_ib_free(adev, ib); |
818 | kfree(ib); | |
4af9f07c | 819 | return r; |
d38ceaf9 AD |
820 | } |
821 | ||
822 | /** | |
823 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
824 | * | |
825 | * @adev: amdgpu_device pointer | |
826 | * @bo_va: requested BO and VM object | |
827 | * @mem: ttm mem | |
828 | * | |
829 | * Fill in the page table entries for @bo_va. | |
830 | * Returns 0 for success, -EINVAL for failure. | |
831 | * | |
832 | * Object have to be reserved and mutex must be locked! | |
833 | */ | |
834 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
835 | struct amdgpu_bo_va *bo_va, | |
836 | struct ttm_mem_reg *mem) | |
837 | { | |
838 | struct amdgpu_vm *vm = bo_va->vm; | |
839 | struct amdgpu_bo_va_mapping *mapping; | |
840 | uint32_t flags; | |
841 | uint64_t addr; | |
842 | int r; | |
843 | ||
844 | if (mem) { | |
b7d698d7 | 845 | addr = (u64)mem->start << PAGE_SHIFT; |
d38ceaf9 AD |
846 | if (mem->mem_type != TTM_PL_TT) |
847 | addr += adev->vm_manager.vram_base_offset; | |
848 | } else { | |
849 | addr = 0; | |
850 | } | |
851 | ||
d38ceaf9 AD |
852 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
853 | ||
7fc11959 CK |
854 | spin_lock(&vm->status_lock); |
855 | if (!list_empty(&bo_va->vm_status)) | |
856 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
857 | spin_unlock(&vm->status_lock); | |
858 | ||
859 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
d38ceaf9 AD |
860 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr, |
861 | flags, &bo_va->last_pt_update); | |
862 | if (r) | |
863 | return r; | |
864 | } | |
865 | ||
d6c10f6b CK |
866 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
867 | list_for_each_entry(mapping, &bo_va->valids, list) | |
868 | trace_amdgpu_vm_bo_mapping(mapping); | |
869 | ||
870 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
871 | trace_amdgpu_vm_bo_mapping(mapping); | |
872 | } | |
873 | ||
d38ceaf9 | 874 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 875 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 876 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
877 | if (!mem) |
878 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
879 | spin_unlock(&vm->status_lock); |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | /** | |
885 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
886 | * | |
887 | * @adev: amdgpu_device pointer | |
888 | * @vm: requested vm | |
889 | * | |
890 | * Make sure all freed BOs are cleared in the PT. | |
891 | * Returns 0 for success. | |
892 | * | |
893 | * PTs have to be reserved and mutex must be locked! | |
894 | */ | |
895 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
896 | struct amdgpu_vm *vm) | |
897 | { | |
898 | struct amdgpu_bo_va_mapping *mapping; | |
899 | int r; | |
900 | ||
9c4153b1 | 901 | spin_lock(&vm->freed_lock); |
d38ceaf9 AD |
902 | while (!list_empty(&vm->freed)) { |
903 | mapping = list_first_entry(&vm->freed, | |
904 | struct amdgpu_bo_va_mapping, list); | |
905 | list_del(&mapping->list); | |
9c4153b1 | 906 | spin_unlock(&vm->freed_lock); |
d38ceaf9 AD |
907 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL); |
908 | kfree(mapping); | |
909 | if (r) | |
910 | return r; | |
911 | ||
9c4153b1 | 912 | spin_lock(&vm->freed_lock); |
d38ceaf9 | 913 | } |
9c4153b1 | 914 | spin_unlock(&vm->freed_lock); |
915 | ||
d38ceaf9 AD |
916 | return 0; |
917 | ||
918 | } | |
919 | ||
920 | /** | |
921 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
922 | * | |
923 | * @adev: amdgpu_device pointer | |
924 | * @vm: requested vm | |
925 | * | |
926 | * Make sure all invalidated BOs are cleared in the PT. | |
927 | * Returns 0 for success. | |
928 | * | |
929 | * PTs have to be reserved and mutex must be locked! | |
930 | */ | |
931 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 932 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 933 | { |
cfe2c978 | 934 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 935 | int r = 0; |
d38ceaf9 AD |
936 | |
937 | spin_lock(&vm->status_lock); | |
938 | while (!list_empty(&vm->invalidated)) { | |
939 | bo_va = list_first_entry(&vm->invalidated, | |
940 | struct amdgpu_bo_va, vm_status); | |
941 | spin_unlock(&vm->status_lock); | |
69b576a1 | 942 | mutex_lock(&bo_va->mutex); |
d38ceaf9 | 943 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
69b576a1 | 944 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 AD |
945 | if (r) |
946 | return r; | |
947 | ||
948 | spin_lock(&vm->status_lock); | |
949 | } | |
950 | spin_unlock(&vm->status_lock); | |
951 | ||
cfe2c978 | 952 | if (bo_va) |
bb1e38a4 | 953 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
954 | |
955 | return r; | |
d38ceaf9 AD |
956 | } |
957 | ||
958 | /** | |
959 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
960 | * | |
961 | * @adev: amdgpu_device pointer | |
962 | * @vm: requested vm | |
963 | * @bo: amdgpu buffer object | |
964 | * | |
965 | * Add @bo into the requested vm (cayman+). | |
966 | * Add @bo to the list of bos associated with the vm | |
967 | * Returns newly added bo_va or NULL for failure | |
968 | * | |
969 | * Object has to be reserved! | |
970 | */ | |
971 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
972 | struct amdgpu_vm *vm, | |
973 | struct amdgpu_bo *bo) | |
974 | { | |
975 | struct amdgpu_bo_va *bo_va; | |
976 | ||
977 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
978 | if (bo_va == NULL) { | |
979 | return NULL; | |
980 | } | |
981 | bo_va->vm = vm; | |
982 | bo_va->bo = bo; | |
d38ceaf9 AD |
983 | bo_va->ref_count = 1; |
984 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
985 | INIT_LIST_HEAD(&bo_va->valids); |
986 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 987 | INIT_LIST_HEAD(&bo_va->vm_status); |
69b576a1 | 988 | mutex_init(&bo_va->mutex); |
d38ceaf9 | 989 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
990 | |
991 | return bo_va; | |
992 | } | |
993 | ||
994 | /** | |
995 | * amdgpu_vm_bo_map - map bo inside a vm | |
996 | * | |
997 | * @adev: amdgpu_device pointer | |
998 | * @bo_va: bo_va to store the address | |
999 | * @saddr: where to map the BO | |
1000 | * @offset: requested offset in the BO | |
1001 | * @flags: attributes of pages (read/write/valid/etc.) | |
1002 | * | |
1003 | * Add a mapping of the BO at the specefied addr into the VM. | |
1004 | * Returns 0 for success, error for failure. | |
1005 | * | |
49b02b18 | 1006 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1007 | */ |
1008 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1009 | struct amdgpu_bo_va *bo_va, | |
1010 | uint64_t saddr, uint64_t offset, | |
1011 | uint64_t size, uint32_t flags) | |
1012 | { | |
1013 | struct amdgpu_bo_va_mapping *mapping; | |
1014 | struct amdgpu_vm *vm = bo_va->vm; | |
1015 | struct interval_tree_node *it; | |
1016 | unsigned last_pfn, pt_idx; | |
1017 | uint64_t eaddr; | |
1018 | int r; | |
1019 | ||
0be52de9 CK |
1020 | /* validate the parameters */ |
1021 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1022 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1023 | return -EINVAL; |
0be52de9 | 1024 | |
d38ceaf9 AD |
1025 | /* make sure object fit at this offset */ |
1026 | eaddr = saddr + size; | |
49b02b18 | 1027 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1028 | return -EINVAL; |
d38ceaf9 AD |
1029 | |
1030 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
1031 | if (last_pfn > adev->vm_manager.max_pfn) { | |
1032 | dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n", | |
1033 | last_pfn, adev->vm_manager.max_pfn); | |
d38ceaf9 AD |
1034 | return -EINVAL; |
1035 | } | |
1036 | ||
d38ceaf9 AD |
1037 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1038 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1039 | ||
c25867df | 1040 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1041 | it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1); |
c25867df | 1042 | spin_unlock(&vm->it_lock); |
d38ceaf9 AD |
1043 | if (it) { |
1044 | struct amdgpu_bo_va_mapping *tmp; | |
1045 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1046 | /* bo and tmp overlap, invalid addr */ | |
1047 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1048 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1049 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1050 | r = -EINVAL; |
f48b2659 | 1051 | goto error; |
d38ceaf9 AD |
1052 | } |
1053 | ||
1054 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1055 | if (!mapping) { | |
d38ceaf9 | 1056 | r = -ENOMEM; |
f48b2659 | 1057 | goto error; |
d38ceaf9 AD |
1058 | } |
1059 | ||
1060 | INIT_LIST_HEAD(&mapping->list); | |
1061 | mapping->it.start = saddr; | |
1062 | mapping->it.last = eaddr - 1; | |
1063 | mapping->offset = offset; | |
1064 | mapping->flags = flags; | |
1065 | ||
69b576a1 | 1066 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1067 | list_add(&mapping->list, &bo_va->invalids); |
69b576a1 | 1068 | mutex_unlock(&bo_va->mutex); |
c25867df | 1069 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1070 | interval_tree_insert(&mapping->it, &vm->va); |
c25867df | 1071 | spin_unlock(&vm->it_lock); |
93e3e438 | 1072 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1073 | |
1074 | /* Make sure the page tables are allocated */ | |
1075 | saddr >>= amdgpu_vm_block_size; | |
1076 | eaddr >>= amdgpu_vm_block_size; | |
1077 | ||
1078 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1079 | ||
1080 | if (eaddr > vm->max_pde_used) | |
1081 | vm->max_pde_used = eaddr; | |
1082 | ||
d38ceaf9 AD |
1083 | /* walk over the address space and allocate the page tables */ |
1084 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1085 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
d38ceaf9 AD |
1086 | struct amdgpu_bo *pt; |
1087 | ||
1088 | if (vm->page_tables[pt_idx].bo) | |
1089 | continue; | |
1090 | ||
d38ceaf9 AD |
1091 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1092 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1093 | AMDGPU_GEM_DOMAIN_VRAM, |
1094 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1095 | NULL, resv, &pt); |
49b02b18 | 1096 | if (r) |
d38ceaf9 | 1097 | goto error_free; |
49b02b18 | 1098 | |
d38ceaf9 AD |
1099 | r = amdgpu_vm_clear_bo(adev, pt); |
1100 | if (r) { | |
1101 | amdgpu_bo_unref(&pt); | |
1102 | goto error_free; | |
1103 | } | |
1104 | ||
d38ceaf9 AD |
1105 | vm->page_tables[pt_idx].addr = 0; |
1106 | vm->page_tables[pt_idx].bo = pt; | |
1107 | } | |
1108 | ||
d38ceaf9 AD |
1109 | return 0; |
1110 | ||
1111 | error_free: | |
d38ceaf9 | 1112 | list_del(&mapping->list); |
c25867df | 1113 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1114 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1115 | spin_unlock(&vm->it_lock); |
93e3e438 | 1116 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1117 | kfree(mapping); |
1118 | ||
f48b2659 | 1119 | error: |
d38ceaf9 AD |
1120 | return r; |
1121 | } | |
1122 | ||
1123 | /** | |
1124 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1125 | * | |
1126 | * @adev: amdgpu_device pointer | |
1127 | * @bo_va: bo_va to remove the address from | |
1128 | * @saddr: where to the BO is mapped | |
1129 | * | |
1130 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1131 | * Returns 0 for success, error for failure. | |
1132 | * | |
49b02b18 | 1133 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1134 | */ |
1135 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1136 | struct amdgpu_bo_va *bo_va, | |
1137 | uint64_t saddr) | |
1138 | { | |
1139 | struct amdgpu_bo_va_mapping *mapping; | |
1140 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1141 | bool valid = true; |
d38ceaf9 | 1142 | |
6c7fc503 | 1143 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
69b576a1 | 1144 | mutex_lock(&bo_va->mutex); |
7fc11959 | 1145 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1146 | if (mapping->it.start == saddr) |
1147 | break; | |
1148 | } | |
1149 | ||
7fc11959 CK |
1150 | if (&mapping->list == &bo_va->valids) { |
1151 | valid = false; | |
1152 | ||
1153 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1154 | if (mapping->it.start == saddr) | |
1155 | break; | |
1156 | } | |
1157 | ||
69b576a1 CZ |
1158 | if (&mapping->list == &bo_va->invalids) { |
1159 | mutex_unlock(&bo_va->mutex); | |
7fc11959 | 1160 | return -ENOENT; |
69b576a1 | 1161 | } |
d38ceaf9 | 1162 | } |
69b576a1 | 1163 | mutex_unlock(&bo_va->mutex); |
d38ceaf9 | 1164 | list_del(&mapping->list); |
c25867df | 1165 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1166 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1167 | spin_unlock(&vm->it_lock); |
93e3e438 | 1168 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1169 | |
9c4153b1 | 1170 | if (valid) { |
1171 | spin_lock(&vm->freed_lock); | |
d38ceaf9 | 1172 | list_add(&mapping->list, &vm->freed); |
9c4153b1 | 1173 | spin_unlock(&vm->freed_lock); |
1174 | } else { | |
d38ceaf9 | 1175 | kfree(mapping); |
9c4153b1 | 1176 | } |
d38ceaf9 AD |
1177 | |
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | /** | |
1182 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1183 | * | |
1184 | * @adev: amdgpu_device pointer | |
1185 | * @bo_va: requested bo_va | |
1186 | * | |
1187 | * Remove @bo_va->bo from the requested vm (cayman+). | |
1188 | * | |
1189 | * Object have to be reserved! | |
1190 | */ | |
1191 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1192 | struct amdgpu_bo_va *bo_va) | |
1193 | { | |
1194 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1195 | struct amdgpu_vm *vm = bo_va->vm; | |
1196 | ||
1197 | list_del(&bo_va->bo_list); | |
1198 | ||
d38ceaf9 AD |
1199 | spin_lock(&vm->status_lock); |
1200 | list_del(&bo_va->vm_status); | |
1201 | spin_unlock(&vm->status_lock); | |
1202 | ||
7fc11959 | 1203 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 1204 | list_del(&mapping->list); |
c25867df | 1205 | spin_lock(&vm->it_lock); |
d38ceaf9 | 1206 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1207 | spin_unlock(&vm->it_lock); |
93e3e438 | 1208 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
9c4153b1 | 1209 | spin_lock(&vm->freed_lock); |
7fc11959 | 1210 | list_add(&mapping->list, &vm->freed); |
9c4153b1 | 1211 | spin_unlock(&vm->freed_lock); |
7fc11959 CK |
1212 | } |
1213 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1214 | list_del(&mapping->list); | |
c25867df | 1215 | spin_lock(&vm->it_lock); |
7fc11959 | 1216 | interval_tree_remove(&mapping->it, &vm->va); |
c25867df | 1217 | spin_unlock(&vm->it_lock); |
7fc11959 | 1218 | kfree(mapping); |
d38ceaf9 | 1219 | } |
bb1e38a4 | 1220 | fence_put(bo_va->last_pt_update); |
69b576a1 | 1221 | mutex_destroy(&bo_va->mutex); |
d38ceaf9 | 1222 | kfree(bo_va); |
d38ceaf9 AD |
1223 | } |
1224 | ||
1225 | /** | |
1226 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1227 | * | |
1228 | * @adev: amdgpu_device pointer | |
1229 | * @vm: requested vm | |
1230 | * @bo: amdgpu buffer object | |
1231 | * | |
1232 | * Mark @bo as invalid (cayman+). | |
1233 | */ | |
1234 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1235 | struct amdgpu_bo *bo) | |
1236 | { | |
1237 | struct amdgpu_bo_va *bo_va; | |
1238 | ||
1239 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1240 | spin_lock(&bo_va->vm->status_lock); |
1241 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1242 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1243 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1244 | } |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * amdgpu_vm_init - initialize a vm instance | |
1249 | * | |
1250 | * @adev: amdgpu_device pointer | |
1251 | * @vm: requested vm | |
1252 | * | |
1253 | * Init @vm fields (cayman+). | |
1254 | */ | |
1255 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1256 | { | |
1257 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1258 | AMDGPU_VM_PTE_COUNT * 8); | |
1259 | unsigned pd_size, pd_entries, pts_size; | |
1260 | int i, r; | |
1261 | ||
1262 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1263 | vm->ids[i].id = 0; | |
1264 | vm->ids[i].flushed_updates = NULL; | |
d38ceaf9 | 1265 | } |
d38ceaf9 AD |
1266 | vm->va = RB_ROOT; |
1267 | spin_lock_init(&vm->status_lock); | |
1268 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1269 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1270 | INIT_LIST_HEAD(&vm->freed); |
c25867df | 1271 | spin_lock_init(&vm->it_lock); |
9c4153b1 | 1272 | spin_lock_init(&vm->freed_lock); |
d38ceaf9 AD |
1273 | pd_size = amdgpu_vm_directory_size(adev); |
1274 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1275 | ||
1276 | /* allocate page table array */ | |
1277 | pts_size = pd_entries * sizeof(struct amdgpu_vm_pt); | |
1278 | vm->page_tables = kzalloc(pts_size, GFP_KERNEL); | |
1279 | if (vm->page_tables == NULL) { | |
1280 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1281 | return -ENOMEM; | |
1282 | } | |
1283 | ||
05906dec BN |
1284 | vm->page_directory_fence = NULL; |
1285 | ||
d38ceaf9 | 1286 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1287 | AMDGPU_GEM_DOMAIN_VRAM, |
1288 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1289 | NULL, NULL, &vm->page_directory); |
d38ceaf9 AD |
1290 | if (r) |
1291 | return r; | |
ef9f0a83 CZ |
1292 | r = amdgpu_bo_reserve(vm->page_directory, false); |
1293 | if (r) { | |
1294 | amdgpu_bo_unref(&vm->page_directory); | |
1295 | vm->page_directory = NULL; | |
1296 | return r; | |
1297 | } | |
d38ceaf9 | 1298 | r = amdgpu_vm_clear_bo(adev, vm->page_directory); |
ef9f0a83 | 1299 | amdgpu_bo_unreserve(vm->page_directory); |
d38ceaf9 AD |
1300 | if (r) { |
1301 | amdgpu_bo_unref(&vm->page_directory); | |
1302 | vm->page_directory = NULL; | |
1303 | return r; | |
1304 | } | |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | ||
1309 | /** | |
1310 | * amdgpu_vm_fini - tear down a vm instance | |
1311 | * | |
1312 | * @adev: amdgpu_device pointer | |
1313 | * @vm: requested vm | |
1314 | * | |
1315 | * Tear down @vm (cayman+). | |
1316 | * Unbind the VM and remove all bos from the vm bo list | |
1317 | */ | |
1318 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1319 | { | |
1320 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1321 | int i; | |
1322 | ||
1323 | if (!RB_EMPTY_ROOT(&vm->va)) { | |
1324 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1325 | } | |
1326 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1327 | list_del(&mapping->list); | |
1328 | interval_tree_remove(&mapping->it, &vm->va); | |
1329 | kfree(mapping); | |
1330 | } | |
1331 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1332 | list_del(&mapping->list); | |
1333 | kfree(mapping); | |
1334 | } | |
1335 | ||
1336 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
1337 | amdgpu_bo_unref(&vm->page_tables[i].bo); | |
1338 | kfree(vm->page_tables); | |
1339 | ||
1340 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1341 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1342 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
1c16c0a7 CK |
1343 | unsigned id = vm->ids[i].id; |
1344 | ||
1345 | atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner, | |
1346 | (long)vm, 0); | |
3c62338c | 1347 | fence_put(vm->ids[i].flushed_updates); |
d38ceaf9 AD |
1348 | } |
1349 | ||
d38ceaf9 | 1350 | } |
ea89f8c9 CK |
1351 | |
1352 | /** | |
1353 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1354 | * | |
1355 | * @adev: amdgpu_device pointer | |
1356 | * | |
1357 | * Cleanup the VM manager and free resources. | |
1358 | */ | |
1359 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1360 | { | |
1361 | unsigned i; | |
1362 | ||
1363 | for (i = 0; i < AMDGPU_NUM_VM; ++i) | |
1c16c0a7 | 1364 | fence_put(adev->vm_manager.ids[i].active); |
ea89f8c9 | 1365 | } |