Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * amdgpu_vm_num_pde - return the number of page directory entries | |
55 | * | |
56 | * @adev: amdgpu_device pointer | |
57 | * | |
58 | * Calculate the number of page directory entries (cayman+). | |
59 | */ | |
60 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
61 | { | |
62 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
63 | } | |
64 | ||
65 | /** | |
66 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
67 | * | |
68 | * @adev: amdgpu_device pointer | |
69 | * | |
70 | * Calculate the size of the page directory in bytes (cayman+). | |
71 | */ | |
72 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
73 | { | |
74 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
75 | } | |
76 | ||
77 | /** | |
78 | * amdgpu_vm_get_bos - add the vm BOs to a validation list | |
79 | * | |
80 | * @vm: vm providing the BOs | |
81 | * @head: head of validation list | |
82 | * | |
83 | * Add the page directory to the list of BOs to | |
84 | * validate for command submission (cayman+). | |
85 | */ | |
86 | struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, | |
87 | struct amdgpu_vm *vm, | |
88 | struct list_head *head) | |
89 | { | |
90 | struct amdgpu_bo_list_entry *list; | |
91 | unsigned i, idx; | |
92 | ||
3d5a08c1 | 93 | mutex_lock(&vm->mutex); |
d38ceaf9 AD |
94 | list = drm_malloc_ab(vm->max_pde_used + 2, |
95 | sizeof(struct amdgpu_bo_list_entry)); | |
3d5a08c1 | 96 | if (!list) { |
97 | mutex_unlock(&vm->mutex); | |
d38ceaf9 | 98 | return NULL; |
3d5a08c1 | 99 | } |
d38ceaf9 AD |
100 | |
101 | /* add the vm page table to the list */ | |
102 | list[0].robj = vm->page_directory; | |
103 | list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
104 | list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
105 | list[0].priority = 0; | |
106 | list[0].tv.bo = &vm->page_directory->tbo; | |
107 | list[0].tv.shared = true; | |
108 | list_add(&list[0].tv.head, head); | |
109 | ||
110 | for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { | |
111 | if (!vm->page_tables[i].bo) | |
112 | continue; | |
113 | ||
114 | list[idx].robj = vm->page_tables[i].bo; | |
115 | list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
116 | list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; | |
117 | list[idx].priority = 0; | |
118 | list[idx].tv.bo = &list[idx].robj->tbo; | |
119 | list[idx].tv.shared = true; | |
120 | list_add(&list[idx++].tv.head, head); | |
121 | } | |
3d5a08c1 | 122 | mutex_unlock(&vm->mutex); |
d38ceaf9 AD |
123 | |
124 | return list; | |
125 | } | |
126 | ||
127 | /** | |
128 | * amdgpu_vm_grab_id - allocate the next free VMID | |
129 | * | |
d38ceaf9 | 130 | * @vm: vm to allocate id for |
7f8a5290 CK |
131 | * @ring: ring we want to submit job to |
132 | * @sync: sync object where we add dependencies | |
d38ceaf9 | 133 | * |
7f8a5290 | 134 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 135 | * |
7f8a5290 | 136 | * Global mutex must be locked! |
d38ceaf9 | 137 | */ |
7f8a5290 CK |
138 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
139 | struct amdgpu_sync *sync) | |
d38ceaf9 AD |
140 | { |
141 | struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {}; | |
142 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; | |
143 | struct amdgpu_device *adev = ring->adev; | |
144 | ||
145 | unsigned choices[2] = {}; | |
146 | unsigned i; | |
147 | ||
148 | /* check if the id is still valid */ | |
149 | if (vm_id->id && vm_id->last_id_use && | |
39ff8449 CK |
150 | vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) { |
151 | trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); | |
7f8a5290 | 152 | return 0; |
39ff8449 | 153 | } |
d38ceaf9 AD |
154 | |
155 | /* we definately need to flush */ | |
156 | vm_id->pd_gpu_addr = ~0ll; | |
157 | ||
158 | /* skip over VMID 0, since it is the system VM */ | |
159 | for (i = 1; i < adev->vm_manager.nvm; ++i) { | |
160 | struct amdgpu_fence *fence = adev->vm_manager.active[i]; | |
161 | ||
162 | if (fence == NULL) { | |
163 | /* found a free one */ | |
164 | vm_id->id = i; | |
165 | trace_amdgpu_vm_grab_id(i, ring->idx); | |
7f8a5290 | 166 | return 0; |
d38ceaf9 AD |
167 | } |
168 | ||
169 | if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) { | |
170 | best[fence->ring->idx] = fence; | |
171 | choices[fence->ring == ring ? 0 : 1] = i; | |
172 | } | |
173 | } | |
174 | ||
175 | for (i = 0; i < 2; ++i) { | |
176 | if (choices[i]) { | |
7f8a5290 CK |
177 | struct amdgpu_fence *fence; |
178 | ||
179 | fence = adev->vm_manager.active[choices[i]]; | |
d38ceaf9 | 180 | vm_id->id = choices[i]; |
7f8a5290 | 181 | |
d38ceaf9 | 182 | trace_amdgpu_vm_grab_id(choices[i], ring->idx); |
7f8a5290 | 183 | return amdgpu_sync_fence(ring->adev, sync, &fence->base); |
d38ceaf9 AD |
184 | } |
185 | } | |
186 | ||
187 | /* should never happen */ | |
188 | BUG(); | |
7f8a5290 | 189 | return -EINVAL; |
d38ceaf9 AD |
190 | } |
191 | ||
192 | /** | |
193 | * amdgpu_vm_flush - hardware flush the vm | |
194 | * | |
195 | * @ring: ring to use for flush | |
196 | * @vm: vm we want to flush | |
197 | * @updates: last vm update that we waited for | |
198 | * | |
199 | * Flush the vm (cayman+). | |
200 | * | |
201 | * Global and local mutex must be locked! | |
202 | */ | |
203 | void amdgpu_vm_flush(struct amdgpu_ring *ring, | |
204 | struct amdgpu_vm *vm, | |
3c62338c | 205 | struct fence *updates) |
d38ceaf9 AD |
206 | { |
207 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
208 | struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; | |
3c62338c CZ |
209 | struct fence *flushed_updates = vm_id->flushed_updates; |
210 | bool is_earlier = false; | |
211 | ||
212 | if (flushed_updates && updates) { | |
213 | BUG_ON(flushed_updates->context != updates->context); | |
214 | is_earlier = (updates->seqno - flushed_updates->seqno <= | |
215 | INT_MAX) ? true : false; | |
216 | } | |
d38ceaf9 | 217 | |
fc8fa5e4 | 218 | if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates || |
3c62338c | 219 | is_earlier) { |
d38ceaf9 AD |
220 | |
221 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); | |
3c62338c CZ |
222 | if (is_earlier) { |
223 | vm_id->flushed_updates = fence_get(updates); | |
224 | fence_put(flushed_updates); | |
225 | } | |
226 | if (!flushed_updates) | |
227 | vm_id->flushed_updates = fence_get(updates); | |
d38ceaf9 AD |
228 | vm_id->pd_gpu_addr = pd_addr; |
229 | amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); | |
230 | } | |
231 | } | |
232 | ||
233 | /** | |
234 | * amdgpu_vm_fence - remember fence for vm | |
235 | * | |
236 | * @adev: amdgpu_device pointer | |
237 | * @vm: vm we want to fence | |
238 | * @fence: fence to remember | |
239 | * | |
240 | * Fence the vm (cayman+). | |
241 | * Set the fence used to protect page table and id. | |
242 | * | |
243 | * Global and local mutex must be locked! | |
244 | */ | |
245 | void amdgpu_vm_fence(struct amdgpu_device *adev, | |
246 | struct amdgpu_vm *vm, | |
247 | struct amdgpu_fence *fence) | |
248 | { | |
249 | unsigned ridx = fence->ring->idx; | |
250 | unsigned vm_id = vm->ids[ridx].id; | |
251 | ||
252 | amdgpu_fence_unref(&adev->vm_manager.active[vm_id]); | |
253 | adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence); | |
254 | ||
255 | amdgpu_fence_unref(&vm->ids[ridx].last_id_use); | |
256 | vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence); | |
257 | } | |
258 | ||
259 | /** | |
260 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
261 | * | |
262 | * @vm: requested vm | |
263 | * @bo: requested buffer object | |
264 | * | |
265 | * Find @bo inside the requested vm (cayman+). | |
266 | * Search inside the @bos vm list for the requested vm | |
267 | * Returns the found bo_va or NULL if none is found | |
268 | * | |
269 | * Object has to be reserved! | |
270 | */ | |
271 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
272 | struct amdgpu_bo *bo) | |
273 | { | |
274 | struct amdgpu_bo_va *bo_va; | |
275 | ||
276 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
277 | if (bo_va->vm == vm) { | |
278 | return bo_va; | |
279 | } | |
280 | } | |
281 | return NULL; | |
282 | } | |
283 | ||
284 | /** | |
285 | * amdgpu_vm_update_pages - helper to call the right asic function | |
286 | * | |
287 | * @adev: amdgpu_device pointer | |
288 | * @ib: indirect buffer to fill with commands | |
289 | * @pe: addr of the page entry | |
290 | * @addr: dst addr to write into pe | |
291 | * @count: number of page entries to update | |
292 | * @incr: increase next addr by incr bytes | |
293 | * @flags: hw access flags | |
294 | * @gtt_flags: GTT hw access flags | |
295 | * | |
296 | * Traces the parameters and calls the right asic functions | |
297 | * to setup the page table using the DMA. | |
298 | */ | |
299 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
300 | struct amdgpu_ib *ib, | |
301 | uint64_t pe, uint64_t addr, | |
302 | unsigned count, uint32_t incr, | |
303 | uint32_t flags, uint32_t gtt_flags) | |
304 | { | |
305 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
306 | ||
307 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
308 | uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; | |
309 | amdgpu_vm_copy_pte(adev, ib, pe, src, count); | |
310 | ||
311 | } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { | |
312 | amdgpu_vm_write_pte(adev, ib, pe, addr, | |
313 | count, incr, flags); | |
314 | ||
315 | } else { | |
316 | amdgpu_vm_set_pte_pde(adev, ib, pe, addr, | |
317 | count, incr, flags); | |
318 | } | |
319 | } | |
320 | ||
4c7eb91c | 321 | int amdgpu_vm_free_job(struct amdgpu_job *job) |
d5fc5e82 CZ |
322 | { |
323 | int i; | |
4c7eb91c JZ |
324 | for (i = 0; i < job->num_ibs; i++) |
325 | amdgpu_ib_free(job->adev, &job->ibs[i]); | |
326 | kfree(job->ibs); | |
d5fc5e82 CZ |
327 | return 0; |
328 | } | |
329 | ||
d38ceaf9 AD |
330 | /** |
331 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
332 | * | |
333 | * @adev: amdgpu_device pointer | |
334 | * @bo: bo to clear | |
335 | */ | |
336 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
337 | struct amdgpu_bo *bo) | |
338 | { | |
339 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
4af9f07c | 340 | struct fence *fence = NULL; |
d5fc5e82 | 341 | struct amdgpu_ib *ib; |
d38ceaf9 AD |
342 | unsigned entries; |
343 | uint64_t addr; | |
344 | int r; | |
345 | ||
346 | r = amdgpu_bo_reserve(bo, false); | |
347 | if (r) | |
348 | return r; | |
349 | ||
ca952613 | 350 | r = reservation_object_reserve_shared(bo->tbo.resv); |
351 | if (r) | |
352 | return r; | |
353 | ||
d38ceaf9 AD |
354 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
355 | if (r) | |
356 | goto error_unreserve; | |
357 | ||
358 | addr = amdgpu_bo_gpu_offset(bo); | |
359 | entries = amdgpu_bo_size(bo) / 8; | |
360 | ||
d5fc5e82 CZ |
361 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
362 | if (!ib) | |
d38ceaf9 AD |
363 | goto error_unreserve; |
364 | ||
d5fc5e82 | 365 | r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); |
d38ceaf9 AD |
366 | if (r) |
367 | goto error_free; | |
368 | ||
d5fc5e82 CZ |
369 | ib->length_dw = 0; |
370 | ||
371 | amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0); | |
372 | amdgpu_vm_pad_ib(adev, ib); | |
373 | WARN_ON(ib->length_dw > 64); | |
4af9f07c CZ |
374 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
375 | &amdgpu_vm_free_job, | |
376 | AMDGPU_FENCE_OWNER_VM, | |
377 | &fence); | |
378 | if (!r) | |
379 | amdgpu_bo_fence(bo, fence, true); | |
281b4223 | 380 | fence_put(fence); |
d5fc5e82 | 381 | if (amdgpu_enable_scheduler) { |
d5fc5e82 CZ |
382 | amdgpu_bo_unreserve(bo); |
383 | return 0; | |
d5fc5e82 | 384 | } |
d38ceaf9 | 385 | error_free: |
d5fc5e82 CZ |
386 | amdgpu_ib_free(adev, ib); |
387 | kfree(ib); | |
d38ceaf9 AD |
388 | |
389 | error_unreserve: | |
390 | amdgpu_bo_unreserve(bo); | |
391 | return r; | |
392 | } | |
393 | ||
394 | /** | |
395 | * amdgpu_vm_map_gart - get the physical address of a gart page | |
396 | * | |
397 | * @adev: amdgpu_device pointer | |
398 | * @addr: the unmapped addr | |
399 | * | |
400 | * Look up the physical address of the page that the pte resolves | |
401 | * to (cayman+). | |
402 | * Returns the physical address of the page. | |
403 | */ | |
404 | uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) | |
405 | { | |
406 | uint64_t result; | |
407 | ||
408 | /* page table offset */ | |
409 | result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; | |
410 | ||
411 | /* in case cpu page size != gpu page size*/ | |
412 | result |= addr & (~PAGE_MASK); | |
413 | ||
414 | return result; | |
415 | } | |
416 | ||
417 | /** | |
418 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
419 | * | |
420 | * @adev: amdgpu_device pointer | |
421 | * @vm: requested vm | |
422 | * @start: start of GPU address range | |
423 | * @end: end of GPU address range | |
424 | * | |
425 | * Allocates new page tables if necessary | |
426 | * and updates the page directory (cayman+). | |
427 | * Returns 0 for success, error for failure. | |
428 | * | |
429 | * Global and local mutex must be locked! | |
430 | */ | |
431 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
432 | struct amdgpu_vm *vm) | |
433 | { | |
434 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
435 | struct amdgpu_bo *pd = vm->page_directory; | |
436 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
437 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
438 | uint64_t last_pde = ~0, last_pt = ~0; | |
439 | unsigned count = 0, pt_idx, ndw; | |
d5fc5e82 | 440 | struct amdgpu_ib *ib; |
4af9f07c | 441 | struct fence *fence = NULL; |
d5fc5e82 | 442 | |
d38ceaf9 AD |
443 | int r; |
444 | ||
445 | /* padding, etc. */ | |
446 | ndw = 64; | |
447 | ||
448 | /* assume the worst case */ | |
449 | ndw += vm->max_pde_used * 6; | |
450 | ||
451 | /* update too big for an IB */ | |
452 | if (ndw > 0xfffff) | |
453 | return -ENOMEM; | |
454 | ||
d5fc5e82 CZ |
455 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
456 | if (!ib) | |
457 | return -ENOMEM; | |
458 | ||
459 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
d38ceaf9 AD |
460 | if (r) |
461 | return r; | |
d5fc5e82 | 462 | ib->length_dw = 0; |
d38ceaf9 AD |
463 | |
464 | /* walk over the address space and update the page directory */ | |
465 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
466 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; | |
467 | uint64_t pde, pt; | |
468 | ||
469 | if (bo == NULL) | |
470 | continue; | |
471 | ||
472 | pt = amdgpu_bo_gpu_offset(bo); | |
473 | if (vm->page_tables[pt_idx].addr == pt) | |
474 | continue; | |
475 | vm->page_tables[pt_idx].addr = pt; | |
476 | ||
477 | pde = pd_addr + pt_idx * 8; | |
478 | if (((last_pde + 8 * count) != pde) || | |
479 | ((last_pt + incr * count) != pt)) { | |
480 | ||
481 | if (count) { | |
d5fc5e82 | 482 | amdgpu_vm_update_pages(adev, ib, last_pde, |
d38ceaf9 AD |
483 | last_pt, count, incr, |
484 | AMDGPU_PTE_VALID, 0); | |
485 | } | |
486 | ||
487 | count = 1; | |
488 | last_pde = pde; | |
489 | last_pt = pt; | |
490 | } else { | |
491 | ++count; | |
492 | } | |
493 | } | |
494 | ||
495 | if (count) | |
d5fc5e82 | 496 | amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, |
d38ceaf9 AD |
497 | incr, AMDGPU_PTE_VALID, 0); |
498 | ||
d5fc5e82 CZ |
499 | if (ib->length_dw != 0) { |
500 | amdgpu_vm_pad_ib(adev, ib); | |
501 | amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); | |
502 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
503 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
504 | &amdgpu_vm_free_job, | |
505 | AMDGPU_FENCE_OWNER_VM, | |
506 | &fence); | |
507 | if (r) | |
508 | goto error_free; | |
05906dec | 509 | |
4af9f07c | 510 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
511 | fence_put(vm->page_directory_fence); |
512 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 513 | fence_put(fence); |
d38ceaf9 | 514 | } |
d5fc5e82 CZ |
515 | |
516 | if (!amdgpu_enable_scheduler || ib->length_dw == 0) { | |
517 | amdgpu_ib_free(adev, ib); | |
518 | kfree(ib); | |
519 | } | |
d38ceaf9 AD |
520 | |
521 | return 0; | |
d5fc5e82 CZ |
522 | |
523 | error_free: | |
d5fc5e82 CZ |
524 | amdgpu_ib_free(adev, ib); |
525 | kfree(ib); | |
4af9f07c | 526 | return r; |
d38ceaf9 AD |
527 | } |
528 | ||
529 | /** | |
530 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
531 | * | |
532 | * @adev: amdgpu_device pointer | |
533 | * @ib: IB for the update | |
534 | * @pe_start: first PTE to handle | |
535 | * @pe_end: last PTE to handle | |
536 | * @addr: addr those PTEs should point to | |
537 | * @flags: hw mapping flags | |
538 | * @gtt_flags: GTT hw mapping flags | |
539 | * | |
540 | * Global and local mutex must be locked! | |
541 | */ | |
542 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
543 | struct amdgpu_ib *ib, | |
544 | uint64_t pe_start, uint64_t pe_end, | |
545 | uint64_t addr, uint32_t flags, | |
546 | uint32_t gtt_flags) | |
547 | { | |
548 | /** | |
549 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
550 | * field in the PTE. When this field is set to a non-zero value, page | |
551 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
552 | * flags are considered valid for all PTEs within the fragment range | |
553 | * and corresponding mappings are assumed to be physically contiguous. | |
554 | * | |
555 | * The L1 TLB can store a single PTE for the whole fragment, | |
556 | * significantly increasing the space available for translation | |
557 | * caching. This leads to large improvements in throughput when the | |
558 | * TLB is under pressure. | |
559 | * | |
560 | * The L2 TLB distributes small and large fragments into two | |
561 | * asymmetric partitions. The large fragment cache is significantly | |
562 | * larger. Thus, we try to use large fragments wherever possible. | |
563 | * Userspace can support this by aligning virtual base address and | |
564 | * allocation size to the fragment size. | |
565 | */ | |
566 | ||
567 | /* SI and newer are optimized for 64KB */ | |
568 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
569 | uint64_t frag_align = 0x80; | |
570 | ||
571 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
572 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
573 | ||
574 | unsigned count; | |
575 | ||
576 | /* system pages are non continuously */ | |
577 | if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) || | |
578 | (frag_start >= frag_end)) { | |
579 | ||
580 | count = (pe_end - pe_start) / 8; | |
581 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
582 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
583 | return; | |
584 | } | |
585 | ||
586 | /* handle the 4K area at the beginning */ | |
587 | if (pe_start != frag_start) { | |
588 | count = (frag_start - pe_start) / 8; | |
589 | amdgpu_vm_update_pages(adev, ib, pe_start, addr, count, | |
590 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
591 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
592 | } | |
593 | ||
594 | /* handle the area in the middle */ | |
595 | count = (frag_end - frag_start) / 8; | |
596 | amdgpu_vm_update_pages(adev, ib, frag_start, addr, count, | |
597 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags, | |
598 | gtt_flags); | |
599 | ||
600 | /* handle the 4K area at the end */ | |
601 | if (frag_end != pe_end) { | |
602 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
603 | count = (pe_end - frag_end) / 8; | |
604 | amdgpu_vm_update_pages(adev, ib, frag_end, addr, count, | |
605 | AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags); | |
606 | } | |
607 | } | |
608 | ||
609 | /** | |
610 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
611 | * | |
612 | * @adev: amdgpu_device pointer | |
613 | * @vm: requested vm | |
614 | * @start: start of GPU address range | |
615 | * @end: end of GPU address range | |
616 | * @dst: destination address to map to | |
617 | * @flags: mapping flags | |
618 | * | |
619 | * Update the page tables in the range @start - @end (cayman+). | |
620 | * | |
621 | * Global and local mutex must be locked! | |
622 | */ | |
623 | static int amdgpu_vm_update_ptes(struct amdgpu_device *adev, | |
624 | struct amdgpu_vm *vm, | |
625 | struct amdgpu_ib *ib, | |
626 | uint64_t start, uint64_t end, | |
627 | uint64_t dst, uint32_t flags, | |
628 | uint32_t gtt_flags) | |
629 | { | |
630 | uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; | |
631 | uint64_t last_pte = ~0, last_dst = ~0; | |
a60c4232 | 632 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
633 | unsigned count = 0; |
634 | uint64_t addr; | |
635 | ||
a60c4232 CK |
636 | /* sync to everything on unmapping */ |
637 | if (!(flags & AMDGPU_PTE_VALID)) | |
638 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
639 | ||
d38ceaf9 AD |
640 | /* walk over the address space and update the page tables */ |
641 | for (addr = start; addr < end; ) { | |
642 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
643 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo; | |
644 | unsigned nptes; | |
645 | uint64_t pte; | |
646 | int r; | |
647 | ||
a60c4232 | 648 | amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner); |
d38ceaf9 AD |
649 | r = reservation_object_reserve_shared(pt->tbo.resv); |
650 | if (r) | |
651 | return r; | |
652 | ||
653 | if ((addr & ~mask) == (end & ~mask)) | |
654 | nptes = end - addr; | |
655 | else | |
656 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
657 | ||
658 | pte = amdgpu_bo_gpu_offset(pt); | |
659 | pte += (addr & mask) * 8; | |
660 | ||
661 | if ((last_pte + 8 * count) != pte) { | |
662 | ||
663 | if (count) { | |
664 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
665 | last_pte + 8 * count, | |
666 | last_dst, flags, | |
667 | gtt_flags); | |
668 | } | |
669 | ||
670 | count = nptes; | |
671 | last_pte = pte; | |
672 | last_dst = dst; | |
673 | } else { | |
674 | count += nptes; | |
675 | } | |
676 | ||
677 | addr += nptes; | |
678 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
679 | } | |
680 | ||
681 | if (count) { | |
682 | amdgpu_vm_frag_ptes(adev, ib, last_pte, | |
683 | last_pte + 8 * count, | |
684 | last_dst, flags, gtt_flags); | |
685 | } | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
d38ceaf9 AD |
690 | /** |
691 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
692 | * | |
693 | * @adev: amdgpu_device pointer | |
694 | * @vm: requested vm | |
695 | * @mapping: mapped range and flags to use for the update | |
696 | * @addr: addr to set the area to | |
697 | * @gtt_flags: flags as they are used for GTT | |
698 | * @fence: optional resulting fence | |
699 | * | |
700 | * Fill in the page table entries for @mapping. | |
701 | * Returns 0 for success, -EINVAL for failure. | |
702 | * | |
703 | * Object have to be reserved and mutex must be locked! | |
704 | */ | |
705 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
706 | struct amdgpu_vm *vm, | |
707 | struct amdgpu_bo_va_mapping *mapping, | |
708 | uint64_t addr, uint32_t gtt_flags, | |
bb1e38a4 | 709 | struct fence **fence) |
d38ceaf9 AD |
710 | { |
711 | struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; | |
712 | unsigned nptes, ncmds, ndw; | |
713 | uint32_t flags = gtt_flags; | |
d5fc5e82 | 714 | struct amdgpu_ib *ib; |
4af9f07c | 715 | struct fence *f = NULL; |
d38ceaf9 AD |
716 | int r; |
717 | ||
718 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
719 | * but in case of something, we filter the flags in first place | |
720 | */ | |
721 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
722 | flags &= ~AMDGPU_PTE_READABLE; | |
723 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
724 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
725 | ||
726 | trace_amdgpu_vm_bo_update(mapping); | |
727 | ||
728 | nptes = mapping->it.last - mapping->it.start + 1; | |
729 | ||
730 | /* | |
731 | * reserve space for one command every (1 << BLOCK_SIZE) | |
732 | * entries or 2k dwords (whatever is smaller) | |
733 | */ | |
734 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
735 | ||
736 | /* padding, etc. */ | |
737 | ndw = 64; | |
738 | ||
739 | if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { | |
740 | /* only copy commands needed */ | |
741 | ndw += ncmds * 7; | |
742 | ||
743 | } else if (flags & AMDGPU_PTE_SYSTEM) { | |
744 | /* header for write data commands */ | |
745 | ndw += ncmds * 4; | |
746 | ||
747 | /* body of write data command */ | |
748 | ndw += nptes * 2; | |
749 | ||
750 | } else { | |
751 | /* set page commands needed */ | |
752 | ndw += ncmds * 10; | |
753 | ||
754 | /* two extra commands for begin/end of fragment */ | |
755 | ndw += 2 * 10; | |
756 | } | |
757 | ||
758 | /* update too big for an IB */ | |
759 | if (ndw > 0xfffff) | |
760 | return -ENOMEM; | |
761 | ||
d5fc5e82 CZ |
762 | ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); |
763 | if (!ib) | |
764 | return -ENOMEM; | |
765 | ||
766 | r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); | |
767 | if (r) { | |
768 | kfree(ib); | |
d38ceaf9 | 769 | return r; |
d5fc5e82 CZ |
770 | } |
771 | ||
772 | ib->length_dw = 0; | |
d38ceaf9 | 773 | |
d5fc5e82 | 774 | r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start, |
d38ceaf9 AD |
775 | mapping->it.last + 1, addr + mapping->offset, |
776 | flags, gtt_flags); | |
777 | ||
778 | if (r) { | |
d5fc5e82 CZ |
779 | amdgpu_ib_free(adev, ib); |
780 | kfree(ib); | |
d38ceaf9 AD |
781 | return r; |
782 | } | |
783 | ||
d5fc5e82 CZ |
784 | amdgpu_vm_pad_ib(adev, ib); |
785 | WARN_ON(ib->length_dw > ndw); | |
4af9f07c CZ |
786 | r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, |
787 | &amdgpu_vm_free_job, | |
788 | AMDGPU_FENCE_OWNER_VM, | |
789 | &f); | |
790 | if (r) | |
791 | goto error_free; | |
d38ceaf9 | 792 | |
bf60efd3 | 793 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
794 | if (fence) { |
795 | fence_put(*fence); | |
796 | *fence = fence_get(f); | |
797 | } | |
281b4223 | 798 | fence_put(f); |
4af9f07c | 799 | if (!amdgpu_enable_scheduler) { |
d5fc5e82 CZ |
800 | amdgpu_ib_free(adev, ib); |
801 | kfree(ib); | |
802 | } | |
d38ceaf9 | 803 | return 0; |
d5fc5e82 CZ |
804 | |
805 | error_free: | |
d5fc5e82 CZ |
806 | amdgpu_ib_free(adev, ib); |
807 | kfree(ib); | |
4af9f07c | 808 | return r; |
d38ceaf9 AD |
809 | } |
810 | ||
811 | /** | |
812 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
813 | * | |
814 | * @adev: amdgpu_device pointer | |
815 | * @bo_va: requested BO and VM object | |
816 | * @mem: ttm mem | |
817 | * | |
818 | * Fill in the page table entries for @bo_va. | |
819 | * Returns 0 for success, -EINVAL for failure. | |
820 | * | |
821 | * Object have to be reserved and mutex must be locked! | |
822 | */ | |
823 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
824 | struct amdgpu_bo_va *bo_va, | |
825 | struct ttm_mem_reg *mem) | |
826 | { | |
827 | struct amdgpu_vm *vm = bo_va->vm; | |
828 | struct amdgpu_bo_va_mapping *mapping; | |
829 | uint32_t flags; | |
830 | uint64_t addr; | |
831 | int r; | |
832 | ||
833 | if (mem) { | |
b7d698d7 | 834 | addr = (u64)mem->start << PAGE_SHIFT; |
d38ceaf9 AD |
835 | if (mem->mem_type != TTM_PL_TT) |
836 | addr += adev->vm_manager.vram_base_offset; | |
837 | } else { | |
838 | addr = 0; | |
839 | } | |
840 | ||
d38ceaf9 AD |
841 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
842 | ||
7fc11959 CK |
843 | spin_lock(&vm->status_lock); |
844 | if (!list_empty(&bo_va->vm_status)) | |
845 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
846 | spin_unlock(&vm->status_lock); | |
847 | ||
848 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
d38ceaf9 AD |
849 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr, |
850 | flags, &bo_va->last_pt_update); | |
851 | if (r) | |
852 | return r; | |
853 | } | |
854 | ||
d6c10f6b CK |
855 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
856 | list_for_each_entry(mapping, &bo_va->valids, list) | |
857 | trace_amdgpu_vm_bo_mapping(mapping); | |
858 | ||
859 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
860 | trace_amdgpu_vm_bo_mapping(mapping); | |
861 | } | |
862 | ||
d38ceaf9 | 863 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 864 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 865 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
866 | if (!mem) |
867 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
868 | spin_unlock(&vm->status_lock); |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | /** | |
874 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
875 | * | |
876 | * @adev: amdgpu_device pointer | |
877 | * @vm: requested vm | |
878 | * | |
879 | * Make sure all freed BOs are cleared in the PT. | |
880 | * Returns 0 for success. | |
881 | * | |
882 | * PTs have to be reserved and mutex must be locked! | |
883 | */ | |
884 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
885 | struct amdgpu_vm *vm) | |
886 | { | |
887 | struct amdgpu_bo_va_mapping *mapping; | |
888 | int r; | |
889 | ||
890 | while (!list_empty(&vm->freed)) { | |
891 | mapping = list_first_entry(&vm->freed, | |
892 | struct amdgpu_bo_va_mapping, list); | |
893 | list_del(&mapping->list); | |
894 | ||
895 | r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL); | |
896 | kfree(mapping); | |
897 | if (r) | |
898 | return r; | |
899 | ||
900 | } | |
901 | return 0; | |
902 | ||
903 | } | |
904 | ||
905 | /** | |
906 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
907 | * | |
908 | * @adev: amdgpu_device pointer | |
909 | * @vm: requested vm | |
910 | * | |
911 | * Make sure all invalidated BOs are cleared in the PT. | |
912 | * Returns 0 for success. | |
913 | * | |
914 | * PTs have to be reserved and mutex must be locked! | |
915 | */ | |
916 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 917 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 918 | { |
cfe2c978 | 919 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 920 | int r = 0; |
d38ceaf9 AD |
921 | |
922 | spin_lock(&vm->status_lock); | |
923 | while (!list_empty(&vm->invalidated)) { | |
924 | bo_va = list_first_entry(&vm->invalidated, | |
925 | struct amdgpu_bo_va, vm_status); | |
926 | spin_unlock(&vm->status_lock); | |
927 | ||
928 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); | |
929 | if (r) | |
930 | return r; | |
931 | ||
932 | spin_lock(&vm->status_lock); | |
933 | } | |
934 | spin_unlock(&vm->status_lock); | |
935 | ||
cfe2c978 | 936 | if (bo_va) |
bb1e38a4 | 937 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
938 | |
939 | return r; | |
d38ceaf9 AD |
940 | } |
941 | ||
942 | /** | |
943 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
944 | * | |
945 | * @adev: amdgpu_device pointer | |
946 | * @vm: requested vm | |
947 | * @bo: amdgpu buffer object | |
948 | * | |
949 | * Add @bo into the requested vm (cayman+). | |
950 | * Add @bo to the list of bos associated with the vm | |
951 | * Returns newly added bo_va or NULL for failure | |
952 | * | |
953 | * Object has to be reserved! | |
954 | */ | |
955 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
956 | struct amdgpu_vm *vm, | |
957 | struct amdgpu_bo *bo) | |
958 | { | |
959 | struct amdgpu_bo_va *bo_va; | |
960 | ||
961 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
962 | if (bo_va == NULL) { | |
963 | return NULL; | |
964 | } | |
965 | bo_va->vm = vm; | |
966 | bo_va->bo = bo; | |
d38ceaf9 AD |
967 | bo_va->ref_count = 1; |
968 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
969 | INIT_LIST_HEAD(&bo_va->valids); |
970 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 AD |
971 | INIT_LIST_HEAD(&bo_va->vm_status); |
972 | ||
973 | mutex_lock(&vm->mutex); | |
974 | list_add_tail(&bo_va->bo_list, &bo->va); | |
975 | mutex_unlock(&vm->mutex); | |
976 | ||
977 | return bo_va; | |
978 | } | |
979 | ||
980 | /** | |
981 | * amdgpu_vm_bo_map - map bo inside a vm | |
982 | * | |
983 | * @adev: amdgpu_device pointer | |
984 | * @bo_va: bo_va to store the address | |
985 | * @saddr: where to map the BO | |
986 | * @offset: requested offset in the BO | |
987 | * @flags: attributes of pages (read/write/valid/etc.) | |
988 | * | |
989 | * Add a mapping of the BO at the specefied addr into the VM. | |
990 | * Returns 0 for success, error for failure. | |
991 | * | |
992 | * Object has to be reserved and gets unreserved by this function! | |
993 | */ | |
994 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
995 | struct amdgpu_bo_va *bo_va, | |
996 | uint64_t saddr, uint64_t offset, | |
997 | uint64_t size, uint32_t flags) | |
998 | { | |
999 | struct amdgpu_bo_va_mapping *mapping; | |
1000 | struct amdgpu_vm *vm = bo_va->vm; | |
1001 | struct interval_tree_node *it; | |
1002 | unsigned last_pfn, pt_idx; | |
1003 | uint64_t eaddr; | |
1004 | int r; | |
1005 | ||
0be52de9 CK |
1006 | /* validate the parameters */ |
1007 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
1008 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) { | |
1009 | amdgpu_bo_unreserve(bo_va->bo); | |
1010 | return -EINVAL; | |
1011 | } | |
1012 | ||
d38ceaf9 AD |
1013 | /* make sure object fit at this offset */ |
1014 | eaddr = saddr + size; | |
1015 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) { | |
1016 | amdgpu_bo_unreserve(bo_va->bo); | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
1021 | if (last_pfn > adev->vm_manager.max_pfn) { | |
1022 | dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n", | |
1023 | last_pfn, adev->vm_manager.max_pfn); | |
1024 | amdgpu_bo_unreserve(bo_va->bo); | |
1025 | return -EINVAL; | |
1026 | } | |
1027 | ||
1028 | mutex_lock(&vm->mutex); | |
1029 | ||
1030 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
1031 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1032 | ||
1033 | it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1); | |
1034 | if (it) { | |
1035 | struct amdgpu_bo_va_mapping *tmp; | |
1036 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1037 | /* bo and tmp overlap, invalid addr */ | |
1038 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1039 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1040 | tmp->it.start, tmp->it.last + 1); | |
1041 | amdgpu_bo_unreserve(bo_va->bo); | |
1042 | r = -EINVAL; | |
1043 | goto error_unlock; | |
1044 | } | |
1045 | ||
1046 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1047 | if (!mapping) { | |
1048 | amdgpu_bo_unreserve(bo_va->bo); | |
1049 | r = -ENOMEM; | |
1050 | goto error_unlock; | |
1051 | } | |
1052 | ||
1053 | INIT_LIST_HEAD(&mapping->list); | |
1054 | mapping->it.start = saddr; | |
1055 | mapping->it.last = eaddr - 1; | |
1056 | mapping->offset = offset; | |
1057 | mapping->flags = flags; | |
1058 | ||
7fc11959 | 1059 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 | 1060 | interval_tree_insert(&mapping->it, &vm->va); |
93e3e438 | 1061 | trace_amdgpu_vm_bo_map(bo_va, mapping); |
d38ceaf9 AD |
1062 | |
1063 | /* Make sure the page tables are allocated */ | |
1064 | saddr >>= amdgpu_vm_block_size; | |
1065 | eaddr >>= amdgpu_vm_block_size; | |
1066 | ||
1067 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1068 | ||
1069 | if (eaddr > vm->max_pde_used) | |
1070 | vm->max_pde_used = eaddr; | |
1071 | ||
1072 | amdgpu_bo_unreserve(bo_va->bo); | |
1073 | ||
1074 | /* walk over the address space and allocate the page tables */ | |
1075 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1076 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
d38ceaf9 AD |
1077 | struct amdgpu_bo *pt; |
1078 | ||
1079 | if (vm->page_tables[pt_idx].bo) | |
1080 | continue; | |
1081 | ||
1082 | /* drop mutex to allocate and clear page table */ | |
1083 | mutex_unlock(&vm->mutex); | |
1084 | ||
bf60efd3 | 1085 | ww_mutex_lock(&resv->lock, NULL); |
d38ceaf9 AD |
1086 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1087 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1088 | AMDGPU_GEM_DOMAIN_VRAM, |
1089 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 CK |
1090 | NULL, resv, &pt); |
1091 | ww_mutex_unlock(&resv->lock); | |
d38ceaf9 AD |
1092 | if (r) |
1093 | goto error_free; | |
1094 | ||
1095 | r = amdgpu_vm_clear_bo(adev, pt); | |
1096 | if (r) { | |
1097 | amdgpu_bo_unref(&pt); | |
1098 | goto error_free; | |
1099 | } | |
1100 | ||
1101 | /* aquire mutex again */ | |
1102 | mutex_lock(&vm->mutex); | |
1103 | if (vm->page_tables[pt_idx].bo) { | |
1104 | /* someone else allocated the pt in the meantime */ | |
1105 | mutex_unlock(&vm->mutex); | |
1106 | amdgpu_bo_unref(&pt); | |
1107 | mutex_lock(&vm->mutex); | |
1108 | continue; | |
1109 | } | |
1110 | ||
1111 | vm->page_tables[pt_idx].addr = 0; | |
1112 | vm->page_tables[pt_idx].bo = pt; | |
1113 | } | |
1114 | ||
1115 | mutex_unlock(&vm->mutex); | |
1116 | return 0; | |
1117 | ||
1118 | error_free: | |
1119 | mutex_lock(&vm->mutex); | |
1120 | list_del(&mapping->list); | |
1121 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1122 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1123 | kfree(mapping); |
1124 | ||
1125 | error_unlock: | |
1126 | mutex_unlock(&vm->mutex); | |
1127 | return r; | |
1128 | } | |
1129 | ||
1130 | /** | |
1131 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1132 | * | |
1133 | * @adev: amdgpu_device pointer | |
1134 | * @bo_va: bo_va to remove the address from | |
1135 | * @saddr: where to the BO is mapped | |
1136 | * | |
1137 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1138 | * Returns 0 for success, error for failure. | |
1139 | * | |
1140 | * Object has to be reserved and gets unreserved by this function! | |
1141 | */ | |
1142 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1143 | struct amdgpu_bo_va *bo_va, | |
1144 | uint64_t saddr) | |
1145 | { | |
1146 | struct amdgpu_bo_va_mapping *mapping; | |
1147 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1148 | bool valid = true; |
d38ceaf9 | 1149 | |
6c7fc503 CK |
1150 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1151 | ||
7fc11959 | 1152 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1153 | if (mapping->it.start == saddr) |
1154 | break; | |
1155 | } | |
1156 | ||
7fc11959 CK |
1157 | if (&mapping->list == &bo_va->valids) { |
1158 | valid = false; | |
1159 | ||
1160 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1161 | if (mapping->it.start == saddr) | |
1162 | break; | |
1163 | } | |
1164 | ||
1165 | if (&mapping->list == &bo_va->invalids) { | |
1166 | amdgpu_bo_unreserve(bo_va->bo); | |
1167 | return -ENOENT; | |
1168 | } | |
d38ceaf9 AD |
1169 | } |
1170 | ||
1171 | mutex_lock(&vm->mutex); | |
1172 | list_del(&mapping->list); | |
1173 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1174 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1175 | |
7fc11959 | 1176 | if (valid) |
d38ceaf9 | 1177 | list_add(&mapping->list, &vm->freed); |
7fc11959 | 1178 | else |
d38ceaf9 | 1179 | kfree(mapping); |
d38ceaf9 AD |
1180 | mutex_unlock(&vm->mutex); |
1181 | amdgpu_bo_unreserve(bo_va->bo); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1188 | * | |
1189 | * @adev: amdgpu_device pointer | |
1190 | * @bo_va: requested bo_va | |
1191 | * | |
1192 | * Remove @bo_va->bo from the requested vm (cayman+). | |
1193 | * | |
1194 | * Object have to be reserved! | |
1195 | */ | |
1196 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1197 | struct amdgpu_bo_va *bo_va) | |
1198 | { | |
1199 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1200 | struct amdgpu_vm *vm = bo_va->vm; | |
1201 | ||
1202 | list_del(&bo_va->bo_list); | |
1203 | ||
1204 | mutex_lock(&vm->mutex); | |
1205 | ||
1206 | spin_lock(&vm->status_lock); | |
1207 | list_del(&bo_va->vm_status); | |
1208 | spin_unlock(&vm->status_lock); | |
1209 | ||
7fc11959 | 1210 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1211 | list_del(&mapping->list); |
1212 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1213 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1214 | list_add(&mapping->list, &vm->freed); |
1215 | } | |
1216 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1217 | list_del(&mapping->list); | |
1218 | interval_tree_remove(&mapping->it, &vm->va); | |
1219 | kfree(mapping); | |
d38ceaf9 | 1220 | } |
7fc11959 | 1221 | |
bb1e38a4 | 1222 | fence_put(bo_va->last_pt_update); |
d38ceaf9 AD |
1223 | kfree(bo_va); |
1224 | ||
1225 | mutex_unlock(&vm->mutex); | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1230 | * | |
1231 | * @adev: amdgpu_device pointer | |
1232 | * @vm: requested vm | |
1233 | * @bo: amdgpu buffer object | |
1234 | * | |
1235 | * Mark @bo as invalid (cayman+). | |
1236 | */ | |
1237 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1238 | struct amdgpu_bo *bo) | |
1239 | { | |
1240 | struct amdgpu_bo_va *bo_va; | |
1241 | ||
1242 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1243 | spin_lock(&bo_va->vm->status_lock); |
1244 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1245 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1246 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1247 | } |
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * amdgpu_vm_init - initialize a vm instance | |
1252 | * | |
1253 | * @adev: amdgpu_device pointer | |
1254 | * @vm: requested vm | |
1255 | * | |
1256 | * Init @vm fields (cayman+). | |
1257 | */ | |
1258 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1259 | { | |
1260 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1261 | AMDGPU_VM_PTE_COUNT * 8); | |
1262 | unsigned pd_size, pd_entries, pts_size; | |
1263 | int i, r; | |
1264 | ||
1265 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1266 | vm->ids[i].id = 0; | |
1267 | vm->ids[i].flushed_updates = NULL; | |
1268 | vm->ids[i].last_id_use = NULL; | |
1269 | } | |
1270 | mutex_init(&vm->mutex); | |
1271 | vm->va = RB_ROOT; | |
1272 | spin_lock_init(&vm->status_lock); | |
1273 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1274 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 AD |
1275 | INIT_LIST_HEAD(&vm->freed); |
1276 | ||
1277 | pd_size = amdgpu_vm_directory_size(adev); | |
1278 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1279 | ||
1280 | /* allocate page table array */ | |
1281 | pts_size = pd_entries * sizeof(struct amdgpu_vm_pt); | |
1282 | vm->page_tables = kzalloc(pts_size, GFP_KERNEL); | |
1283 | if (vm->page_tables == NULL) { | |
1284 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1285 | return -ENOMEM; | |
1286 | } | |
1287 | ||
05906dec BN |
1288 | vm->page_directory_fence = NULL; |
1289 | ||
d38ceaf9 | 1290 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1291 | AMDGPU_GEM_DOMAIN_VRAM, |
1292 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1293 | NULL, NULL, &vm->page_directory); |
d38ceaf9 AD |
1294 | if (r) |
1295 | return r; | |
1296 | ||
1297 | r = amdgpu_vm_clear_bo(adev, vm->page_directory); | |
1298 | if (r) { | |
1299 | amdgpu_bo_unref(&vm->page_directory); | |
1300 | vm->page_directory = NULL; | |
1301 | return r; | |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | /** | |
1308 | * amdgpu_vm_fini - tear down a vm instance | |
1309 | * | |
1310 | * @adev: amdgpu_device pointer | |
1311 | * @vm: requested vm | |
1312 | * | |
1313 | * Tear down @vm (cayman+). | |
1314 | * Unbind the VM and remove all bos from the vm bo list | |
1315 | */ | |
1316 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1317 | { | |
1318 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1319 | int i; | |
1320 | ||
1321 | if (!RB_EMPTY_ROOT(&vm->va)) { | |
1322 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1323 | } | |
1324 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1325 | list_del(&mapping->list); | |
1326 | interval_tree_remove(&mapping->it, &vm->va); | |
1327 | kfree(mapping); | |
1328 | } | |
1329 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1330 | list_del(&mapping->list); | |
1331 | kfree(mapping); | |
1332 | } | |
1333 | ||
1334 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
1335 | amdgpu_bo_unref(&vm->page_tables[i].bo); | |
1336 | kfree(vm->page_tables); | |
1337 | ||
1338 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1339 | fence_put(vm->page_directory_fence); |
d38ceaf9 AD |
1340 | |
1341 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
3c62338c | 1342 | fence_put(vm->ids[i].flushed_updates); |
d38ceaf9 AD |
1343 | amdgpu_fence_unref(&vm->ids[i].last_id_use); |
1344 | } | |
1345 | ||
1346 | mutex_destroy(&vm->mutex); | |
1347 | } |