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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / atombios_dp.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/amdgpu_drm.h>
29#include "amdgpu.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_atombios.h"
37#include <drm/drm_dp_helper.h>
38
39/* move these to drm_dp_helper.c/h */
40#define DP_LINK_CONFIGURATION_SIZE 9
41#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
42
43static char *voltage_names[] = {
44 "0.4V", "0.6V", "0.8V", "1.2V"
45};
46static char *pre_emph_names[] = {
47 "0dB", "3.5dB", "6dB", "9.5dB"
48};
49
50/***** amdgpu AUX functions *****/
51
52union aux_channel_transaction {
53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
55};
56
57static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
58 u8 *send, int send_bytes,
59 u8 *recv, int recv_size,
60 u8 delay, u8 *ack)
61{
62 struct drm_device *dev = chan->dev;
63 struct amdgpu_device *adev = dev->dev_private;
64 union aux_channel_transaction args;
65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
66 unsigned char *base;
67 int recv_bytes;
68 int r = 0;
69
70 memset(&args, 0, sizeof(args));
71
72 mutex_lock(&chan->mutex);
73
74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
75
76 amdgpu_atombios_copy_swap(base, send, send_bytes, true);
77
78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
80 args.v2.ucDataOutLen = 0;
81 args.v2.ucChannelID = chan->rec.i2c_id;
82 args.v2.ucDelay = delay / 10;
83 args.v2.ucHPD_ID = chan->rec.hpd;
84
85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
86
87 *ack = args.v2.ucReplyStatus;
88
89 /* timeout */
90 if (args.v2.ucReplyStatus == 1) {
91 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
92 r = -ETIMEDOUT;
93 goto done;
94 }
95
96 /* flags not zero */
97 if (args.v2.ucReplyStatus == 2) {
98 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
99 r = -EIO;
100 goto done;
101 }
102
103 /* error */
104 if (args.v2.ucReplyStatus == 3) {
105 DRM_DEBUG_KMS("dp_aux_ch error\n");
106 r = -EIO;
107 goto done;
108 }
109
110 recv_bytes = args.v1.ucDataOutLen;
111 if (recv_bytes > recv_size)
112 recv_bytes = recv_size;
113
114 if (recv && recv_size)
115 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
116
117 r = recv_bytes;
118done:
119 mutex_unlock(&chan->mutex);
120
121 return r;
122}
123
124#define BARE_ADDRESS_SIZE 3
125#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
126
127static ssize_t
128amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
129{
130 struct amdgpu_i2c_chan *chan =
131 container_of(aux, struct amdgpu_i2c_chan, aux);
132 int ret;
133 u8 tx_buf[20];
134 size_t tx_size;
135 u8 ack, delay = 0;
136
137 if (WARN_ON(msg->size > 16))
138 return -E2BIG;
139
140 tx_buf[0] = msg->address & 0xff;
141 tx_buf[1] = msg->address >> 8;
e39daf2c
AD		 142 tx_buf[2] = (msg->request << 4) |
143 ((msg->address >> 16) & 0xf);
d38ceaf9
AD		 144 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
145
146 switch (msg->request & ~DP_AUX_I2C_MOT) {
147 case DP_AUX_NATIVE_WRITE:
148 case DP_AUX_I2C_WRITE:
149 /* tx_size needs to be 4 even for bare address packets since the atom
150 * table needs the info in tx_buf[3].
151 */
152 tx_size = HEADER_SIZE + msg->size;
153 if (msg->size == 0)
154 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
155 else
156 tx_buf[3] |= tx_size << 4;
157 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
158 ret = amdgpu_atombios_dp_process_aux_ch(chan,
159 tx_buf, tx_size, NULL, 0, delay, &ack);
160 if (ret >= 0)
161 /* Return payload size. */
162 ret = msg->size;
163 break;
164 case DP_AUX_NATIVE_READ:
165 case DP_AUX_I2C_READ:
166 /* tx_size needs to be 4 even for bare address packets since the atom
167 * table needs the info in tx_buf[3].
168 */
169 tx_size = HEADER_SIZE;
170 if (msg->size == 0)
171 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
172 else
173 tx_buf[3] |= tx_size << 4;
174 ret = amdgpu_atombios_dp_process_aux_ch(chan,
175 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
176 break;
177 default:
178 ret = -EINVAL;
179 break;
180 }
181
182 if (ret >= 0)
183 msg->reply = ack >> 4;
184
185 return ret;
186}
187
188void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
189{
190 int ret;
191
192 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
193 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
194 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
195 ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
196 if (!ret)
197 amdgpu_connector->ddc_bus->has_aux = true;
198
199 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
200}
201
202/***** general DP utility functions *****/
203
204#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
205#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
206
dc5f428d
AD		 207static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
208 int lane_count,
209 u8 train_set[4])
d38ceaf9
AD		 210{
211 u8 v = 0;
212 u8 p = 0;
213 int lane;
214
215 for (lane = 0; lane < lane_count; lane++) {
216 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
217 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
218
219 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
220 lane,
221 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
222 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
223
224 if (this_v > v)
225 v = this_v;
226 if (this_p > p)
227 p = this_p;
228 }
229
230 if (v >= DP_VOLTAGE_MAX)
231 v |= DP_TRAIN_MAX_SWING_REACHED;
232
233 if (p >= DP_PRE_EMPHASIS_MAX)
234 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
235
236 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
237 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
238 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
239
240 for (lane = 0; lane < 4; lane++)
241 train_set[lane] = v | p;
242}
243
244/* convert bits per color to bits per pixel */
245/* get bpc from the EDID */
246static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
247{
248 if (bpc == 0)
249 return 24;
250 else
251 return bpc * 3;
252}
253
254/* get the max pix clock supported by the link rate and lane num */
255static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate,
256 int lane_num,
257 int bpp)
258{
259 return (link_rate * lane_num * 8) / bpp;
260}
261
262/***** amdgpu specific DP functions *****/
263
264/* First get the min lane# when low rate is used according to pixel clock
265 * (prefer low rate), second check max lane# supported by DP panel,
266 * if the max lane# < low rate lane# then use max lane# instead.
267 */
268static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector,
dc5f428d
AD		 269 const u8 dpcd[DP_DPCD_SIZE],
270 int pix_clock)
d38ceaf9
AD		 271{
272 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
273 int max_link_rate = drm_dp_max_link_rate(dpcd);
274 int max_lane_num = drm_dp_max_lane_count(dpcd);
275 int lane_num;
276 int max_dp_pix_clock;
277
278 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
279 max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
280 if (pix_clock <= max_dp_pix_clock)
281 break;
282 }
283
284 return lane_num;
285}
286
287static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector,
dc5f428d
AD		 288 const u8 dpcd[DP_DPCD_SIZE],
289 int pix_clock)
d38ceaf9
AD		 290{
291 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
292 int lane_num, max_pix_clock;
293
294 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
295 ENCODER_OBJECT_ID_NUTMEG)
296 return 270000;
297
298 lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock);
299 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp);
300 if (pix_clock <= max_pix_clock)
301 return 162000;
302 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp);
303 if (pix_clock <= max_pix_clock)
304 return 270000;
305 if (amdgpu_connector_is_dp12_capable(connector)) {
306 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp);
307 if (pix_clock <= max_pix_clock)
308 return 540000;
309 }
310
311 return drm_dp_max_link_rate(dpcd);
312}
313
314static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
315 int action, int dp_clock,
316 u8 ucconfig, u8 lane_num)
317{
318 DP_ENCODER_SERVICE_PARAMETERS args;
319 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
320
321 memset(&args, 0, sizeof(args));
322 args.ucLinkClock = dp_clock / 10;
323 args.ucConfig = ucconfig;
324 args.ucAction = action;
325 args.ucLaneNum = lane_num;
326 args.ucStatus = 0;
327
328 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
329 return args.ucStatus;
330}
331
332u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
333{
334 struct drm_device *dev = amdgpu_connector->base.dev;
335 struct amdgpu_device *adev = dev->dev_private;
336
337 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
338 amdgpu_connector->ddc_bus->rec.i2c_id, 0);
339}
340
341static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
342{
343 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
344 u8 buf[3];
345
346 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
347 return;
348
349 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
350 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
351 buf[0], buf[1], buf[2]);
352
353 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
354 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
355 buf[0], buf[1], buf[2]);
356}
357
358int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
359{
360 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
361 u8 msg[DP_DPCD_SIZE];
67ed0092 362 int ret, i;
d38ceaf9 363
67ed0092
AD		 364 for (i = 0; i < 7; i++) {
365 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg,
366 DP_DPCD_SIZE);
367 if (ret == DP_DPCD_SIZE) {
368 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
7af93b50 369
67ed0092
AD		 370 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
371 dig_connector->dpcd);
d38ceaf9 372
67ed0092 373 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
d38ceaf9 374
67ed0092
AD		 375 return 0;
376 }
d38ceaf9
AD		 377 }
378 dig_connector->dpcd[0] = 0;
379 return -EINVAL;
380}
381
382int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
383 struct drm_connector *connector)
384{
385 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
386 struct amdgpu_connector_atom_dig *dig_connector;
387 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
388 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
389 u8 tmp;
390
391 if (!amdgpu_connector->con_priv)
392 return panel_mode;
393
394 dig_connector = amdgpu_connector->con_priv;
395
396 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
397 /* DP bridge chips */
398 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
399 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
400 if (tmp & 1)
401 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
402 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
403 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
404 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
405 else
406 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
407 }
408 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
409 /* eDP */
410 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
411 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
412 if (tmp & 1)
413 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
414 }
415 }
416
417 return panel_mode;
418}
419
420void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
421 const struct drm_display_mode *mode)
422{
423 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
424 struct amdgpu_connector_atom_dig *dig_connector;
425
426 if (!amdgpu_connector->con_priv)
427 return;
428 dig_connector = amdgpu_connector->con_priv;
429
430 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
431 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
432 dig_connector->dp_clock =
433 amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
434 dig_connector->dp_lane_count =
435 amdgpu_atombios_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
436 }
437}
438
439int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
440 struct drm_display_mode *mode)
441{
442 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
443 struct amdgpu_connector_atom_dig *dig_connector;
444 int dp_clock;
445
446 if (!amdgpu_connector->con_priv)
447 return MODE_CLOCK_HIGH;
448 dig_connector = amdgpu_connector->con_priv;
449
450 dp_clock =
451 amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
452
453 if ((dp_clock == 540000) &&
454 (!amdgpu_connector_is_dp12_capable(connector)))
455 return MODE_CLOCK_HIGH;
456
457 return MODE_OK;
458}
459
460bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
461{
462 u8 link_status[DP_LINK_STATUS_SIZE];
463 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
464
465 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
466 <= 0)
467 return false;
468 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
469 return false;
470 return true;
471}
472
473void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
474 u8 power_state)
475{
476 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
477 struct amdgpu_connector_atom_dig *dig_connector;
478
479 if (!amdgpu_connector->con_priv)
480 return;
481
482 dig_connector = amdgpu_connector->con_priv;
483
484 /* power up/down the sink */
485 if (dig_connector->dpcd[0] >= 0x11) {
486 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
487 DP_SET_POWER, power_state);
488 usleep_range(1000, 2000);
489 }
490}
491
492struct amdgpu_atombios_dp_link_train_info {
493 struct amdgpu_device *adev;
494 struct drm_encoder *encoder;
495 struct drm_connector *connector;
496 int dp_clock;
497 int dp_lane_count;
498 bool tp3_supported;
499 u8 dpcd[DP_RECEIVER_CAP_SIZE];
500 u8 train_set[4];
501 u8 link_status[DP_LINK_STATUS_SIZE];
502 u8 tries;
503 struct drm_dp_aux *aux;
504};
505
506static void
507amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
508{
509 /* set the initial vs/emph on the source */
510 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
511 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
512 0, dp_info->train_set[0]); /* sets all lanes at once */
513
514 /* set the vs/emph on the sink */
515 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
516 dp_info->train_set, dp_info->dp_lane_count);
517}
518
519static void
520amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
521{
522 int rtp = 0;
523
524 /* set training pattern on the source */
525 switch (tp) {
526 case DP_TRAINING_PATTERN_1:
527 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
528 break;
529 case DP_TRAINING_PATTERN_2:
530 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
531 break;
532 case DP_TRAINING_PATTERN_3:
533 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
534 break;
535 }
536 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
537
538 /* enable training pattern on the sink */
539 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
540}
541
542static int
543amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
544{
545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
547 u8 tmp;
548
549 /* power up the sink */
550 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
551
552 /* possibly enable downspread on the sink */
553 if (dp_info->dpcd[3] & 0x1)
554 drm_dp_dpcd_writeb(dp_info->aux,
555 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
556 else
557 drm_dp_dpcd_writeb(dp_info->aux,
558 DP_DOWNSPREAD_CTRL, 0);
559
560 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
561 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
562
563 /* set the lane count on the sink */
564 tmp = dp_info->dp_lane_count;
565 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
566 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
567 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
568
569 /* set the link rate on the sink */
570 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
571 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
572
573 /* start training on the source */
574 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
575 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
576
577 /* disable the training pattern on the sink */
578 drm_dp_dpcd_writeb(dp_info->aux,
579 DP_TRAINING_PATTERN_SET,
580 DP_TRAINING_PATTERN_DISABLE);
581
582 return 0;
583}
584
585static int
586amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
587{
588 udelay(400);
589
590 /* disable the training pattern on the sink */
591 drm_dp_dpcd_writeb(dp_info->aux,
592 DP_TRAINING_PATTERN_SET,
593 DP_TRAINING_PATTERN_DISABLE);
594
595 /* disable the training pattern on the source */
596 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
597 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
598
599 return 0;
600}
601
602static int
603amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
604{
605 bool clock_recovery;
606 u8 voltage;
607 int i;
608
609 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
610 memset(dp_info->train_set, 0, 4);
611 amdgpu_atombios_dp_update_vs_emph(dp_info);
612
613 udelay(400);
614
615 /* clock recovery loop */
616 clock_recovery = false;
617 dp_info->tries = 0;
618 voltage = 0xff;
619 while (1) {
620 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
621
622 if (drm_dp_dpcd_read_link_status(dp_info->aux,
623 dp_info->link_status) <= 0) {
624 DRM_ERROR("displayport link status failed\n");
625 break;
626 }
627
628 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
629 clock_recovery = true;
630 break;
631 }
632
633 for (i = 0; i < dp_info->dp_lane_count; i++) {
634 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
635 break;
636 }
637 if (i == dp_info->dp_lane_count) {
638 DRM_ERROR("clock recovery reached max voltage\n");
639 break;
640 }
641
642 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
643 ++dp_info->tries;
644 if (dp_info->tries == 5) {
645 DRM_ERROR("clock recovery tried 5 times\n");
646 break;
647 }
648 } else
649 dp_info->tries = 0;
650
651 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
652
653 /* Compute new train_set as requested by sink */
654 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
655 dp_info->train_set);
656
657 amdgpu_atombios_dp_update_vs_emph(dp_info);
658 }
659 if (!clock_recovery) {
660 DRM_ERROR("clock recovery failed\n");
661 return -1;
662 } else {
663 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
664 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
665 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
666 DP_TRAIN_PRE_EMPHASIS_SHIFT);
667 return 0;
668 }
669}
670
671static int
672amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
673{
674 bool channel_eq;
675
676 if (dp_info->tp3_supported)
677 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
678 else
679 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
680
681 /* channel equalization loop */
682 dp_info->tries = 0;
683 channel_eq = false;
684 while (1) {
685 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
686
687 if (drm_dp_dpcd_read_link_status(dp_info->aux,
688 dp_info->link_status) <= 0) {
689 DRM_ERROR("displayport link status failed\n");
690 break;
691 }
692
693 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
694 channel_eq = true;
695 break;
696 }
697
698 /* Try 5 times */
699 if (dp_info->tries > 5) {
700 DRM_ERROR("channel eq failed: 5 tries\n");
701 break;
702 }
703
704 /* Compute new train_set as requested by sink */
705 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
706 dp_info->train_set);
707
708 amdgpu_atombios_dp_update_vs_emph(dp_info);
709 dp_info->tries++;
710 }
711
712 if (!channel_eq) {
713 DRM_ERROR("channel eq failed\n");
714 return -1;
715 } else {
716 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
717 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
718 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
719 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
720 return 0;
721 }
722}
723
724void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
725 struct drm_connector *connector)
726{
727 struct drm_device *dev = encoder->dev;
728 struct amdgpu_device *adev = dev->dev_private;
729 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
730 struct amdgpu_encoder_atom_dig *dig;
731 struct amdgpu_connector *amdgpu_connector;
732 struct amdgpu_connector_atom_dig *dig_connector;
733 struct amdgpu_atombios_dp_link_train_info dp_info;
734 u8 tmp;
735
736 if (!amdgpu_encoder->enc_priv)
737 return;
738 dig = amdgpu_encoder->enc_priv;
739
740 amdgpu_connector = to_amdgpu_connector(connector);
741 if (!amdgpu_connector->con_priv)
742 return;
743 dig_connector = amdgpu_connector->con_priv;
744
745 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
746 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
747 return;
748
749 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
750 == 1) {
751 if (tmp & DP_TPS3_SUPPORTED)
752 dp_info.tp3_supported = true;
753 else
754 dp_info.tp3_supported = false;
755 } else {
756 dp_info.tp3_supported = false;
757 }
758
759 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
760 dp_info.adev = adev;
761 dp_info.encoder = encoder;
762 dp_info.connector = connector;
763 dp_info.dp_lane_count = dig_connector->dp_lane_count;
764 dp_info.dp_clock = dig_connector->dp_clock;
765 dp_info.aux = &amdgpu_connector->ddc_bus->aux;
766
767 if (amdgpu_atombios_dp_link_train_init(&dp_info))
768 goto done;
769 if (amdgpu_atombios_dp_link_train_cr(&dp_info))
770 goto done;
771 if (amdgpu_atombios_dp_link_train_ce(&dp_info))
772 goto done;
773done:
774 if (amdgpu_atombios_dp_link_train_finish(&dp_info))
775 return;
776}
Linux kernel - Deliverables
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