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drm/amdgpu: make the CTX ioctl thread-safe
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
36
37#include "gmc/gmc_7_1_d.h"
38#include "gmc/gmc_7_1_sh_mask.h"
39
40#include "oss/oss_2_0_d.h"
41#include "oss/oss_2_0_sh_mask.h"
42
43static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
44{
45 SDMA0_REGISTER_OFFSET,
46 SDMA1_REGISTER_OFFSET
47};
48
49static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
50static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
51static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
53
54MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
55MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
56MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
57MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
58MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
59MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
60MODULE_FIRMWARE("radeon/kabini_sdma.bin");
61MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
62MODULE_FIRMWARE("radeon/mullins_sdma.bin");
63MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
64
65u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
66
67/*
68 * sDMA - System DMA
69 * Starting with CIK, the GPU has new asynchronous
70 * DMA engines. These engines are used for compute
71 * and gfx. There are two DMA engines (SDMA0, SDMA1)
72 * and each one supports 1 ring buffer used for gfx
73 * and 2 queues used for compute.
74 *
75 * The programming model is very similar to the CP
76 * (ring buffer, IBs, etc.), but sDMA has it's own
77 * packet format that is different from the PM4 format
78 * used by the CP. sDMA supports copying data, writing
79 * embedded data, solid fills, and a number of other
80 * things. It also has support for tiling/detiling of
81 * buffers.
82 */
83
84/**
85 * cik_sdma_init_microcode - load ucode images from disk
86 *
87 * @adev: amdgpu_device pointer
88 *
89 * Use the firmware interface to load the ucode images into
90 * the driver (not loaded into hw).
91 * Returns 0 on success, error on failure.
92 */
93static int cik_sdma_init_microcode(struct amdgpu_device *adev)
94{
95 const char *chip_name;
96 char fw_name[30];
97 int err, i;
98
99 DRM_DEBUG("\n");
100
101 switch (adev->asic_type) {
102 case CHIP_BONAIRE:
103 chip_name = "bonaire";
104 break;
105 case CHIP_HAWAII:
106 chip_name = "hawaii";
107 break;
108 case CHIP_KAVERI:
109 chip_name = "kaveri";
110 break;
111 case CHIP_KABINI:
112 chip_name = "kabini";
113 break;
114 case CHIP_MULLINS:
115 chip_name = "mullins";
116 break;
117 default: BUG();
118 }
119
120 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
121 if (i == 0)
122 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
123 else
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
125 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
126 if (err)
127 goto out;
128 err = amdgpu_ucode_validate(adev->sdma[i].fw);
129 }
130out:
131 if (err) {
132 printk(KERN_ERR
133 "cik_sdma: Failed to load firmware \"%s\"\n",
134 fw_name);
135 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
136 release_firmware(adev->sdma[i].fw);
137 adev->sdma[i].fw = NULL;
138 }
139 }
140 return err;
141}
142
143/**
144 * cik_sdma_ring_get_rptr - get the current read pointer
145 *
146 * @ring: amdgpu ring pointer
147 *
148 * Get the current rptr from the hardware (CIK+).
149 */
150static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
151{
152 u32 rptr;
153
154 rptr = ring->adev->wb.wb[ring->rptr_offs];
155
156 return (rptr & 0x3fffc) >> 2;
157}
158
159/**
160 * cik_sdma_ring_get_wptr - get the current write pointer
161 *
162 * @ring: amdgpu ring pointer
163 *
164 * Get the current wptr from the hardware (CIK+).
165 */
166static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
167{
168 struct amdgpu_device *adev = ring->adev;
169 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
170
171 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
172}
173
174/**
175 * cik_sdma_ring_set_wptr - commit the write pointer
176 *
177 * @ring: amdgpu ring pointer
178 *
179 * Write the wptr back to the hardware (CIK+).
180 */
181static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
182{
183 struct amdgpu_device *adev = ring->adev;
184 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
185
186 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
187}
188
189static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *);
190
191/**
192 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
193 *
194 * @ring: amdgpu ring pointer
195 * @ib: IB object to schedule
196 *
197 * Schedule an IB in the DMA ring (CIK).
198 */
199static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
200 struct amdgpu_ib *ib)
201{
202 u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
203 u32 next_rptr = ring->wptr + 5;
204
205 if (ib->flush_hdp_writefifo)
206 next_rptr += 6;
207
208 while ((next_rptr & 7) != 4)
209 next_rptr++;
210
211 next_rptr += 4;
212 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
213 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
214 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
215 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
216 amdgpu_ring_write(ring, next_rptr);
217
218 if (ib->flush_hdp_writefifo) {
219 /* flush HDP */
220 cik_sdma_hdp_flush_ring_emit(ring);
221 }
222
223 /* IB packet must end on a 8 DW boundary */
224 while ((ring->wptr & 7) != 4)
225 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
226 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
227 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
228 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
229 amdgpu_ring_write(ring, ib->length_dw);
230
231}
232
233/**
234 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
235 *
236 * @ring: amdgpu ring pointer
237 *
238 * Emit an hdp flush packet on the requested DMA ring.
239 */
240static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring)
241{
242 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
243 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
244 u32 ref_and_mask;
245
246 if (ring == &ring->adev->sdma[0].ring)
247 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
248 else
249 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
250
251 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
252 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
253 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
254 amdgpu_ring_write(ring, ref_and_mask); /* reference */
255 amdgpu_ring_write(ring, ref_and_mask); /* mask */
256 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
257}
258
259/**
260 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
261 *
262 * @ring: amdgpu ring pointer
263 * @fence: amdgpu fence object
264 *
265 * Add a DMA fence packet to the ring to write
266 * the fence seq number and DMA trap packet to generate
267 * an interrupt if needed (CIK).
268 */
269static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
270 bool write64bit)
271{
272 /* write the fence */
273 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
274 amdgpu_ring_write(ring, lower_32_bits(addr));
275 amdgpu_ring_write(ring, upper_32_bits(addr));
276 amdgpu_ring_write(ring, lower_32_bits(seq));
277
278 /* optionally write high bits as well */
279 if (write64bit) {
280 addr += 4;
281 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
282 amdgpu_ring_write(ring, lower_32_bits(addr));
283 amdgpu_ring_write(ring, upper_32_bits(addr));
284 amdgpu_ring_write(ring, upper_32_bits(seq));
285 }
286
287 /* generate an interrupt */
288 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
289}
290
291/**
292 * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
293 *
294 * @ring: amdgpu_ring structure holding ring information
295 * @semaphore: amdgpu semaphore object
296 * @emit_wait: wait or signal semaphore
297 *
298 * Add a DMA semaphore packet to the ring wait on or signal
299 * other rings (CIK).
300 */
301static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
302 struct amdgpu_semaphore *semaphore,
303 bool emit_wait)
304{
305 u64 addr = semaphore->gpu_addr;
306 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
307
308 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
309 amdgpu_ring_write(ring, addr & 0xfffffff8);
310 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
311
312 return true;
313}
314
315/**
316 * cik_sdma_gfx_stop - stop the gfx async dma engines
317 *
318 * @adev: amdgpu_device pointer
319 *
320 * Stop the gfx async dma ring buffers (CIK).
321 */
322static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
323{
324 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
325 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
326 u32 rb_cntl;
327 int i;
328
329 if ((adev->mman.buffer_funcs_ring == sdma0) ||
330 (adev->mman.buffer_funcs_ring == sdma1))
331 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
332
333 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
334 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
335 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
336 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
337 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
338 }
339 sdma0->ready = false;
340 sdma1->ready = false;
341}
342
343/**
344 * cik_sdma_rlc_stop - stop the compute async dma engines
345 *
346 * @adev: amdgpu_device pointer
347 *
348 * Stop the compute async dma queues (CIK).
349 */
350static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
351{
352 /* XXX todo */
353}
354
355/**
356 * cik_sdma_enable - stop the async dma engines
357 *
358 * @adev: amdgpu_device pointer
359 * @enable: enable/disable the DMA MEs.
360 *
361 * Halt or unhalt the async dma engines (CIK).
362 */
363static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
364{
365 u32 me_cntl;
366 int i;
367
368 if (enable == false) {
369 cik_sdma_gfx_stop(adev);
370 cik_sdma_rlc_stop(adev);
371 }
372
373 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
374 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
375 if (enable)
376 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
377 else
378 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
379 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
380 }
381}
382
383/**
384 * cik_sdma_gfx_resume - setup and start the async dma engines
385 *
386 * @adev: amdgpu_device pointer
387 *
388 * Set up the gfx DMA ring buffers and enable them (CIK).
389 * Returns 0 for success, error for failure.
390 */
391static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
392{
393 struct amdgpu_ring *ring;
394 u32 rb_cntl, ib_cntl;
395 u32 rb_bufsz;
396 u32 wb_offset;
397 int i, j, r;
398
399 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
400 ring = &adev->sdma[i].ring;
401 wb_offset = (ring->rptr_offs * 4);
402
403 mutex_lock(&adev->srbm_mutex);
404 for (j = 0; j < 16; j++) {
405 cik_srbm_select(adev, 0, 0, 0, j);
406 /* SDMA GFX */
407 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
408 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
409 /* XXX SDMA RLC - todo */
410 }
411 cik_srbm_select(adev, 0, 0, 0, 0);
412 mutex_unlock(&adev->srbm_mutex);
413
414 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
415 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
416
417 /* Set ring buffer size in dwords */
418 rb_bufsz = order_base_2(ring->ring_size / 4);
419 rb_cntl = rb_bufsz << 1;
420#ifdef __BIG_ENDIAN
421 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
422#endif
423 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
424
425 /* Initialize the ring buffer's read and write pointers */
426 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
427 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
428
429 /* set the wb address whether it's enabled or not */
430 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
431 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
432 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
433 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
434
435 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
436
437 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
438 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
439
440 ring->wptr = 0;
441 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
442
443 /* enable DMA RB */
444 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
445 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
446
447 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
448#ifdef __BIG_ENDIAN
449 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
450#endif
451 /* enable DMA IBs */
452 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
453
454 ring->ready = true;
455
456 r = amdgpu_ring_test_ring(ring);
457 if (r) {
458 ring->ready = false;
459 return r;
460 }
461
462 if (adev->mman.buffer_funcs_ring == ring)
463 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
464 }
465
466 return 0;
467}
468
469/**
470 * cik_sdma_rlc_resume - setup and start the async dma engines
471 *
472 * @adev: amdgpu_device pointer
473 *
474 * Set up the compute DMA queues and enable them (CIK).
475 * Returns 0 for success, error for failure.
476 */
477static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
478{
479 /* XXX todo */
480 return 0;
481}
482
483/**
484 * cik_sdma_load_microcode - load the sDMA ME ucode
485 *
486 * @adev: amdgpu_device pointer
487 *
488 * Loads the sDMA0/1 ucode.
489 * Returns 0 for success, -EINVAL if the ucode is not available.
490 */
491static int cik_sdma_load_microcode(struct amdgpu_device *adev)
492{
493 const struct sdma_firmware_header_v1_0 *hdr;
494 const __le32 *fw_data;
495 u32 fw_size;
496 int i, j;
497
498 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
499 return -EINVAL;
500
501 /* halt the MEs */
502 cik_sdma_enable(adev, false);
503
504 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
505 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
506 amdgpu_ucode_print_sdma_hdr(&hdr->header);
507 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
508 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
509 fw_data = (const __le32 *)
510 (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
511 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
512 for (j = 0; j < fw_size; j++)
513 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
514 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
515 }
516
517 return 0;
518}
519
520/**
521 * cik_sdma_start - setup and start the async dma engines
522 *
523 * @adev: amdgpu_device pointer
524 *
525 * Set up the DMA engines and enable them (CIK).
526 * Returns 0 for success, error for failure.
527 */
528static int cik_sdma_start(struct amdgpu_device *adev)
529{
530 int r;
531
532 r = cik_sdma_load_microcode(adev);
533 if (r)
534 return r;
535
536 /* unhalt the MEs */
537 cik_sdma_enable(adev, true);
538
539 /* start the gfx rings and rlc compute queues */
540 r = cik_sdma_gfx_resume(adev);
541 if (r)
542 return r;
543 r = cik_sdma_rlc_resume(adev);
544 if (r)
545 return r;
546
547 return 0;
548}
549
550/**
551 * cik_sdma_ring_test_ring - simple async dma engine test
552 *
553 * @ring: amdgpu_ring structure holding ring information
554 *
555 * Test the DMA engine by writing using it to write an
556 * value to memory. (CIK).
557 * Returns 0 for success, error for failure.
558 */
559static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
560{
561 struct amdgpu_device *adev = ring->adev;
562 unsigned i;
563 unsigned index;
564 int r;
565 u32 tmp;
566 u64 gpu_addr;
567
568 r = amdgpu_wb_get(adev, &index);
569 if (r) {
570 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
571 return r;
572 }
573
574 gpu_addr = adev->wb.gpu_addr + (index * 4);
575 tmp = 0xCAFEDEAD;
576 adev->wb.wb[index] = cpu_to_le32(tmp);
577
578 r = amdgpu_ring_lock(ring, 5);
579 if (r) {
580 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
581 amdgpu_wb_free(adev, index);
582 return r;
583 }
584 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
585 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
586 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
587 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
588 amdgpu_ring_write(ring, 0xDEADBEEF);
589 amdgpu_ring_unlock_commit(ring);
590
591 for (i = 0; i < adev->usec_timeout; i++) {
592 tmp = le32_to_cpu(adev->wb.wb[index]);
593 if (tmp == 0xDEADBEEF)
594 break;
595 DRM_UDELAY(1);
596 }
597
598 if (i < adev->usec_timeout) {
599 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
600 } else {
601 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
602 ring->idx, tmp);
603 r = -EINVAL;
604 }
605 amdgpu_wb_free(adev, index);
606
607 return r;
608}
609
610/**
611 * cik_sdma_ring_test_ib - test an IB on the DMA engine
612 *
613 * @ring: amdgpu_ring structure holding ring information
614 *
615 * Test a simple IB in the DMA ring (CIK).
616 * Returns 0 on success, error on failure.
617 */
618static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
619{
620 struct amdgpu_device *adev = ring->adev;
621 struct amdgpu_ib ib;
622 unsigned i;
623 unsigned index;
624 int r;
625 u32 tmp = 0;
626 u64 gpu_addr;
627
628 r = amdgpu_wb_get(adev, &index);
629 if (r) {
630 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
631 return r;
632 }
633
634 gpu_addr = adev->wb.gpu_addr + (index * 4);
635 tmp = 0xCAFEDEAD;
636 adev->wb.wb[index] = cpu_to_le32(tmp);
637
638 r = amdgpu_ib_get(ring, NULL, 256, &ib);
639 if (r) {
640 amdgpu_wb_free(adev, index);
641 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
642 return r;
643 }
644
645 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
646 ib.ptr[1] = lower_32_bits(gpu_addr);
647 ib.ptr[2] = upper_32_bits(gpu_addr);
648 ib.ptr[3] = 1;
649 ib.ptr[4] = 0xDEADBEEF;
650 ib.length_dw = 5;
651
652 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
653 if (r) {
654 amdgpu_ib_free(adev, &ib);
655 amdgpu_wb_free(adev, index);
656 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
657 return r;
658 }
659 r = amdgpu_fence_wait(ib.fence, false);
660 if (r) {
661 amdgpu_ib_free(adev, &ib);
662 amdgpu_wb_free(adev, index);
663 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
664 return r;
665 }
666 for (i = 0; i < adev->usec_timeout; i++) {
667 tmp = le32_to_cpu(adev->wb.wb[index]);
668 if (tmp == 0xDEADBEEF)
669 break;
670 DRM_UDELAY(1);
671 }
672 if (i < adev->usec_timeout) {
673 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
674 ib.fence->ring->idx, i);
675 } else {
676 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
677 r = -EINVAL;
678 }
679 amdgpu_ib_free(adev, &ib);
680 amdgpu_wb_free(adev, index);
681 return r;
682}
683
684/**
685 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
686 *
687 * @ib: indirect buffer to fill with commands
688 * @pe: addr of the page entry
689 * @src: src addr to copy from
690 * @count: number of page entries to update
691 *
692 * Update PTEs by copying them from the GART using sDMA (CIK).
693 */
694static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
695 uint64_t pe, uint64_t src,
696 unsigned count)
697{
698 while (count) {
699 unsigned bytes = count * 8;
700 if (bytes > 0x1FFFF8)
701 bytes = 0x1FFFF8;
702
703 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
704 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
705 ib->ptr[ib->length_dw++] = bytes;
706 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
707 ib->ptr[ib->length_dw++] = lower_32_bits(src);
708 ib->ptr[ib->length_dw++] = upper_32_bits(src);
709 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
710 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
711
712 pe += bytes;
713 src += bytes;
714 count -= bytes / 8;
715 }
716}
717
718/**
719 * cik_sdma_vm_write_pages - update PTEs by writing them manually
720 *
721 * @ib: indirect buffer to fill with commands
722 * @pe: addr of the page entry
723 * @addr: dst addr to write into pe
724 * @count: number of page entries to update
725 * @incr: increase next addr by incr bytes
726 * @flags: access flags
727 *
728 * Update PTEs by writing them manually using sDMA (CIK).
729 */
730static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
731 uint64_t pe,
732 uint64_t addr, unsigned count,
733 uint32_t incr, uint32_t flags)
734{
735 uint64_t value;
736 unsigned ndw;
737
738 while (count) {
739 ndw = count * 2;
740 if (ndw > 0xFFFFE)
741 ndw = 0xFFFFE;
742
743 /* for non-physically contiguous pages (system) */
744 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
745 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
746 ib->ptr[ib->length_dw++] = pe;
747 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
748 ib->ptr[ib->length_dw++] = ndw;
749 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
750 if (flags & AMDGPU_PTE_SYSTEM) {
751 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
752 value &= 0xFFFFFFFFFFFFF000ULL;
753 } else if (flags & AMDGPU_PTE_VALID) {
754 value = addr;
755 } else {
756 value = 0;
757 }
758 addr += incr;
759 value |= flags;
760 ib->ptr[ib->length_dw++] = value;
761 ib->ptr[ib->length_dw++] = upper_32_bits(value);
762 }
763 }
764}
765
766/**
767 * cik_sdma_vm_set_pages - update the page tables using sDMA
768 *
769 * @ib: indirect buffer to fill with commands
770 * @pe: addr of the page entry
771 * @addr: dst addr to write into pe
772 * @count: number of page entries to update
773 * @incr: increase next addr by incr bytes
774 * @flags: access flags
775 *
776 * Update the page tables using sDMA (CIK).
777 */
778static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
779 uint64_t pe,
780 uint64_t addr, unsigned count,
781 uint32_t incr, uint32_t flags)
782{
783 uint64_t value;
784 unsigned ndw;
785
786 while (count) {
787 ndw = count;
788 if (ndw > 0x7FFFF)
789 ndw = 0x7FFFF;
790
791 if (flags & AMDGPU_PTE_VALID)
792 value = addr;
793 else
794 value = 0;
795
796 /* for physically contiguous pages (vram) */
797 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
798 ib->ptr[ib->length_dw++] = pe; /* dst addr */
799 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
800 ib->ptr[ib->length_dw++] = flags; /* mask */
801 ib->ptr[ib->length_dw++] = 0;
802 ib->ptr[ib->length_dw++] = value; /* value */
803 ib->ptr[ib->length_dw++] = upper_32_bits(value);
804 ib->ptr[ib->length_dw++] = incr; /* increment size */
805 ib->ptr[ib->length_dw++] = 0;
806 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
807
808 pe += ndw * 8;
809 addr += ndw * incr;
810 count -= ndw;
811 }
812}
813
814/**
815 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
816 *
817 * @ib: indirect buffer to fill with padding
818 *
819 */
820static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
821{
822 while (ib->length_dw & 0x7)
823 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
824}
825
826/**
827 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
828 *
829 * @ring: amdgpu_ring pointer
830 * @vm: amdgpu_vm pointer
831 *
832 * Update the page table base and flush the VM TLB
833 * using sDMA (CIK).
834 */
835static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
836 unsigned vm_id, uint64_t pd_addr)
837{
838 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
839 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
840
841 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
842 if (vm_id < 8) {
843 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
844 } else {
845 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
846 }
847 amdgpu_ring_write(ring, pd_addr >> 12);
848
849 /* update SH_MEM_* regs */
850 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
851 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
852 amdgpu_ring_write(ring, VMID(vm_id));
853
854 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
855 amdgpu_ring_write(ring, mmSH_MEM_BASES);
856 amdgpu_ring_write(ring, 0);
857
858 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
859 amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
860 amdgpu_ring_write(ring, 0);
861
862 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
863 amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
864 amdgpu_ring_write(ring, 1);
865
866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
867 amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
868 amdgpu_ring_write(ring, 0);
869
870 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
871 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
872 amdgpu_ring_write(ring, VMID(0));
873
874 /* flush TLB */
875 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
876 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
877 amdgpu_ring_write(ring, 1 << vm_id);
878
879 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
880 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
881 amdgpu_ring_write(ring, 0);
882 amdgpu_ring_write(ring, 0); /* reference */
883 amdgpu_ring_write(ring, 0); /* mask */
884 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
885}
886
887static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
888 bool enable)
889{
890 u32 orig, data;
891
892 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
893 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
894 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
895 } else {
896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
897 data |= 0xff000000;
898 if (data != orig)
899 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
900
901 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
902 data |= 0xff000000;
903 if (data != orig)
904 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
905 }
906}
907
908static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
909 bool enable)
910{
911 u32 orig, data;
912
913 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
915 data |= 0x100;
916 if (orig != data)
917 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
918
919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
920 data |= 0x100;
921 if (orig != data)
922 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
923 } else {
924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
925 data &= ~0x100;
926 if (orig != data)
927 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
928
929 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
930 data &= ~0x100;
931 if (orig != data)
932 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
933 }
934}
935
936static int cik_sdma_early_init(struct amdgpu_device *adev)
937{
938 cik_sdma_set_ring_funcs(adev);
939 cik_sdma_set_irq_funcs(adev);
940 cik_sdma_set_buffer_funcs(adev);
941 cik_sdma_set_vm_pte_funcs(adev);
942
943 return 0;
944}
945
946static int cik_sdma_sw_init(struct amdgpu_device *adev)
947{
948 struct amdgpu_ring *ring;
949 int r;
950
951 r = cik_sdma_init_microcode(adev);
952 if (r) {
953 DRM_ERROR("Failed to load sdma firmware!\n");
954 return r;
955 }
956
957 /* SDMA trap event */
958 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
959 if (r)
960 return r;
961
962 /* SDMA Privileged inst */
963 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
964 if (r)
965 return r;
966
967 /* SDMA Privileged inst */
968 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
969 if (r)
970 return r;
971
972 ring = &adev->sdma[0].ring;
973 ring->ring_obj = NULL;
974
975 ring = &adev->sdma[1].ring;
976 ring->ring_obj = NULL;
977
978 ring = &adev->sdma[0].ring;
979 sprintf(ring->name, "sdma0");
980 r = amdgpu_ring_init(adev, ring, 256 * 1024,
981 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
982 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
983 AMDGPU_RING_TYPE_SDMA);
984 if (r)
985 return r;
986
987 ring = &adev->sdma[1].ring;
988 sprintf(ring->name, "sdma1");
989 r = amdgpu_ring_init(adev, ring, 256 * 1024,
990 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
991 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
992 AMDGPU_RING_TYPE_SDMA);
993 if (r)
994 return r;
995
996 return r;
997}
998
999static int cik_sdma_sw_fini(struct amdgpu_device *adev)
1000{
1001 amdgpu_ring_fini(&adev->sdma[0].ring);
1002 amdgpu_ring_fini(&adev->sdma[1].ring);
1003
1004 return 0;
1005}
1006
1007static int cik_sdma_hw_init(struct amdgpu_device *adev)
1008{
1009 int r;
1010
1011 r = cik_sdma_start(adev);
1012 if (r)
1013 return r;
1014
1015 return r;
1016}
1017
1018static int cik_sdma_hw_fini(struct amdgpu_device *adev)
1019{
1020 cik_sdma_enable(adev, false);
1021
1022 return 0;
1023}
1024
1025static int cik_sdma_suspend(struct amdgpu_device *adev)
1026{
1027
1028 return cik_sdma_hw_fini(adev);
1029}
1030
1031static int cik_sdma_resume(struct amdgpu_device *adev)
1032{
1033
1034 return cik_sdma_hw_init(adev);
1035}
1036
1037static bool cik_sdma_is_idle(struct amdgpu_device *adev)
1038{
1039 u32 tmp = RREG32(mmSRBM_STATUS2);
1040
1041 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1042 SRBM_STATUS2__SDMA1_BUSY_MASK))
1043 return false;
1044
1045 return true;
1046}
1047
1048static int cik_sdma_wait_for_idle(struct amdgpu_device *adev)
1049{
1050 unsigned i;
1051 u32 tmp;
1052
1053 for (i = 0; i < adev->usec_timeout; i++) {
1054 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1055 SRBM_STATUS2__SDMA1_BUSY_MASK);
1056
1057 if (!tmp)
1058 return 0;
1059 udelay(1);
1060 }
1061 return -ETIMEDOUT;
1062}
1063
1064static void cik_sdma_print_status(struct amdgpu_device *adev)
1065{
1066 int i, j;
1067
1068 dev_info(adev->dev, "CIK SDMA registers\n");
1069 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1070 RREG32(mmSRBM_STATUS2));
1071 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1072 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1073 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1074 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1075 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1076 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1077 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1098 mutex_lock(&adev->srbm_mutex);
1099 for (j = 0; j < 16; j++) {
1100 cik_srbm_select(adev, 0, 0, 0, j);
1101 dev_info(adev->dev, " VM %d:\n", j);
1102 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1103 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1104 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1105 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1106 }
1107 cik_srbm_select(adev, 0, 0, 0, 0);
1108 mutex_unlock(&adev->srbm_mutex);
1109 }
1110}
1111
1112static int cik_sdma_soft_reset(struct amdgpu_device *adev)
1113{
1114 u32 srbm_soft_reset = 0;
1115 u32 tmp = RREG32(mmSRBM_STATUS2);
1116
1117 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1118 /* sdma0 */
1119 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1120 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1121 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1122 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1123 }
1124 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1125 /* sdma1 */
1126 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1127 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1128 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1129 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1130 }
1131
1132 if (srbm_soft_reset) {
1133 cik_sdma_print_status(adev);
1134
1135 tmp = RREG32(mmSRBM_SOFT_RESET);
1136 tmp |= srbm_soft_reset;
1137 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1138 WREG32(mmSRBM_SOFT_RESET, tmp);
1139 tmp = RREG32(mmSRBM_SOFT_RESET);
1140
1141 udelay(50);
1142
1143 tmp &= ~srbm_soft_reset;
1144 WREG32(mmSRBM_SOFT_RESET, tmp);
1145 tmp = RREG32(mmSRBM_SOFT_RESET);
1146
1147 /* Wait a little for things to settle down */
1148 udelay(50);
1149
1150 cik_sdma_print_status(adev);
1151 }
1152
1153 return 0;
1154}
1155
1156static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1157 struct amdgpu_irq_src *src,
1158 unsigned type,
1159 enum amdgpu_interrupt_state state)
1160{
1161 u32 sdma_cntl;
1162
1163 switch (type) {
1164 case AMDGPU_SDMA_IRQ_TRAP0:
1165 switch (state) {
1166 case AMDGPU_IRQ_STATE_DISABLE:
1167 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1168 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1169 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1170 break;
1171 case AMDGPU_IRQ_STATE_ENABLE:
1172 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1173 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1174 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1175 break;
1176 default:
1177 break;
1178 }
1179 break;
1180 case AMDGPU_SDMA_IRQ_TRAP1:
1181 switch (state) {
1182 case AMDGPU_IRQ_STATE_DISABLE:
1183 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1184 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1185 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1186 break;
1187 case AMDGPU_IRQ_STATE_ENABLE:
1188 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1189 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1190 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1191 break;
1192 default:
1193 break;
1194 }
1195 break;
1196 default:
1197 break;
1198 }
1199 return 0;
1200}
1201
1202static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1203 struct amdgpu_irq_src *source,
1204 struct amdgpu_iv_entry *entry)
1205{
1206 u8 instance_id, queue_id;
1207
1208 instance_id = (entry->ring_id & 0x3) >> 0;
1209 queue_id = (entry->ring_id & 0xc) >> 2;
1210 DRM_DEBUG("IH: SDMA trap\n");
1211 switch (instance_id) {
1212 case 0:
1213 switch (queue_id) {
1214 case 0:
1215 amdgpu_fence_process(&adev->sdma[0].ring);
1216 break;
1217 case 1:
1218 /* XXX compute */
1219 break;
1220 case 2:
1221 /* XXX compute */
1222 break;
1223 }
1224 break;
1225 case 1:
1226 switch (queue_id) {
1227 case 0:
1228 amdgpu_fence_process(&adev->sdma[1].ring);
1229 break;
1230 case 1:
1231 /* XXX compute */
1232 break;
1233 case 2:
1234 /* XXX compute */
1235 break;
1236 }
1237 break;
1238 }
1239
1240 return 0;
1241}
1242
1243static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1244 struct amdgpu_irq_src *source,
1245 struct amdgpu_iv_entry *entry)
1246{
1247 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1248 schedule_work(&adev->reset_work);
1249 return 0;
1250}
1251
1252static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev,
1253 enum amdgpu_clockgating_state state)
1254{
1255 bool gate = false;
1256
1257 if (state == AMDGPU_CG_STATE_GATE)
1258 gate = true;
1259
1260 cik_enable_sdma_mgcg(adev, gate);
1261 cik_enable_sdma_mgls(adev, gate);
1262
1263 return 0;
1264}
1265
1266static int cik_sdma_set_powergating_state(struct amdgpu_device *adev,
1267 enum amdgpu_powergating_state state)
1268{
1269 return 0;
1270}
1271
1272const struct amdgpu_ip_funcs cik_sdma_ip_funcs = {
1273 .early_init = cik_sdma_early_init,
1274 .late_init = NULL,
1275 .sw_init = cik_sdma_sw_init,
1276 .sw_fini = cik_sdma_sw_fini,
1277 .hw_init = cik_sdma_hw_init,
1278 .hw_fini = cik_sdma_hw_fini,
1279 .suspend = cik_sdma_suspend,
1280 .resume = cik_sdma_resume,
1281 .is_idle = cik_sdma_is_idle,
1282 .wait_for_idle = cik_sdma_wait_for_idle,
1283 .soft_reset = cik_sdma_soft_reset,
1284 .print_status = cik_sdma_print_status,
1285 .set_clockgating_state = cik_sdma_set_clockgating_state,
1286 .set_powergating_state = cik_sdma_set_powergating_state,
1287};
1288
1289/**
1290 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1291 *
1292 * @ring: amdgpu_ring structure holding ring information
1293 *
1294 * Check if the async DMA engine is locked up (CIK).
1295 * Returns true if the engine appears to be locked up, false if not.
1296 */
1297static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
1298{
1299
1300 if (cik_sdma_is_idle(ring->adev)) {
1301 amdgpu_ring_lockup_update(ring);
1302 return false;
1303 }
1304 return amdgpu_ring_test_lockup(ring);
1305}
1306
1307static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1308 .get_rptr = cik_sdma_ring_get_rptr,
1309 .get_wptr = cik_sdma_ring_get_wptr,
1310 .set_wptr = cik_sdma_ring_set_wptr,
1311 .parse_cs = NULL,
1312 .emit_ib = cik_sdma_ring_emit_ib,
1313 .emit_fence = cik_sdma_ring_emit_fence,
1314 .emit_semaphore = cik_sdma_ring_emit_semaphore,
1315 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1316 .test_ring = cik_sdma_ring_test_ring,
1317 .test_ib = cik_sdma_ring_test_ib,
1318 .is_lockup = cik_sdma_ring_is_lockup,
1319};
1320
1321static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1322{
1323 adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
1324 adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
1325}
1326
1327static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1328 .set = cik_sdma_set_trap_irq_state,
1329 .process = cik_sdma_process_trap_irq,
1330};
1331
1332static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1333 .process = cik_sdma_process_illegal_inst_irq,
1334};
1335
1336static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1337{
1338 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1339 adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1340 adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1341}
1342
1343/**
1344 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1345 *
1346 * @ring: amdgpu_ring structure holding ring information
1347 * @src_offset: src GPU address
1348 * @dst_offset: dst GPU address
1349 * @byte_count: number of bytes to xfer
1350 *
1351 * Copy GPU buffers using the DMA engine (CIK).
1352 * Used by the amdgpu ttm implementation to move pages if
1353 * registered as the asic copy callback.
1354 */
1355static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring,
1356 uint64_t src_offset,
1357 uint64_t dst_offset,
1358 uint32_t byte_count)
1359{
1360 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
1361 amdgpu_ring_write(ring, byte_count);
1362 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1363 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1364 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1365 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1366 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1367}
1368
1369/**
1370 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1371 *
1372 * @ring: amdgpu_ring structure holding ring information
1373 * @src_data: value to write to buffer
1374 * @dst_offset: dst GPU address
1375 * @byte_count: number of bytes to xfer
1376 *
1377 * Fill GPU buffers using the DMA engine (CIK).
1378 */
1379static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring,
1380 uint32_t src_data,
1381 uint64_t dst_offset,
1382 uint32_t byte_count)
1383{
1384 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0));
1385 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1386 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1387 amdgpu_ring_write(ring, src_data);
1388 amdgpu_ring_write(ring, byte_count);
1389}
1390
1391static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1392 .copy_max_bytes = 0x1fffff,
1393 .copy_num_dw = 7,
1394 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1395
1396 .fill_max_bytes = 0x1fffff,
1397 .fill_num_dw = 5,
1398 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1399};
1400
1401static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1402{
1403 if (adev->mman.buffer_funcs == NULL) {
1404 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1405 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1406 }
1407}
1408
1409static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1410 .copy_pte = cik_sdma_vm_copy_pte,
1411 .write_pte = cik_sdma_vm_write_pte,
1412 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1413 .pad_ib = cik_sdma_vm_pad_ib,
1414};
1415
1416static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1417{
1418 if (adev->vm_manager.vm_pte_funcs == NULL) {
1419 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1420 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1421 }
1422}
Linux kernel - Deliverables
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