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drm/amdgpu: Revert "add mutex for ba_va->valids/invalids"
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
74a5d165
JX		 36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
a2e73f56
AD		 38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
66
67u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
68
69/*
70 * sDMA - System DMA
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
76 *
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
83 * buffers.
84 */
85
86/**
87 * cik_sdma_init_microcode - load ucode images from disk
88 *
89 * @adev: amdgpu_device pointer
90 *
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
94 */
95static int cik_sdma_init_microcode(struct amdgpu_device *adev)
96{
97 const char *chip_name;
98 char fw_name[30];
c113ea1c 99 int err = 0, i;
a2e73f56
AD		 100
101 DRM_DEBUG("\n");
102
103 switch (adev->asic_type) {
104 case CHIP_BONAIRE:
105 chip_name = "bonaire";
106 break;
107 case CHIP_HAWAII:
108 chip_name = "hawaii";
109 break;
110 case CHIP_KAVERI:
111 chip_name = "kaveri";
112 break;
113 case CHIP_KABINI:
114 chip_name = "kabini";
115 break;
116 case CHIP_MULLINS:
117 chip_name = "mullins";
118 break;
119 default: BUG();
120 }
121
c113ea1c 122 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 123 if (i == 0)
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
125 else
126 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
c113ea1c 127 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
a2e73f56
AD		 128 if (err)
129 goto out;
c113ea1c 130 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
a2e73f56
AD		 131 }
132out:
133 if (err) {
134 printk(KERN_ERR
135 "cik_sdma: Failed to load firmware \"%s\"\n",
136 fw_name);
c113ea1c
AD		 137 for (i = 0; i < adev->sdma.num_instances; i++) {
138 release_firmware(adev->sdma.instance[i].fw);
139 adev->sdma.instance[i].fw = NULL;
a2e73f56
AD		 140 }
141 }
142 return err;
143}
144
145/**
146 * cik_sdma_ring_get_rptr - get the current read pointer
147 *
148 * @ring: amdgpu ring pointer
149 *
150 * Get the current rptr from the hardware (CIK+).
151 */
152static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
153{
154 u32 rptr;
155
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
157
158 return (rptr & 0x3fffc) >> 2;
159}
160
161/**
162 * cik_sdma_ring_get_wptr - get the current write pointer
163 *
164 * @ring: amdgpu ring pointer
165 *
166 * Get the current wptr from the hardware (CIK+).
167 */
168static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
169{
170 struct amdgpu_device *adev = ring->adev;
c113ea1c 171 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
a2e73f56
AD		 172
173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
174}
175
176/**
177 * cik_sdma_ring_set_wptr - commit the write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Write the wptr back to the hardware (CIK+).
182 */
183static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184{
185 struct amdgpu_device *adev = ring->adev;
c113ea1c 186 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
a2e73f56
AD		 187
188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
189}
190
ac01db3d
JZ		 191static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
192{
c113ea1c 193 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 194 int i;
195
196 for (i = 0; i < count; i++)
197 if (sdma && sdma->burst_nop && (i == 0))
198 amdgpu_ring_write(ring, ring->nop |
199 SDMA_NOP_COUNT(count - 1));
200 else
201 amdgpu_ring_write(ring, ring->nop);
202}
203
a2e73f56
AD		 204/**
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
206 *
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
209 *
210 * Schedule an IB in the DMA ring (CIK).
211 */
212static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
213 struct amdgpu_ib *ib)
214{
4ff37a83 215 u32 extra_bits = ib->vm_id & 0xf;
a2e73f56
AD		 216 u32 next_rptr = ring->wptr + 5;
217
a2e73f56
AD		 218 while ((next_rptr & 7) != 4)
219 next_rptr++;
220
221 next_rptr += 4;
222 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
223 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
224 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
225 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
226 amdgpu_ring_write(ring, next_rptr);
227
a2e73f56 228 /* IB packet must end on a 8 DW boundary */
ac01db3d
JZ		 229 cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
230
a2e73f56
AD		 231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 amdgpu_ring_write(ring, ib->length_dw);
235
236}
237
238/**
d2edb07b 239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
a2e73f56
AD		 240 *
241 * @ring: amdgpu ring pointer
242 *
243 * Emit an hdp flush packet on the requested DMA ring.
244 */
d2edb07b 245static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 246{
247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
249 u32 ref_and_mask;
250
c113ea1c 251 if (ring == &ring->adev->sdma.instance[0].ring)
a2e73f56
AD		 252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
253 else
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
255
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */
261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
262}
263
498dd97d
CZ		 264static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
265{
266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
267 amdgpu_ring_write(ring, mmHDP_DEBUG0);
268 amdgpu_ring_write(ring, 1);
269}
270
a2e73f56
AD		 271/**
272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
273 *
274 * @ring: amdgpu ring pointer
275 * @fence: amdgpu fence object
276 *
277 * Add a DMA fence packet to the ring to write
278 * the fence seq number and DMA trap packet to generate
279 * an interrupt if needed (CIK).
280 */
281static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 282 unsigned flags)
a2e73f56 283{
890ee23f 284 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
a2e73f56
AD		 285 /* write the fence */
286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
287 amdgpu_ring_write(ring, lower_32_bits(addr));
288 amdgpu_ring_write(ring, upper_32_bits(addr));
289 amdgpu_ring_write(ring, lower_32_bits(seq));
290
291 /* optionally write high bits as well */
292 if (write64bit) {
293 addr += 4;
294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
295 amdgpu_ring_write(ring, lower_32_bits(addr));
296 amdgpu_ring_write(ring, upper_32_bits(addr));
297 amdgpu_ring_write(ring, upper_32_bits(seq));
298 }
299
300 /* generate an interrupt */
301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
302}
303
a2e73f56
AD		 304/**
305 * cik_sdma_gfx_stop - stop the gfx async dma engines
306 *
307 * @adev: amdgpu_device pointer
308 *
309 * Stop the gfx async dma ring buffers (CIK).
310 */
311static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
312{
c113ea1c
AD		 313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
a2e73f56
AD		 315 u32 rb_cntl;
316 int i;
317
318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
319 (adev->mman.buffer_funcs_ring == sdma1))
320 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
321
c113ea1c 322 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
327 }
328 sdma0->ready = false;
329 sdma1->ready = false;
330}
331
332/**
333 * cik_sdma_rlc_stop - stop the compute async dma engines
334 *
335 * @adev: amdgpu_device pointer
336 *
337 * Stop the compute async dma queues (CIK).
338 */
339static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
340{
341 /* XXX todo */
342}
343
344/**
345 * cik_sdma_enable - stop the async dma engines
346 *
347 * @adev: amdgpu_device pointer
348 * @enable: enable/disable the DMA MEs.
349 *
350 * Halt or unhalt the async dma engines (CIK).
351 */
352static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
353{
354 u32 me_cntl;
355 int i;
356
357 if (enable == false) {
358 cik_sdma_gfx_stop(adev);
359 cik_sdma_rlc_stop(adev);
360 }
361
c113ea1c 362 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 363 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
364 if (enable)
365 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
366 else
367 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
368 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
369 }
370}
371
372/**
373 * cik_sdma_gfx_resume - setup and start the async dma engines
374 *
375 * @adev: amdgpu_device pointer
376 *
377 * Set up the gfx DMA ring buffers and enable them (CIK).
378 * Returns 0 for success, error for failure.
379 */
380static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
381{
382 struct amdgpu_ring *ring;
383 u32 rb_cntl, ib_cntl;
384 u32 rb_bufsz;
385 u32 wb_offset;
386 int i, j, r;
387
c113ea1c
AD		 388 for (i = 0; i < adev->sdma.num_instances; i++) {
389 ring = &adev->sdma.instance[i].ring;
a2e73f56
AD		 390 wb_offset = (ring->rptr_offs * 4);
391
392 mutex_lock(&adev->srbm_mutex);
393 for (j = 0; j < 16; j++) {
394 cik_srbm_select(adev, 0, 0, 0, j);
395 /* SDMA GFX */
396 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
397 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
398 /* XXX SDMA RLC - todo */
399 }
400 cik_srbm_select(adev, 0, 0, 0, 0);
401 mutex_unlock(&adev->srbm_mutex);
402
2b3a765d
AD		 403 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
404 adev->gfx.config.gb_addr_config & 0x70);
405
a2e73f56
AD		 406 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
407 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
408
409 /* Set ring buffer size in dwords */
410 rb_bufsz = order_base_2(ring->ring_size / 4);
411 rb_cntl = rb_bufsz << 1;
412#ifdef __BIG_ENDIAN
454fc95e
AD		 413 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
414 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
a2e73f56
AD		 415#endif
416 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
417
418 /* Initialize the ring buffer's read and write pointers */
419 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
420 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
421
422 /* set the wb address whether it's enabled or not */
423 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
424 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
425 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
426 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
427
428 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
429
430 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
431 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
432
433 ring->wptr = 0;
434 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
435
436 /* enable DMA RB */
437 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
438 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
439
440 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
441#ifdef __BIG_ENDIAN
442 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
443#endif
444 /* enable DMA IBs */
445 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
446
447 ring->ready = true;
448
449 r = amdgpu_ring_test_ring(ring);
450 if (r) {
451 ring->ready = false;
452 return r;
453 }
454
455 if (adev->mman.buffer_funcs_ring == ring)
456 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
457 }
458
459 return 0;
460}
461
462/**
463 * cik_sdma_rlc_resume - setup and start the async dma engines
464 *
465 * @adev: amdgpu_device pointer
466 *
467 * Set up the compute DMA queues and enable them (CIK).
468 * Returns 0 for success, error for failure.
469 */
470static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
471{
472 /* XXX todo */
473 return 0;
474}
475
476/**
477 * cik_sdma_load_microcode - load the sDMA ME ucode
478 *
479 * @adev: amdgpu_device pointer
480 *
481 * Loads the sDMA0/1 ucode.
482 * Returns 0 for success, -EINVAL if the ucode is not available.
483 */
484static int cik_sdma_load_microcode(struct amdgpu_device *adev)
485{
486 const struct sdma_firmware_header_v1_0 *hdr;
487 const __le32 *fw_data;
488 u32 fw_size;
489 int i, j;
490
a2e73f56
AD		 491 /* halt the MEs */
492 cik_sdma_enable(adev, false);
493
c113ea1c
AD		 494 for (i = 0; i < adev->sdma.num_instances; i++) {
495 if (!adev->sdma.instance[i].fw)
496 return -EINVAL;
497 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
a2e73f56
AD		 498 amdgpu_ucode_print_sdma_hdr(&hdr->header);
499 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
c113ea1c
AD		 500 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
501 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
502 if (adev->sdma.instance[i].feature_version >= 20)
503 adev->sdma.instance[i].burst_nop = true;
a2e73f56 504 fw_data = (const __le32 *)
c113ea1c 505 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
a2e73f56
AD		 506 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
507 for (j = 0; j < fw_size; j++)
508 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
c113ea1c 509 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
a2e73f56
AD		 510 }
511
512 return 0;
513}
514
515/**
516 * cik_sdma_start - setup and start the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Set up the DMA engines and enable them (CIK).
521 * Returns 0 for success, error for failure.
522 */
523static int cik_sdma_start(struct amdgpu_device *adev)
524{
525 int r;
526
527 r = cik_sdma_load_microcode(adev);
528 if (r)
529 return r;
530
531 /* unhalt the MEs */
532 cik_sdma_enable(adev, true);
533
534 /* start the gfx rings and rlc compute queues */
535 r = cik_sdma_gfx_resume(adev);
536 if (r)
537 return r;
538 r = cik_sdma_rlc_resume(adev);
539 if (r)
540 return r;
541
542 return 0;
543}
544
545/**
546 * cik_sdma_ring_test_ring - simple async dma engine test
547 *
548 * @ring: amdgpu_ring structure holding ring information
549 *
550 * Test the DMA engine by writing using it to write an
551 * value to memory. (CIK).
552 * Returns 0 for success, error for failure.
553 */
554static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
555{
556 struct amdgpu_device *adev = ring->adev;
557 unsigned i;
558 unsigned index;
559 int r;
560 u32 tmp;
561 u64 gpu_addr;
562
563 r = amdgpu_wb_get(adev, &index);
564 if (r) {
565 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
566 return r;
567 }
568
569 gpu_addr = adev->wb.gpu_addr + (index * 4);
570 tmp = 0xCAFEDEAD;
571 adev->wb.wb[index] = cpu_to_le32(tmp);
572
a27de35c 573 r = amdgpu_ring_alloc(ring, 5);
a2e73f56
AD		 574 if (r) {
575 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
576 amdgpu_wb_free(adev, index);
577 return r;
578 }
579 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
580 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
581 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
582 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
583 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 584 amdgpu_ring_commit(ring);
a2e73f56
AD		 585
586 for (i = 0; i < adev->usec_timeout; i++) {
587 tmp = le32_to_cpu(adev->wb.wb[index]);
588 if (tmp == 0xDEADBEEF)
589 break;
590 DRM_UDELAY(1);
591 }
592
593 if (i < adev->usec_timeout) {
594 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
595 } else {
596 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
597 ring->idx, tmp);
598 r = -EINVAL;
599 }
600 amdgpu_wb_free(adev, index);
601
602 return r;
603}
604
605/**
606 * cik_sdma_ring_test_ib - test an IB on the DMA engine
607 *
608 * @ring: amdgpu_ring structure holding ring information
609 *
610 * Test a simple IB in the DMA ring (CIK).
611 * Returns 0 on success, error on failure.
612 */
613static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
614{
615 struct amdgpu_device *adev = ring->adev;
616 struct amdgpu_ib ib;
1763552e 617 struct fence *f = NULL;
a2e73f56
AD		 618 unsigned i;
619 unsigned index;
620 int r;
621 u32 tmp = 0;
622 u64 gpu_addr;
623
624 r = amdgpu_wb_get(adev, &index);
625 if (r) {
626 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
627 return r;
628 }
629
630 gpu_addr = adev->wb.gpu_addr + (index * 4);
631 tmp = 0xCAFEDEAD;
632 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 633 memset(&ib, 0, sizeof(ib));
b07c60c0 634 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56 635 if (r) {
a2e73f56 636 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 637 goto err0;
a2e73f56
AD		 638 }
639
640 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
641 ib.ptr[1] = lower_32_bits(gpu_addr);
642 ib.ptr[2] = upper_32_bits(gpu_addr);
643 ib.ptr[3] = 1;
644 ib.ptr[4] = 0xDEADBEEF;
645 ib.length_dw = 5;
336d1f5e 646 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
0011fdaa
CZ		 647 if (r)
648 goto err1;
a2e73f56 649
1763552e 650 r = fence_wait(f, false);
a2e73f56 651 if (r) {
a2e73f56 652 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 653 goto err1;
a2e73f56
AD		 654 }
655 for (i = 0; i < adev->usec_timeout; i++) {
656 tmp = le32_to_cpu(adev->wb.wb[index]);
657 if (tmp == 0xDEADBEEF)
658 break;
659 DRM_UDELAY(1);
660 }
661 if (i < adev->usec_timeout) {
662 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
0011fdaa
CZ		 663 ring->idx, i);
664 goto err1;
a2e73f56
AD		 665 } else {
666 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
667 r = -EINVAL;
668 }
0011fdaa
CZ		 669
670err1:
281b4223 671 fence_put(f);
a2e73f56 672 amdgpu_ib_free(adev, &ib);
0011fdaa 673err0:
a2e73f56
AD		 674 amdgpu_wb_free(adev, index);
675 return r;
676}
677
678/**
679 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
680 *
681 * @ib: indirect buffer to fill with commands
682 * @pe: addr of the page entry
683 * @src: src addr to copy from
684 * @count: number of page entries to update
685 *
686 * Update PTEs by copying them from the GART using sDMA (CIK).
687 */
688static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
689 uint64_t pe, uint64_t src,
690 unsigned count)
691{
692 while (count) {
693 unsigned bytes = count * 8;
694 if (bytes > 0x1FFFF8)
695 bytes = 0x1FFFF8;
696
697 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
698 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
699 ib->ptr[ib->length_dw++] = bytes;
700 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
701 ib->ptr[ib->length_dw++] = lower_32_bits(src);
702 ib->ptr[ib->length_dw++] = upper_32_bits(src);
703 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
704 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
705
706 pe += bytes;
707 src += bytes;
708 count -= bytes / 8;
709 }
710}
711
712/**
713 * cik_sdma_vm_write_pages - update PTEs by writing them manually
714 *
715 * @ib: indirect buffer to fill with commands
716 * @pe: addr of the page entry
717 * @addr: dst addr to write into pe
718 * @count: number of page entries to update
719 * @incr: increase next addr by incr bytes
720 * @flags: access flags
721 *
722 * Update PTEs by writing them manually using sDMA (CIK).
723 */
724static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
b07c9d2a 725 const dma_addr_t *pages_addr, uint64_t pe,
a2e73f56
AD		 726 uint64_t addr, unsigned count,
727 uint32_t incr, uint32_t flags)
728{
729 uint64_t value;
730 unsigned ndw;
731
732 while (count) {
733 ndw = count * 2;
734 if (ndw > 0xFFFFE)
735 ndw = 0xFFFFE;
736
737 /* for non-physically contiguous pages (system) */
738 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
739 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
740 ib->ptr[ib->length_dw++] = pe;
741 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
742 ib->ptr[ib->length_dw++] = ndw;
743 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
b07c9d2a 744 value = amdgpu_vm_map_gart(pages_addr, addr);
a2e73f56
AD		 745 addr += incr;
746 value |= flags;
747 ib->ptr[ib->length_dw++] = value;
748 ib->ptr[ib->length_dw++] = upper_32_bits(value);
749 }
750 }
751}
752
753/**
754 * cik_sdma_vm_set_pages - update the page tables using sDMA
755 *
756 * @ib: indirect buffer to fill with commands
757 * @pe: addr of the page entry
758 * @addr: dst addr to write into pe
759 * @count: number of page entries to update
760 * @incr: increase next addr by incr bytes
761 * @flags: access flags
762 *
763 * Update the page tables using sDMA (CIK).
764 */
765static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
766 uint64_t pe,
767 uint64_t addr, unsigned count,
768 uint32_t incr, uint32_t flags)
769{
770 uint64_t value;
771 unsigned ndw;
772
773 while (count) {
774 ndw = count;
775 if (ndw > 0x7FFFF)
776 ndw = 0x7FFFF;
777
778 if (flags & AMDGPU_PTE_VALID)
779 value = addr;
780 else
781 value = 0;
782
783 /* for physically contiguous pages (vram) */
784 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
785 ib->ptr[ib->length_dw++] = pe; /* dst addr */
786 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
787 ib->ptr[ib->length_dw++] = flags; /* mask */
788 ib->ptr[ib->length_dw++] = 0;
789 ib->ptr[ib->length_dw++] = value; /* value */
790 ib->ptr[ib->length_dw++] = upper_32_bits(value);
791 ib->ptr[ib->length_dw++] = incr; /* increment size */
792 ib->ptr[ib->length_dw++] = 0;
793 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
794
795 pe += ndw * 8;
796 addr += ndw * incr;
797 count -= ndw;
798 }
799}
800
801/**
802 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
803 *
804 * @ib: indirect buffer to fill with padding
805 *
806 */
9e5d5309 807static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
a2e73f56 808{
9e5d5309 809 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 810 u32 pad_count;
811 int i;
812
813 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
814 for (i = 0; i < pad_count; i++)
815 if (sdma && sdma->burst_nop && (i == 0))
816 ib->ptr[ib->length_dw++] =
817 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
818 SDMA_NOP_COUNT(pad_count - 1);
819 else
820 ib->ptr[ib->length_dw++] =
821 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
a2e73f56
AD		 822}
823
824/**
825 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
826 *
827 * @ring: amdgpu_ring pointer
828 * @vm: amdgpu_vm pointer
829 *
830 * Update the page table base and flush the VM TLB
831 * using sDMA (CIK).
832 */
833static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
834 unsigned vm_id, uint64_t pd_addr)
835{
836 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
837 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
5c55db83
CZ		 838 uint32_t seq = ring->fence_drv.sync_seq;
839 uint64_t addr = ring->fence_drv.gpu_addr;
840
841 /* wait for idle */
842 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
843 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
844 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
845 SDMA_POLL_REG_MEM_EXTRA_M));
846 amdgpu_ring_write(ring, addr & 0xfffffffc);
847 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
848 amdgpu_ring_write(ring, seq); /* reference */
849 amdgpu_ring_write(ring, 0xfffffff); /* mask */
850 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
851
a2e73f56
AD		 852
853 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
854 if (vm_id < 8) {
855 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
856 } else {
857 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
858 }
859 amdgpu_ring_write(ring, pd_addr >> 12);
860
a2e73f56
AD		 861 /* flush TLB */
862 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
863 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
864 amdgpu_ring_write(ring, 1 << vm_id);
865
866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
867 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
868 amdgpu_ring_write(ring, 0);
869 amdgpu_ring_write(ring, 0); /* reference */
870 amdgpu_ring_write(ring, 0); /* mask */
871 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
872}
873
874static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
875 bool enable)
876{
877 u32 orig, data;
878
879 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
880 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
881 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
882 } else {
883 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
884 data |= 0xff000000;
885 if (data != orig)
886 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
887
888 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
889 data |= 0xff000000;
890 if (data != orig)
891 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
892 }
893}
894
895static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
896 bool enable)
897{
898 u32 orig, data;
899
900 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
901 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
902 data |= 0x100;
903 if (orig != data)
904 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
905
906 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
907 data |= 0x100;
908 if (orig != data)
909 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
910 } else {
911 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
912 data &= ~0x100;
913 if (orig != data)
914 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
915
916 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
917 data &= ~0x100;
918 if (orig != data)
919 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
920 }
921}
922
5fc3aeeb 923static int cik_sdma_early_init(void *handle)
a2e73f56 924{
5fc3aeeb 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
926
c113ea1c
AD		 927 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
928
a2e73f56
AD		 929 cik_sdma_set_ring_funcs(adev);
930 cik_sdma_set_irq_funcs(adev);
931 cik_sdma_set_buffer_funcs(adev);
932 cik_sdma_set_vm_pte_funcs(adev);
933
934 return 0;
935}
936
5fc3aeeb 937static int cik_sdma_sw_init(void *handle)
a2e73f56
AD		 938{
939 struct amdgpu_ring *ring;
5fc3aeeb 940 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 941 int r, i;
a2e73f56
AD		 942
943 r = cik_sdma_init_microcode(adev);
944 if (r) {
945 DRM_ERROR("Failed to load sdma firmware!\n");
946 return r;
947 }
948
949 /* SDMA trap event */
c113ea1c 950 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
a2e73f56
AD		 951 if (r)
952 return r;
953
954 /* SDMA Privileged inst */
c113ea1c 955 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
a2e73f56
AD		 956 if (r)
957 return r;
958
959 /* SDMA Privileged inst */
c113ea1c 960 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
a2e73f56
AD		 961 if (r)
962 return r;
963
c113ea1c
AD		 964 for (i = 0; i < adev->sdma.num_instances; i++) {
965 ring = &adev->sdma.instance[i].ring;
966 ring->ring_obj = NULL;
967 sprintf(ring->name, "sdma%d", i);
968 r = amdgpu_ring_init(adev, ring, 256 * 1024,
969 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
970 &adev->sdma.trap_irq,
971 (i == 0) ?
972 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
973 AMDGPU_RING_TYPE_SDMA);
974 if (r)
975 return r;
976 }
a2e73f56
AD		 977
978 return r;
979}
980
5fc3aeeb 981static int cik_sdma_sw_fini(void *handle)
a2e73f56 982{
5fc3aeeb 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 984 int i;
5fc3aeeb 985
c113ea1c
AD		 986 for (i = 0; i < adev->sdma.num_instances; i++)
987 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
a2e73f56
AD		 988
989 return 0;
990}
991
5fc3aeeb 992static int cik_sdma_hw_init(void *handle)
a2e73f56
AD		 993{
994 int r;
5fc3aeeb 995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 996
997 r = cik_sdma_start(adev);
998 if (r)
999 return r;
1000
1001 return r;
1002}
1003
5fc3aeeb 1004static int cik_sdma_hw_fini(void *handle)
a2e73f56 1005{
5fc3aeeb 1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
a2e73f56
AD		 1008 cik_sdma_enable(adev, false);
1009
1010 return 0;
1011}
1012
5fc3aeeb 1013static int cik_sdma_suspend(void *handle)
a2e73f56 1014{
5fc3aeeb 1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1016
1017 return cik_sdma_hw_fini(adev);
1018}
1019
5fc3aeeb 1020static int cik_sdma_resume(void *handle)
a2e73f56 1021{
5fc3aeeb 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1023
1024 return cik_sdma_hw_init(adev);
1025}
1026
5fc3aeeb 1027static bool cik_sdma_is_idle(void *handle)
a2e73f56 1028{
5fc3aeeb 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1030 u32 tmp = RREG32(mmSRBM_STATUS2);
1031
1032 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1033 SRBM_STATUS2__SDMA1_BUSY_MASK))
1034 return false;
1035
1036 return true;
1037}
1038
5fc3aeeb 1039static int cik_sdma_wait_for_idle(void *handle)
a2e73f56
AD		 1040{
1041 unsigned i;
1042 u32 tmp;
5fc3aeeb 1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1044
1045 for (i = 0; i < adev->usec_timeout; i++) {
1046 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1047 SRBM_STATUS2__SDMA1_BUSY_MASK);
1048
1049 if (!tmp)
1050 return 0;
1051 udelay(1);
1052 }
1053 return -ETIMEDOUT;
1054}
1055
5fc3aeeb 1056static void cik_sdma_print_status(void *handle)
a2e73f56
AD		 1057{
1058 int i, j;
5fc3aeeb 1059 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1060
1061 dev_info(adev->dev, "CIK SDMA registers\n");
1062 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1063 RREG32(mmSRBM_STATUS2));
c113ea1c 1064 for (i = 0; i < adev->sdma.num_instances; i++) {
a2e73f56
AD		 1065 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1066 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1067 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1068 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1069 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1070 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1071 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1072 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1073 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1074 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1075 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1076 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1077 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1078 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1079 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1080 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1081 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1082 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1083 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1084 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1085 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1086 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1087 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1088 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1089 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1090 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
2b3a765d
AD		 1091 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1092 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
a2e73f56
AD		 1093 mutex_lock(&adev->srbm_mutex);
1094 for (j = 0; j < 16; j++) {
1095 cik_srbm_select(adev, 0, 0, 0, j);
1096 dev_info(adev->dev, " VM %d:\n", j);
1097 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1098 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1099 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1100 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1101 }
1102 cik_srbm_select(adev, 0, 0, 0, 0);
1103 mutex_unlock(&adev->srbm_mutex);
1104 }
1105}
1106
5fc3aeeb 1107static int cik_sdma_soft_reset(void *handle)
a2e73f56
AD		 1108{
1109 u32 srbm_soft_reset = 0;
5fc3aeeb 1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1111 u32 tmp = RREG32(mmSRBM_STATUS2);
1112
1113 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1114 /* sdma0 */
1115 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1116 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1117 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1118 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1119 }
1120 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1121 /* sdma1 */
1122 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1123 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1124 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1125 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1126 }
1127
1128 if (srbm_soft_reset) {
5fc3aeeb 1129 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1130
1131 tmp = RREG32(mmSRBM_SOFT_RESET);
1132 tmp |= srbm_soft_reset;
1133 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1134 WREG32(mmSRBM_SOFT_RESET, tmp);
1135 tmp = RREG32(mmSRBM_SOFT_RESET);
1136
1137 udelay(50);
1138
1139 tmp &= ~srbm_soft_reset;
1140 WREG32(mmSRBM_SOFT_RESET, tmp);
1141 tmp = RREG32(mmSRBM_SOFT_RESET);
1142
1143 /* Wait a little for things to settle down */
1144 udelay(50);
1145
5fc3aeeb 1146 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1147 }
1148
1149 return 0;
1150}
1151
1152static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1153 struct amdgpu_irq_src *src,
1154 unsigned type,
1155 enum amdgpu_interrupt_state state)
1156{
1157 u32 sdma_cntl;
1158
1159 switch (type) {
1160 case AMDGPU_SDMA_IRQ_TRAP0:
1161 switch (state) {
1162 case AMDGPU_IRQ_STATE_DISABLE:
1163 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1164 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1165 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1166 break;
1167 case AMDGPU_IRQ_STATE_ENABLE:
1168 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1169 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1170 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1171 break;
1172 default:
1173 break;
1174 }
1175 break;
1176 case AMDGPU_SDMA_IRQ_TRAP1:
1177 switch (state) {
1178 case AMDGPU_IRQ_STATE_DISABLE:
1179 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1180 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1181 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1182 break;
1183 case AMDGPU_IRQ_STATE_ENABLE:
1184 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1185 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1186 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1187 break;
1188 default:
1189 break;
1190 }
1191 break;
1192 default:
1193 break;
1194 }
1195 return 0;
1196}
1197
1198static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1199 struct amdgpu_irq_src *source,
1200 struct amdgpu_iv_entry *entry)
1201{
1202 u8 instance_id, queue_id;
1203
1204 instance_id = (entry->ring_id & 0x3) >> 0;
1205 queue_id = (entry->ring_id & 0xc) >> 2;
1206 DRM_DEBUG("IH: SDMA trap\n");
1207 switch (instance_id) {
1208 case 0:
1209 switch (queue_id) {
1210 case 0:
c113ea1c 1211 amdgpu_fence_process(&adev->sdma.instance[0].ring);
a2e73f56
AD		 1212 break;
1213 case 1:
1214 /* XXX compute */
1215 break;
1216 case 2:
1217 /* XXX compute */
1218 break;
1219 }
1220 break;
1221 case 1:
1222 switch (queue_id) {
1223 case 0:
c113ea1c 1224 amdgpu_fence_process(&adev->sdma.instance[1].ring);
a2e73f56
AD		 1225 break;
1226 case 1:
1227 /* XXX compute */
1228 break;
1229 case 2:
1230 /* XXX compute */
1231 break;
1232 }
1233 break;
1234 }
1235
1236 return 0;
1237}
1238
1239static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1240 struct amdgpu_irq_src *source,
1241 struct amdgpu_iv_entry *entry)
1242{
1243 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1244 schedule_work(&adev->reset_work);
1245 return 0;
1246}
1247
5fc3aeeb 1248static int cik_sdma_set_clockgating_state(void *handle,
1249 enum amd_clockgating_state state)
a2e73f56
AD		 1250{
1251 bool gate = false;
5fc3aeeb 1252 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 1253
5fc3aeeb 1254 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 1255 gate = true;
1256
1257 cik_enable_sdma_mgcg(adev, gate);
1258 cik_enable_sdma_mgls(adev, gate);
1259
1260 return 0;
1261}
1262
5fc3aeeb 1263static int cik_sdma_set_powergating_state(void *handle,
1264 enum amd_powergating_state state)
a2e73f56
AD		 1265{
1266 return 0;
1267}
1268
5fc3aeeb 1269const struct amd_ip_funcs cik_sdma_ip_funcs = {
a2e73f56
AD		 1270 .early_init = cik_sdma_early_init,
1271 .late_init = NULL,
1272 .sw_init = cik_sdma_sw_init,
1273 .sw_fini = cik_sdma_sw_fini,
1274 .hw_init = cik_sdma_hw_init,
1275 .hw_fini = cik_sdma_hw_fini,
1276 .suspend = cik_sdma_suspend,
1277 .resume = cik_sdma_resume,
1278 .is_idle = cik_sdma_is_idle,
1279 .wait_for_idle = cik_sdma_wait_for_idle,
1280 .soft_reset = cik_sdma_soft_reset,
1281 .print_status = cik_sdma_print_status,
1282 .set_clockgating_state = cik_sdma_set_clockgating_state,
1283 .set_powergating_state = cik_sdma_set_powergating_state,
1284};
1285
a2e73f56
AD		 1286static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1287 .get_rptr = cik_sdma_ring_get_rptr,
1288 .get_wptr = cik_sdma_ring_get_wptr,
1289 .set_wptr = cik_sdma_ring_set_wptr,
1290 .parse_cs = NULL,
1291 .emit_ib = cik_sdma_ring_emit_ib,
1292 .emit_fence = cik_sdma_ring_emit_fence,
a2e73f56 1293 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
d2edb07b 1294 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
498dd97d 1295 .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
a2e73f56
AD		 1296 .test_ring = cik_sdma_ring_test_ring,
1297 .test_ib = cik_sdma_ring_test_ib,
ac01db3d 1298 .insert_nop = cik_sdma_ring_insert_nop,
9e5d5309 1299 .pad_ib = cik_sdma_ring_pad_ib,
a2e73f56
AD		 1300};
1301
1302static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1303{
c113ea1c
AD		 1304 int i;
1305
1306 for (i = 0; i < adev->sdma.num_instances; i++)
1307 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
a2e73f56
AD		 1308}
1309
1310static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1311 .set = cik_sdma_set_trap_irq_state,
1312 .process = cik_sdma_process_trap_irq,
1313};
1314
1315static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1316 .process = cik_sdma_process_illegal_inst_irq,
1317};
1318
1319static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1320{
c113ea1c
AD		 1321 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1322 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1323 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
a2e73f56
AD		 1324}
1325
1326/**
1327 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1328 *
1329 * @ring: amdgpu_ring structure holding ring information
1330 * @src_offset: src GPU address
1331 * @dst_offset: dst GPU address
1332 * @byte_count: number of bytes to xfer
1333 *
1334 * Copy GPU buffers using the DMA engine (CIK).
1335 * Used by the amdgpu ttm implementation to move pages if
1336 * registered as the asic copy callback.
1337 */
c7ae72c0 1338static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
a2e73f56
AD		 1339 uint64_t src_offset,
1340 uint64_t dst_offset,
1341 uint32_t byte_count)
1342{
c7ae72c0
CZ		 1343 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1344 ib->ptr[ib->length_dw++] = byte_count;
1345 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1346 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1347 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1348 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1349 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
a2e73f56
AD		 1350}
1351
1352/**
1353 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1354 *
1355 * @ring: amdgpu_ring structure holding ring information
1356 * @src_data: value to write to buffer
1357 * @dst_offset: dst GPU address
1358 * @byte_count: number of bytes to xfer
1359 *
1360 * Fill GPU buffers using the DMA engine (CIK).
1361 */
6e7a3840 1362static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
a2e73f56
AD		 1363 uint32_t src_data,
1364 uint64_t dst_offset,
1365 uint32_t byte_count)
1366{
6e7a3840
CZ		 1367 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1368 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1369 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1370 ib->ptr[ib->length_dw++] = src_data;
1371 ib->ptr[ib->length_dw++] = byte_count;
a2e73f56
AD		 1372}
1373
1374static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1375 .copy_max_bytes = 0x1fffff,
1376 .copy_num_dw = 7,
1377 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1378
1379 .fill_max_bytes = 0x1fffff,
1380 .fill_num_dw = 5,
1381 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1382};
1383
1384static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1385{
1386 if (adev->mman.buffer_funcs == NULL) {
1387 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
c113ea1c 1388 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
a2e73f56
AD		 1389 }
1390}
1391
1392static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1393 .copy_pte = cik_sdma_vm_copy_pte,
1394 .write_pte = cik_sdma_vm_write_pte,
1395 .set_pte_pde = cik_sdma_vm_set_pte_pde,
a2e73f56
AD		 1396};
1397
1398static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1399{
2d55e45a
CK		 1400 unsigned i;
1401
a2e73f56
AD		 1402 if (adev->vm_manager.vm_pte_funcs == NULL) {
1403 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
2d55e45a
CK		 1404 for (i = 0; i < adev->sdma.num_instances; i++)
1405 adev->vm_manager.vm_pte_rings[i] =
1406 &adev->sdma.instance[i].ring;
1407
1408 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
a2e73f56
AD		 1409 }
1410}
Linux kernel - Deliverables
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