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drm/amdgpu: always emit GDS switch
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
74a5d165
JX		 36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
a2e73f56
AD		 38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
66
67u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
68
69/*
70 * sDMA - System DMA
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
76 *
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
83 * buffers.
84 */
85
86/**
87 * cik_sdma_init_microcode - load ucode images from disk
88 *
89 * @adev: amdgpu_device pointer
90 *
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
94 */
95static int cik_sdma_init_microcode(struct amdgpu_device *adev)
96{
97 const char *chip_name;
98 char fw_name[30];
99 int err, i;
100
101 DRM_DEBUG("\n");
102
103 switch (adev->asic_type) {
104 case CHIP_BONAIRE:
105 chip_name = "bonaire";
106 break;
107 case CHIP_HAWAII:
108 chip_name = "hawaii";
109 break;
110 case CHIP_KAVERI:
111 chip_name = "kaveri";
112 break;
113 case CHIP_KABINI:
114 chip_name = "kabini";
115 break;
116 case CHIP_MULLINS:
117 chip_name = "mullins";
118 break;
119 default: BUG();
120 }
121
122 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
123 if (i == 0)
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
125 else
126 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
127 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
128 if (err)
129 goto out;
130 err = amdgpu_ucode_validate(adev->sdma[i].fw);
131 }
132out:
133 if (err) {
134 printk(KERN_ERR
135 "cik_sdma: Failed to load firmware \"%s\"\n",
136 fw_name);
137 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
138 release_firmware(adev->sdma[i].fw);
139 adev->sdma[i].fw = NULL;
140 }
141 }
142 return err;
143}
144
145/**
146 * cik_sdma_ring_get_rptr - get the current read pointer
147 *
148 * @ring: amdgpu ring pointer
149 *
150 * Get the current rptr from the hardware (CIK+).
151 */
152static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
153{
154 u32 rptr;
155
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
157
158 return (rptr & 0x3fffc) >> 2;
159}
160
161/**
162 * cik_sdma_ring_get_wptr - get the current write pointer
163 *
164 * @ring: amdgpu ring pointer
165 *
166 * Get the current wptr from the hardware (CIK+).
167 */
168static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
169{
170 struct amdgpu_device *adev = ring->adev;
171 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
172
173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
174}
175
176/**
177 * cik_sdma_ring_set_wptr - commit the write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Write the wptr back to the hardware (CIK+).
182 */
183static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184{
185 struct amdgpu_device *adev = ring->adev;
186 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
187
188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
189}
190
191static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *);
192
193/**
194 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
195 *
196 * @ring: amdgpu ring pointer
197 * @ib: IB object to schedule
198 *
199 * Schedule an IB in the DMA ring (CIK).
200 */
201static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
202 struct amdgpu_ib *ib)
203{
204 u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
205 u32 next_rptr = ring->wptr + 5;
206
207 if (ib->flush_hdp_writefifo)
208 next_rptr += 6;
209
210 while ((next_rptr & 7) != 4)
211 next_rptr++;
212
213 next_rptr += 4;
214 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
215 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
216 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
217 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
218 amdgpu_ring_write(ring, next_rptr);
219
220 if (ib->flush_hdp_writefifo) {
221 /* flush HDP */
222 cik_sdma_hdp_flush_ring_emit(ring);
223 }
224
225 /* IB packet must end on a 8 DW boundary */
226 while ((ring->wptr & 7) != 4)
227 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
228 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
229 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
230 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
231 amdgpu_ring_write(ring, ib->length_dw);
232
233}
234
235/**
236 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
237 *
238 * @ring: amdgpu ring pointer
239 *
240 * Emit an hdp flush packet on the requested DMA ring.
241 */
242static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring)
243{
244 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
245 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
246 u32 ref_and_mask;
247
248 if (ring == &ring->adev->sdma[0].ring)
249 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
250 else
251 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
252
253 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
254 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
255 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
256 amdgpu_ring_write(ring, ref_and_mask); /* reference */
257 amdgpu_ring_write(ring, ref_and_mask); /* mask */
258 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
259}
260
261/**
262 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
263 *
264 * @ring: amdgpu ring pointer
265 * @fence: amdgpu fence object
266 *
267 * Add a DMA fence packet to the ring to write
268 * the fence seq number and DMA trap packet to generate
269 * an interrupt if needed (CIK).
270 */
271static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
272 bool write64bit)
273{
274 /* write the fence */
275 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
276 amdgpu_ring_write(ring, lower_32_bits(addr));
277 amdgpu_ring_write(ring, upper_32_bits(addr));
278 amdgpu_ring_write(ring, lower_32_bits(seq));
279
280 /* optionally write high bits as well */
281 if (write64bit) {
282 addr += 4;
283 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
284 amdgpu_ring_write(ring, lower_32_bits(addr));
285 amdgpu_ring_write(ring, upper_32_bits(addr));
286 amdgpu_ring_write(ring, upper_32_bits(seq));
287 }
288
289 /* generate an interrupt */
290 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
291}
292
293/**
294 * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
295 *
296 * @ring: amdgpu_ring structure holding ring information
297 * @semaphore: amdgpu semaphore object
298 * @emit_wait: wait or signal semaphore
299 *
300 * Add a DMA semaphore packet to the ring wait on or signal
301 * other rings (CIK).
302 */
303static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
304 struct amdgpu_semaphore *semaphore,
305 bool emit_wait)
306{
307 u64 addr = semaphore->gpu_addr;
308 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
309
310 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
311 amdgpu_ring_write(ring, addr & 0xfffffff8);
312 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
313
314 return true;
315}
316
317/**
318 * cik_sdma_gfx_stop - stop the gfx async dma engines
319 *
320 * @adev: amdgpu_device pointer
321 *
322 * Stop the gfx async dma ring buffers (CIK).
323 */
324static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
325{
326 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
327 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
328 u32 rb_cntl;
329 int i;
330
331 if ((adev->mman.buffer_funcs_ring == sdma0) ||
332 (adev->mman.buffer_funcs_ring == sdma1))
333 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
334
335 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
336 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
337 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
338 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
339 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
340 }
341 sdma0->ready = false;
342 sdma1->ready = false;
343}
344
345/**
346 * cik_sdma_rlc_stop - stop the compute async dma engines
347 *
348 * @adev: amdgpu_device pointer
349 *
350 * Stop the compute async dma queues (CIK).
351 */
352static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
353{
354 /* XXX todo */
355}
356
357/**
358 * cik_sdma_enable - stop the async dma engines
359 *
360 * @adev: amdgpu_device pointer
361 * @enable: enable/disable the DMA MEs.
362 *
363 * Halt or unhalt the async dma engines (CIK).
364 */
365static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
366{
367 u32 me_cntl;
368 int i;
369
370 if (enable == false) {
371 cik_sdma_gfx_stop(adev);
372 cik_sdma_rlc_stop(adev);
373 }
374
375 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
376 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
377 if (enable)
378 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
379 else
380 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
381 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
382 }
383}
384
385/**
386 * cik_sdma_gfx_resume - setup and start the async dma engines
387 *
388 * @adev: amdgpu_device pointer
389 *
390 * Set up the gfx DMA ring buffers and enable them (CIK).
391 * Returns 0 for success, error for failure.
392 */
393static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
394{
395 struct amdgpu_ring *ring;
396 u32 rb_cntl, ib_cntl;
397 u32 rb_bufsz;
398 u32 wb_offset;
399 int i, j, r;
400
401 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
402 ring = &adev->sdma[i].ring;
403 wb_offset = (ring->rptr_offs * 4);
404
405 mutex_lock(&adev->srbm_mutex);
406 for (j = 0; j < 16; j++) {
407 cik_srbm_select(adev, 0, 0, 0, j);
408 /* SDMA GFX */
409 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
410 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
411 /* XXX SDMA RLC - todo */
412 }
413 cik_srbm_select(adev, 0, 0, 0, 0);
414 mutex_unlock(&adev->srbm_mutex);
415
416 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
417 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
418
419 /* Set ring buffer size in dwords */
420 rb_bufsz = order_base_2(ring->ring_size / 4);
421 rb_cntl = rb_bufsz << 1;
422#ifdef __BIG_ENDIAN
423 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
424#endif
425 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
426
427 /* Initialize the ring buffer's read and write pointers */
428 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
429 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
430
431 /* set the wb address whether it's enabled or not */
432 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
433 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
434 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
435 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
436
437 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
438
439 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
440 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
441
442 ring->wptr = 0;
443 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
444
445 /* enable DMA RB */
446 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
447 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
448
449 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
450#ifdef __BIG_ENDIAN
451 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
452#endif
453 /* enable DMA IBs */
454 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
455
456 ring->ready = true;
457
458 r = amdgpu_ring_test_ring(ring);
459 if (r) {
460 ring->ready = false;
461 return r;
462 }
463
464 if (adev->mman.buffer_funcs_ring == ring)
465 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
466 }
467
468 return 0;
469}
470
471/**
472 * cik_sdma_rlc_resume - setup and start the async dma engines
473 *
474 * @adev: amdgpu_device pointer
475 *
476 * Set up the compute DMA queues and enable them (CIK).
477 * Returns 0 for success, error for failure.
478 */
479static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
480{
481 /* XXX todo */
482 return 0;
483}
484
485/**
486 * cik_sdma_load_microcode - load the sDMA ME ucode
487 *
488 * @adev: amdgpu_device pointer
489 *
490 * Loads the sDMA0/1 ucode.
491 * Returns 0 for success, -EINVAL if the ucode is not available.
492 */
493static int cik_sdma_load_microcode(struct amdgpu_device *adev)
494{
495 const struct sdma_firmware_header_v1_0 *hdr;
496 const __le32 *fw_data;
497 u32 fw_size;
498 int i, j;
499
500 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
501 return -EINVAL;
502
503 /* halt the MEs */
504 cik_sdma_enable(adev, false);
505
506 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
507 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
508 amdgpu_ucode_print_sdma_hdr(&hdr->header);
509 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
510 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
511 fw_data = (const __le32 *)
512 (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
513 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
514 for (j = 0; j < fw_size; j++)
515 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
516 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
517 }
518
519 return 0;
520}
521
522/**
523 * cik_sdma_start - setup and start the async dma engines
524 *
525 * @adev: amdgpu_device pointer
526 *
527 * Set up the DMA engines and enable them (CIK).
528 * Returns 0 for success, error for failure.
529 */
530static int cik_sdma_start(struct amdgpu_device *adev)
531{
532 int r;
533
534 r = cik_sdma_load_microcode(adev);
535 if (r)
536 return r;
537
538 /* unhalt the MEs */
539 cik_sdma_enable(adev, true);
540
541 /* start the gfx rings and rlc compute queues */
542 r = cik_sdma_gfx_resume(adev);
543 if (r)
544 return r;
545 r = cik_sdma_rlc_resume(adev);
546 if (r)
547 return r;
548
549 return 0;
550}
551
552/**
553 * cik_sdma_ring_test_ring - simple async dma engine test
554 *
555 * @ring: amdgpu_ring structure holding ring information
556 *
557 * Test the DMA engine by writing using it to write an
558 * value to memory. (CIK).
559 * Returns 0 for success, error for failure.
560 */
561static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
562{
563 struct amdgpu_device *adev = ring->adev;
564 unsigned i;
565 unsigned index;
566 int r;
567 u32 tmp;
568 u64 gpu_addr;
569
570 r = amdgpu_wb_get(adev, &index);
571 if (r) {
572 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
573 return r;
574 }
575
576 gpu_addr = adev->wb.gpu_addr + (index * 4);
577 tmp = 0xCAFEDEAD;
578 adev->wb.wb[index] = cpu_to_le32(tmp);
579
580 r = amdgpu_ring_lock(ring, 5);
581 if (r) {
582 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
583 amdgpu_wb_free(adev, index);
584 return r;
585 }
586 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
587 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
588 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
589 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
590 amdgpu_ring_write(ring, 0xDEADBEEF);
591 amdgpu_ring_unlock_commit(ring);
592
593 for (i = 0; i < adev->usec_timeout; i++) {
594 tmp = le32_to_cpu(adev->wb.wb[index]);
595 if (tmp == 0xDEADBEEF)
596 break;
597 DRM_UDELAY(1);
598 }
599
600 if (i < adev->usec_timeout) {
601 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
602 } else {
603 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
604 ring->idx, tmp);
605 r = -EINVAL;
606 }
607 amdgpu_wb_free(adev, index);
608
609 return r;
610}
611
612/**
613 * cik_sdma_ring_test_ib - test an IB on the DMA engine
614 *
615 * @ring: amdgpu_ring structure holding ring information
616 *
617 * Test a simple IB in the DMA ring (CIK).
618 * Returns 0 on success, error on failure.
619 */
620static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
621{
622 struct amdgpu_device *adev = ring->adev;
623 struct amdgpu_ib ib;
624 unsigned i;
625 unsigned index;
626 int r;
627 u32 tmp = 0;
628 u64 gpu_addr;
629
630 r = amdgpu_wb_get(adev, &index);
631 if (r) {
632 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
633 return r;
634 }
635
636 gpu_addr = adev->wb.gpu_addr + (index * 4);
637 tmp = 0xCAFEDEAD;
638 adev->wb.wb[index] = cpu_to_le32(tmp);
639
640 r = amdgpu_ib_get(ring, NULL, 256, &ib);
641 if (r) {
642 amdgpu_wb_free(adev, index);
643 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
644 return r;
645 }
646
647 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
648 ib.ptr[1] = lower_32_bits(gpu_addr);
649 ib.ptr[2] = upper_32_bits(gpu_addr);
650 ib.ptr[3] = 1;
651 ib.ptr[4] = 0xDEADBEEF;
652 ib.length_dw = 5;
653
654 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
655 if (r) {
656 amdgpu_ib_free(adev, &ib);
657 amdgpu_wb_free(adev, index);
658 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
659 return r;
660 }
661 r = amdgpu_fence_wait(ib.fence, false);
662 if (r) {
663 amdgpu_ib_free(adev, &ib);
664 amdgpu_wb_free(adev, index);
665 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
666 return r;
667 }
668 for (i = 0; i < adev->usec_timeout; i++) {
669 tmp = le32_to_cpu(adev->wb.wb[index]);
670 if (tmp == 0xDEADBEEF)
671 break;
672 DRM_UDELAY(1);
673 }
674 if (i < adev->usec_timeout) {
675 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
676 ib.fence->ring->idx, i);
677 } else {
678 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
679 r = -EINVAL;
680 }
681 amdgpu_ib_free(adev, &ib);
682 amdgpu_wb_free(adev, index);
683 return r;
684}
685
686/**
687 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
688 *
689 * @ib: indirect buffer to fill with commands
690 * @pe: addr of the page entry
691 * @src: src addr to copy from
692 * @count: number of page entries to update
693 *
694 * Update PTEs by copying them from the GART using sDMA (CIK).
695 */
696static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
697 uint64_t pe, uint64_t src,
698 unsigned count)
699{
700 while (count) {
701 unsigned bytes = count * 8;
702 if (bytes > 0x1FFFF8)
703 bytes = 0x1FFFF8;
704
705 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
706 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
707 ib->ptr[ib->length_dw++] = bytes;
708 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
709 ib->ptr[ib->length_dw++] = lower_32_bits(src);
710 ib->ptr[ib->length_dw++] = upper_32_bits(src);
711 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
712 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
713
714 pe += bytes;
715 src += bytes;
716 count -= bytes / 8;
717 }
718}
719
720/**
721 * cik_sdma_vm_write_pages - update PTEs by writing them manually
722 *
723 * @ib: indirect buffer to fill with commands
724 * @pe: addr of the page entry
725 * @addr: dst addr to write into pe
726 * @count: number of page entries to update
727 * @incr: increase next addr by incr bytes
728 * @flags: access flags
729 *
730 * Update PTEs by writing them manually using sDMA (CIK).
731 */
732static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
733 uint64_t pe,
734 uint64_t addr, unsigned count,
735 uint32_t incr, uint32_t flags)
736{
737 uint64_t value;
738 unsigned ndw;
739
740 while (count) {
741 ndw = count * 2;
742 if (ndw > 0xFFFFE)
743 ndw = 0xFFFFE;
744
745 /* for non-physically contiguous pages (system) */
746 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
747 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
748 ib->ptr[ib->length_dw++] = pe;
749 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
750 ib->ptr[ib->length_dw++] = ndw;
751 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
752 if (flags & AMDGPU_PTE_SYSTEM) {
753 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
754 value &= 0xFFFFFFFFFFFFF000ULL;
755 } else if (flags & AMDGPU_PTE_VALID) {
756 value = addr;
757 } else {
758 value = 0;
759 }
760 addr += incr;
761 value |= flags;
762 ib->ptr[ib->length_dw++] = value;
763 ib->ptr[ib->length_dw++] = upper_32_bits(value);
764 }
765 }
766}
767
768/**
769 * cik_sdma_vm_set_pages - update the page tables using sDMA
770 *
771 * @ib: indirect buffer to fill with commands
772 * @pe: addr of the page entry
773 * @addr: dst addr to write into pe
774 * @count: number of page entries to update
775 * @incr: increase next addr by incr bytes
776 * @flags: access flags
777 *
778 * Update the page tables using sDMA (CIK).
779 */
780static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
781 uint64_t pe,
782 uint64_t addr, unsigned count,
783 uint32_t incr, uint32_t flags)
784{
785 uint64_t value;
786 unsigned ndw;
787
788 while (count) {
789 ndw = count;
790 if (ndw > 0x7FFFF)
791 ndw = 0x7FFFF;
792
793 if (flags & AMDGPU_PTE_VALID)
794 value = addr;
795 else
796 value = 0;
797
798 /* for physically contiguous pages (vram) */
799 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
800 ib->ptr[ib->length_dw++] = pe; /* dst addr */
801 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
802 ib->ptr[ib->length_dw++] = flags; /* mask */
803 ib->ptr[ib->length_dw++] = 0;
804 ib->ptr[ib->length_dw++] = value; /* value */
805 ib->ptr[ib->length_dw++] = upper_32_bits(value);
806 ib->ptr[ib->length_dw++] = incr; /* increment size */
807 ib->ptr[ib->length_dw++] = 0;
808 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
809
810 pe += ndw * 8;
811 addr += ndw * incr;
812 count -= ndw;
813 }
814}
815
816/**
817 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
818 *
819 * @ib: indirect buffer to fill with padding
820 *
821 */
822static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
823{
824 while (ib->length_dw & 0x7)
825 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
826}
827
828/**
829 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
830 *
831 * @ring: amdgpu_ring pointer
832 * @vm: amdgpu_vm pointer
833 *
834 * Update the page table base and flush the VM TLB
835 * using sDMA (CIK).
836 */
837static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
838 unsigned vm_id, uint64_t pd_addr)
839{
840 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
841 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
74a5d165
JX		 842 u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
843 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
a2e73f56
AD		 844
845 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
846 if (vm_id < 8) {
847 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
848 } else {
849 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
850 }
851 amdgpu_ring_write(ring, pd_addr >> 12);
852
853 /* update SH_MEM_* regs */
854 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
855 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
856 amdgpu_ring_write(ring, VMID(vm_id));
857
858 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
859 amdgpu_ring_write(ring, mmSH_MEM_BASES);
860 amdgpu_ring_write(ring, 0);
861
862 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
863 amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
74a5d165 864 amdgpu_ring_write(ring, sh_mem_cfg);
a2e73f56
AD		 865
866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
867 amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
868 amdgpu_ring_write(ring, 1);
869
870 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
871 amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
872 amdgpu_ring_write(ring, 0);
873
874 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
875 amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
876 amdgpu_ring_write(ring, VMID(0));
877
878 /* flush TLB */
879 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
880 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
881 amdgpu_ring_write(ring, 1 << vm_id);
882
883 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
884 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
885 amdgpu_ring_write(ring, 0);
886 amdgpu_ring_write(ring, 0); /* reference */
887 amdgpu_ring_write(ring, 0); /* mask */
888 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
889}
890
891static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
892 bool enable)
893{
894 u32 orig, data;
895
896 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
897 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
898 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
899 } else {
900 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
901 data |= 0xff000000;
902 if (data != orig)
903 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
904
905 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
906 data |= 0xff000000;
907 if (data != orig)
908 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
909 }
910}
911
912static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
913 bool enable)
914{
915 u32 orig, data;
916
917 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
918 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
919 data |= 0x100;
920 if (orig != data)
921 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
922
923 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
924 data |= 0x100;
925 if (orig != data)
926 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
927 } else {
928 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
929 data &= ~0x100;
930 if (orig != data)
931 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
932
933 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
934 data &= ~0x100;
935 if (orig != data)
936 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
937 }
938}
939
940static int cik_sdma_early_init(struct amdgpu_device *adev)
941{
942 cik_sdma_set_ring_funcs(adev);
943 cik_sdma_set_irq_funcs(adev);
944 cik_sdma_set_buffer_funcs(adev);
945 cik_sdma_set_vm_pte_funcs(adev);
946
947 return 0;
948}
949
950static int cik_sdma_sw_init(struct amdgpu_device *adev)
951{
952 struct amdgpu_ring *ring;
953 int r;
954
955 r = cik_sdma_init_microcode(adev);
956 if (r) {
957 DRM_ERROR("Failed to load sdma firmware!\n");
958 return r;
959 }
960
961 /* SDMA trap event */
962 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
963 if (r)
964 return r;
965
966 /* SDMA Privileged inst */
967 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
968 if (r)
969 return r;
970
971 /* SDMA Privileged inst */
972 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
973 if (r)
974 return r;
975
976 ring = &adev->sdma[0].ring;
977 ring->ring_obj = NULL;
978
979 ring = &adev->sdma[1].ring;
980 ring->ring_obj = NULL;
981
982 ring = &adev->sdma[0].ring;
983 sprintf(ring->name, "sdma0");
984 r = amdgpu_ring_init(adev, ring, 256 * 1024,
985 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
986 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
987 AMDGPU_RING_TYPE_SDMA);
988 if (r)
989 return r;
990
991 ring = &adev->sdma[1].ring;
992 sprintf(ring->name, "sdma1");
993 r = amdgpu_ring_init(adev, ring, 256 * 1024,
994 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
995 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
996 AMDGPU_RING_TYPE_SDMA);
997 if (r)
998 return r;
999
1000 return r;
1001}
1002
1003static int cik_sdma_sw_fini(struct amdgpu_device *adev)
1004{
1005 amdgpu_ring_fini(&adev->sdma[0].ring);
1006 amdgpu_ring_fini(&adev->sdma[1].ring);
1007
1008 return 0;
1009}
1010
1011static int cik_sdma_hw_init(struct amdgpu_device *adev)
1012{
1013 int r;
1014
1015 r = cik_sdma_start(adev);
1016 if (r)
1017 return r;
1018
1019 return r;
1020}
1021
1022static int cik_sdma_hw_fini(struct amdgpu_device *adev)
1023{
1024 cik_sdma_enable(adev, false);
1025
1026 return 0;
1027}
1028
1029static int cik_sdma_suspend(struct amdgpu_device *adev)
1030{
1031
1032 return cik_sdma_hw_fini(adev);
1033}
1034
1035static int cik_sdma_resume(struct amdgpu_device *adev)
1036{
1037
1038 return cik_sdma_hw_init(adev);
1039}
1040
1041static bool cik_sdma_is_idle(struct amdgpu_device *adev)
1042{
1043 u32 tmp = RREG32(mmSRBM_STATUS2);
1044
1045 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1046 SRBM_STATUS2__SDMA1_BUSY_MASK))
1047 return false;
1048
1049 return true;
1050}
1051
1052static int cik_sdma_wait_for_idle(struct amdgpu_device *adev)
1053{
1054 unsigned i;
1055 u32 tmp;
1056
1057 for (i = 0; i < adev->usec_timeout; i++) {
1058 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1059 SRBM_STATUS2__SDMA1_BUSY_MASK);
1060
1061 if (!tmp)
1062 return 0;
1063 udelay(1);
1064 }
1065 return -ETIMEDOUT;
1066}
1067
1068static void cik_sdma_print_status(struct amdgpu_device *adev)
1069{
1070 int i, j;
1071
1072 dev_info(adev->dev, "CIK SDMA registers\n");
1073 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1074 RREG32(mmSRBM_STATUS2));
1075 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1076 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1077 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1098 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1099 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1100 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1101 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1102 mutex_lock(&adev->srbm_mutex);
1103 for (j = 0; j < 16; j++) {
1104 cik_srbm_select(adev, 0, 0, 0, j);
1105 dev_info(adev->dev, " VM %d:\n", j);
1106 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1107 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1108 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1109 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1110 }
1111 cik_srbm_select(adev, 0, 0, 0, 0);
1112 mutex_unlock(&adev->srbm_mutex);
1113 }
1114}
1115
1116static int cik_sdma_soft_reset(struct amdgpu_device *adev)
1117{
1118 u32 srbm_soft_reset = 0;
1119 u32 tmp = RREG32(mmSRBM_STATUS2);
1120
1121 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1122 /* sdma0 */
1123 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1124 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1125 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1126 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1127 }
1128 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1129 /* sdma1 */
1130 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1131 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1132 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1133 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1134 }
1135
1136 if (srbm_soft_reset) {
1137 cik_sdma_print_status(adev);
1138
1139 tmp = RREG32(mmSRBM_SOFT_RESET);
1140 tmp |= srbm_soft_reset;
1141 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1142 WREG32(mmSRBM_SOFT_RESET, tmp);
1143 tmp = RREG32(mmSRBM_SOFT_RESET);
1144
1145 udelay(50);
1146
1147 tmp &= ~srbm_soft_reset;
1148 WREG32(mmSRBM_SOFT_RESET, tmp);
1149 tmp = RREG32(mmSRBM_SOFT_RESET);
1150
1151 /* Wait a little for things to settle down */
1152 udelay(50);
1153
1154 cik_sdma_print_status(adev);
1155 }
1156
1157 return 0;
1158}
1159
1160static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1161 struct amdgpu_irq_src *src,
1162 unsigned type,
1163 enum amdgpu_interrupt_state state)
1164{
1165 u32 sdma_cntl;
1166
1167 switch (type) {
1168 case AMDGPU_SDMA_IRQ_TRAP0:
1169 switch (state) {
1170 case AMDGPU_IRQ_STATE_DISABLE:
1171 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1172 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1173 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1174 break;
1175 case AMDGPU_IRQ_STATE_ENABLE:
1176 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1177 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1178 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1179 break;
1180 default:
1181 break;
1182 }
1183 break;
1184 case AMDGPU_SDMA_IRQ_TRAP1:
1185 switch (state) {
1186 case AMDGPU_IRQ_STATE_DISABLE:
1187 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1188 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1189 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1190 break;
1191 case AMDGPU_IRQ_STATE_ENABLE:
1192 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1193 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1194 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1195 break;
1196 default:
1197 break;
1198 }
1199 break;
1200 default:
1201 break;
1202 }
1203 return 0;
1204}
1205
1206static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1207 struct amdgpu_irq_src *source,
1208 struct amdgpu_iv_entry *entry)
1209{
1210 u8 instance_id, queue_id;
1211
1212 instance_id = (entry->ring_id & 0x3) >> 0;
1213 queue_id = (entry->ring_id & 0xc) >> 2;
1214 DRM_DEBUG("IH: SDMA trap\n");
1215 switch (instance_id) {
1216 case 0:
1217 switch (queue_id) {
1218 case 0:
1219 amdgpu_fence_process(&adev->sdma[0].ring);
1220 break;
1221 case 1:
1222 /* XXX compute */
1223 break;
1224 case 2:
1225 /* XXX compute */
1226 break;
1227 }
1228 break;
1229 case 1:
1230 switch (queue_id) {
1231 case 0:
1232 amdgpu_fence_process(&adev->sdma[1].ring);
1233 break;
1234 case 1:
1235 /* XXX compute */
1236 break;
1237 case 2:
1238 /* XXX compute */
1239 break;
1240 }
1241 break;
1242 }
1243
1244 return 0;
1245}
1246
1247static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1248 struct amdgpu_irq_src *source,
1249 struct amdgpu_iv_entry *entry)
1250{
1251 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1252 schedule_work(&adev->reset_work);
1253 return 0;
1254}
1255
1256static int cik_sdma_set_clockgating_state(struct amdgpu_device *adev,
1257 enum amdgpu_clockgating_state state)
1258{
1259 bool gate = false;
1260
1261 if (state == AMDGPU_CG_STATE_GATE)
1262 gate = true;
1263
1264 cik_enable_sdma_mgcg(adev, gate);
1265 cik_enable_sdma_mgls(adev, gate);
1266
1267 return 0;
1268}
1269
1270static int cik_sdma_set_powergating_state(struct amdgpu_device *adev,
1271 enum amdgpu_powergating_state state)
1272{
1273 return 0;
1274}
1275
1276const struct amdgpu_ip_funcs cik_sdma_ip_funcs = {
1277 .early_init = cik_sdma_early_init,
1278 .late_init = NULL,
1279 .sw_init = cik_sdma_sw_init,
1280 .sw_fini = cik_sdma_sw_fini,
1281 .hw_init = cik_sdma_hw_init,
1282 .hw_fini = cik_sdma_hw_fini,
1283 .suspend = cik_sdma_suspend,
1284 .resume = cik_sdma_resume,
1285 .is_idle = cik_sdma_is_idle,
1286 .wait_for_idle = cik_sdma_wait_for_idle,
1287 .soft_reset = cik_sdma_soft_reset,
1288 .print_status = cik_sdma_print_status,
1289 .set_clockgating_state = cik_sdma_set_clockgating_state,
1290 .set_powergating_state = cik_sdma_set_powergating_state,
1291};
1292
1293/**
1294 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1295 *
1296 * @ring: amdgpu_ring structure holding ring information
1297 *
1298 * Check if the async DMA engine is locked up (CIK).
1299 * Returns true if the engine appears to be locked up, false if not.
1300 */
1301static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
1302{
1303
1304 if (cik_sdma_is_idle(ring->adev)) {
1305 amdgpu_ring_lockup_update(ring);
1306 return false;
1307 }
1308 return amdgpu_ring_test_lockup(ring);
1309}
1310
1311static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1312 .get_rptr = cik_sdma_ring_get_rptr,
1313 .get_wptr = cik_sdma_ring_get_wptr,
1314 .set_wptr = cik_sdma_ring_set_wptr,
1315 .parse_cs = NULL,
1316 .emit_ib = cik_sdma_ring_emit_ib,
1317 .emit_fence = cik_sdma_ring_emit_fence,
1318 .emit_semaphore = cik_sdma_ring_emit_semaphore,
1319 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1320 .test_ring = cik_sdma_ring_test_ring,
1321 .test_ib = cik_sdma_ring_test_ib,
1322 .is_lockup = cik_sdma_ring_is_lockup,
1323};
1324
1325static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1326{
1327 adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
1328 adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
1329}
1330
1331static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1332 .set = cik_sdma_set_trap_irq_state,
1333 .process = cik_sdma_process_trap_irq,
1334};
1335
1336static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1337 .process = cik_sdma_process_illegal_inst_irq,
1338};
1339
1340static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1341{
1342 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1343 adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1344 adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1345}
1346
1347/**
1348 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1349 *
1350 * @ring: amdgpu_ring structure holding ring information
1351 * @src_offset: src GPU address
1352 * @dst_offset: dst GPU address
1353 * @byte_count: number of bytes to xfer
1354 *
1355 * Copy GPU buffers using the DMA engine (CIK).
1356 * Used by the amdgpu ttm implementation to move pages if
1357 * registered as the asic copy callback.
1358 */
1359static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring,
1360 uint64_t src_offset,
1361 uint64_t dst_offset,
1362 uint32_t byte_count)
1363{
1364 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
1365 amdgpu_ring_write(ring, byte_count);
1366 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1367 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1368 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1369 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1370 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1371}
1372
1373/**
1374 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1375 *
1376 * @ring: amdgpu_ring structure holding ring information
1377 * @src_data: value to write to buffer
1378 * @dst_offset: dst GPU address
1379 * @byte_count: number of bytes to xfer
1380 *
1381 * Fill GPU buffers using the DMA engine (CIK).
1382 */
1383static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring,
1384 uint32_t src_data,
1385 uint64_t dst_offset,
1386 uint32_t byte_count)
1387{
1388 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0));
1389 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1390 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1391 amdgpu_ring_write(ring, src_data);
1392 amdgpu_ring_write(ring, byte_count);
1393}
1394
1395static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1396 .copy_max_bytes = 0x1fffff,
1397 .copy_num_dw = 7,
1398 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1399
1400 .fill_max_bytes = 0x1fffff,
1401 .fill_num_dw = 5,
1402 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1403};
1404
1405static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1406{
1407 if (adev->mman.buffer_funcs == NULL) {
1408 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1409 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1410 }
1411}
1412
1413static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1414 .copy_pte = cik_sdma_vm_copy_pte,
1415 .write_pte = cik_sdma_vm_write_pte,
1416 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1417 .pad_ib = cik_sdma_vm_pad_ib,
1418};
1419
1420static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1421{
1422 if (adev->vm_manager.vm_pte_funcs == NULL) {
1423 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1424 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1425 }
1426}
Linux kernel - Deliverables
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