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drm/amdgpu: cleanup UAPI comments
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / cik_sdma.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
74a5d165
JX		 36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
a2e73f56
AD		 38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
66
67u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
68
69/*
70 * sDMA - System DMA
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
76 *
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
83 * buffers.
84 */
85
86/**
87 * cik_sdma_init_microcode - load ucode images from disk
88 *
89 * @adev: amdgpu_device pointer
90 *
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
94 */
95static int cik_sdma_init_microcode(struct amdgpu_device *adev)
96{
97 const char *chip_name;
98 char fw_name[30];
99 int err, i;
100
101 DRM_DEBUG("\n");
102
103 switch (adev->asic_type) {
104 case CHIP_BONAIRE:
105 chip_name = "bonaire";
106 break;
107 case CHIP_HAWAII:
108 chip_name = "hawaii";
109 break;
110 case CHIP_KAVERI:
111 chip_name = "kaveri";
112 break;
113 case CHIP_KABINI:
114 chip_name = "kabini";
115 break;
116 case CHIP_MULLINS:
117 chip_name = "mullins";
118 break;
119 default: BUG();
120 }
121
122 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
123 if (i == 0)
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
125 else
126 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
127 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
128 if (err)
129 goto out;
130 err = amdgpu_ucode_validate(adev->sdma[i].fw);
131 }
132out:
133 if (err) {
134 printk(KERN_ERR
135 "cik_sdma: Failed to load firmware \"%s\"\n",
136 fw_name);
137 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
138 release_firmware(adev->sdma[i].fw);
139 adev->sdma[i].fw = NULL;
140 }
141 }
142 return err;
143}
144
145/**
146 * cik_sdma_ring_get_rptr - get the current read pointer
147 *
148 * @ring: amdgpu ring pointer
149 *
150 * Get the current rptr from the hardware (CIK+).
151 */
152static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
153{
154 u32 rptr;
155
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
157
158 return (rptr & 0x3fffc) >> 2;
159}
160
161/**
162 * cik_sdma_ring_get_wptr - get the current write pointer
163 *
164 * @ring: amdgpu ring pointer
165 *
166 * Get the current wptr from the hardware (CIK+).
167 */
168static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
169{
170 struct amdgpu_device *adev = ring->adev;
171 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
172
173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
174}
175
176/**
177 * cik_sdma_ring_set_wptr - commit the write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Write the wptr back to the hardware (CIK+).
182 */
183static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184{
185 struct amdgpu_device *adev = ring->adev;
186 u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
187
188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
189}
190
a2e73f56
AD		 191/**
192 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
193 *
194 * @ring: amdgpu ring pointer
195 * @ib: IB object to schedule
196 *
197 * Schedule an IB in the DMA ring (CIK).
198 */
199static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
200 struct amdgpu_ib *ib)
201{
202 u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
203 u32 next_rptr = ring->wptr + 5;
204
a2e73f56
AD		 205 while ((next_rptr & 7) != 4)
206 next_rptr++;
207
208 next_rptr += 4;
209 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
210 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
211 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
212 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
213 amdgpu_ring_write(ring, next_rptr);
214
a2e73f56
AD		 215 /* IB packet must end on a 8 DW boundary */
216 while ((ring->wptr & 7) != 4)
217 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
218 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
219 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
220 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
221 amdgpu_ring_write(ring, ib->length_dw);
222
223}
224
225/**
d2edb07b 226 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
a2e73f56
AD		 227 *
228 * @ring: amdgpu ring pointer
229 *
230 * Emit an hdp flush packet on the requested DMA ring.
231 */
d2edb07b 232static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 233{
234 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
235 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
236 u32 ref_and_mask;
237
238 if (ring == &ring->adev->sdma[0].ring)
239 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
240 else
241 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
242
243 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
244 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
245 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
246 amdgpu_ring_write(ring, ref_and_mask); /* reference */
247 amdgpu_ring_write(ring, ref_and_mask); /* mask */
248 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
249}
250
251/**
252 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
253 *
254 * @ring: amdgpu ring pointer
255 * @fence: amdgpu fence object
256 *
257 * Add a DMA fence packet to the ring to write
258 * the fence seq number and DMA trap packet to generate
259 * an interrupt if needed (CIK).
260 */
261static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 262 unsigned flags)
a2e73f56 263{
890ee23f 264 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
a2e73f56
AD		 265 /* write the fence */
266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
267 amdgpu_ring_write(ring, lower_32_bits(addr));
268 amdgpu_ring_write(ring, upper_32_bits(addr));
269 amdgpu_ring_write(ring, lower_32_bits(seq));
270
271 /* optionally write high bits as well */
272 if (write64bit) {
273 addr += 4;
274 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
275 amdgpu_ring_write(ring, lower_32_bits(addr));
276 amdgpu_ring_write(ring, upper_32_bits(addr));
277 amdgpu_ring_write(ring, upper_32_bits(seq));
278 }
279
280 /* generate an interrupt */
281 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
282}
283
284/**
285 * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
286 *
287 * @ring: amdgpu_ring structure holding ring information
288 * @semaphore: amdgpu semaphore object
289 * @emit_wait: wait or signal semaphore
290 *
291 * Add a DMA semaphore packet to the ring wait on or signal
292 * other rings (CIK).
293 */
294static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
295 struct amdgpu_semaphore *semaphore,
296 bool emit_wait)
297{
298 u64 addr = semaphore->gpu_addr;
299 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
300
301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
302 amdgpu_ring_write(ring, addr & 0xfffffff8);
303 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
304
305 return true;
306}
307
308/**
309 * cik_sdma_gfx_stop - stop the gfx async dma engines
310 *
311 * @adev: amdgpu_device pointer
312 *
313 * Stop the gfx async dma ring buffers (CIK).
314 */
315static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
316{
317 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
318 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
319 u32 rb_cntl;
320 int i;
321
322 if ((adev->mman.buffer_funcs_ring == sdma0) ||
323 (adev->mman.buffer_funcs_ring == sdma1))
324 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
325
326 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
327 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
328 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
329 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
330 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
331 }
332 sdma0->ready = false;
333 sdma1->ready = false;
334}
335
336/**
337 * cik_sdma_rlc_stop - stop the compute async dma engines
338 *
339 * @adev: amdgpu_device pointer
340 *
341 * Stop the compute async dma queues (CIK).
342 */
343static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
344{
345 /* XXX todo */
346}
347
348/**
349 * cik_sdma_enable - stop the async dma engines
350 *
351 * @adev: amdgpu_device pointer
352 * @enable: enable/disable the DMA MEs.
353 *
354 * Halt or unhalt the async dma engines (CIK).
355 */
356static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
357{
358 u32 me_cntl;
359 int i;
360
361 if (enable == false) {
362 cik_sdma_gfx_stop(adev);
363 cik_sdma_rlc_stop(adev);
364 }
365
366 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
367 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
368 if (enable)
369 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
370 else
371 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
372 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
373 }
374}
375
376/**
377 * cik_sdma_gfx_resume - setup and start the async dma engines
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * Set up the gfx DMA ring buffers and enable them (CIK).
382 * Returns 0 for success, error for failure.
383 */
384static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
385{
386 struct amdgpu_ring *ring;
387 u32 rb_cntl, ib_cntl;
388 u32 rb_bufsz;
389 u32 wb_offset;
390 int i, j, r;
391
392 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
393 ring = &adev->sdma[i].ring;
394 wb_offset = (ring->rptr_offs * 4);
395
396 mutex_lock(&adev->srbm_mutex);
397 for (j = 0; j < 16; j++) {
398 cik_srbm_select(adev, 0, 0, 0, j);
399 /* SDMA GFX */
400 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
401 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
402 /* XXX SDMA RLC - todo */
403 }
404 cik_srbm_select(adev, 0, 0, 0, 0);
405 mutex_unlock(&adev->srbm_mutex);
406
407 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
408 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
409
410 /* Set ring buffer size in dwords */
411 rb_bufsz = order_base_2(ring->ring_size / 4);
412 rb_cntl = rb_bufsz << 1;
413#ifdef __BIG_ENDIAN
414 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
415#endif
416 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
417
418 /* Initialize the ring buffer's read and write pointers */
419 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
420 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
421
422 /* set the wb address whether it's enabled or not */
423 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
424 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
425 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
426 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
427
428 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
429
430 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
431 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
432
433 ring->wptr = 0;
434 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
435
436 /* enable DMA RB */
437 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
438 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
439
440 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
441#ifdef __BIG_ENDIAN
442 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
443#endif
444 /* enable DMA IBs */
445 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
446
447 ring->ready = true;
448
449 r = amdgpu_ring_test_ring(ring);
450 if (r) {
451 ring->ready = false;
452 return r;
453 }
454
455 if (adev->mman.buffer_funcs_ring == ring)
456 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
457 }
458
459 return 0;
460}
461
462/**
463 * cik_sdma_rlc_resume - setup and start the async dma engines
464 *
465 * @adev: amdgpu_device pointer
466 *
467 * Set up the compute DMA queues and enable them (CIK).
468 * Returns 0 for success, error for failure.
469 */
470static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
471{
472 /* XXX todo */
473 return 0;
474}
475
476/**
477 * cik_sdma_load_microcode - load the sDMA ME ucode
478 *
479 * @adev: amdgpu_device pointer
480 *
481 * Loads the sDMA0/1 ucode.
482 * Returns 0 for success, -EINVAL if the ucode is not available.
483 */
484static int cik_sdma_load_microcode(struct amdgpu_device *adev)
485{
486 const struct sdma_firmware_header_v1_0 *hdr;
487 const __le32 *fw_data;
488 u32 fw_size;
489 int i, j;
490
491 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
492 return -EINVAL;
493
494 /* halt the MEs */
495 cik_sdma_enable(adev, false);
496
497 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
498 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
499 amdgpu_ucode_print_sdma_hdr(&hdr->header);
500 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
501 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
502 fw_data = (const __le32 *)
503 (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
504 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
505 for (j = 0; j < fw_size; j++)
506 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
507 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
508 }
509
510 return 0;
511}
512
513/**
514 * cik_sdma_start - setup and start the async dma engines
515 *
516 * @adev: amdgpu_device pointer
517 *
518 * Set up the DMA engines and enable them (CIK).
519 * Returns 0 for success, error for failure.
520 */
521static int cik_sdma_start(struct amdgpu_device *adev)
522{
523 int r;
524
525 r = cik_sdma_load_microcode(adev);
526 if (r)
527 return r;
528
529 /* unhalt the MEs */
530 cik_sdma_enable(adev, true);
531
532 /* start the gfx rings and rlc compute queues */
533 r = cik_sdma_gfx_resume(adev);
534 if (r)
535 return r;
536 r = cik_sdma_rlc_resume(adev);
537 if (r)
538 return r;
539
540 return 0;
541}
542
543/**
544 * cik_sdma_ring_test_ring - simple async dma engine test
545 *
546 * @ring: amdgpu_ring structure holding ring information
547 *
548 * Test the DMA engine by writing using it to write an
549 * value to memory. (CIK).
550 * Returns 0 for success, error for failure.
551 */
552static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
553{
554 struct amdgpu_device *adev = ring->adev;
555 unsigned i;
556 unsigned index;
557 int r;
558 u32 tmp;
559 u64 gpu_addr;
560
561 r = amdgpu_wb_get(adev, &index);
562 if (r) {
563 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
564 return r;
565 }
566
567 gpu_addr = adev->wb.gpu_addr + (index * 4);
568 tmp = 0xCAFEDEAD;
569 adev->wb.wb[index] = cpu_to_le32(tmp);
570
571 r = amdgpu_ring_lock(ring, 5);
572 if (r) {
573 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
574 amdgpu_wb_free(adev, index);
575 return r;
576 }
577 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
578 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
579 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
580 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
581 amdgpu_ring_write(ring, 0xDEADBEEF);
582 amdgpu_ring_unlock_commit(ring);
583
584 for (i = 0; i < adev->usec_timeout; i++) {
585 tmp = le32_to_cpu(adev->wb.wb[index]);
586 if (tmp == 0xDEADBEEF)
587 break;
588 DRM_UDELAY(1);
589 }
590
591 if (i < adev->usec_timeout) {
592 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
593 } else {
594 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
595 ring->idx, tmp);
596 r = -EINVAL;
597 }
598 amdgpu_wb_free(adev, index);
599
600 return r;
601}
602
603/**
604 * cik_sdma_ring_test_ib - test an IB on the DMA engine
605 *
606 * @ring: amdgpu_ring structure holding ring information
607 *
608 * Test a simple IB in the DMA ring (CIK).
609 * Returns 0 on success, error on failure.
610 */
611static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
612{
613 struct amdgpu_device *adev = ring->adev;
614 struct amdgpu_ib ib;
615 unsigned i;
616 unsigned index;
617 int r;
618 u32 tmp = 0;
619 u64 gpu_addr;
620
621 r = amdgpu_wb_get(adev, &index);
622 if (r) {
623 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
624 return r;
625 }
626
627 gpu_addr = adev->wb.gpu_addr + (index * 4);
628 tmp = 0xCAFEDEAD;
629 adev->wb.wb[index] = cpu_to_le32(tmp);
630
631 r = amdgpu_ib_get(ring, NULL, 256, &ib);
632 if (r) {
633 amdgpu_wb_free(adev, index);
634 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
635 return r;
636 }
637
638 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
639 ib.ptr[1] = lower_32_bits(gpu_addr);
640 ib.ptr[2] = upper_32_bits(gpu_addr);
641 ib.ptr[3] = 1;
642 ib.ptr[4] = 0xDEADBEEF;
643 ib.length_dw = 5;
644
645 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
646 if (r) {
647 amdgpu_ib_free(adev, &ib);
648 amdgpu_wb_free(adev, index);
649 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
650 return r;
651 }
652 r = amdgpu_fence_wait(ib.fence, false);
653 if (r) {
654 amdgpu_ib_free(adev, &ib);
655 amdgpu_wb_free(adev, index);
656 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
657 return r;
658 }
659 for (i = 0; i < adev->usec_timeout; i++) {
660 tmp = le32_to_cpu(adev->wb.wb[index]);
661 if (tmp == 0xDEADBEEF)
662 break;
663 DRM_UDELAY(1);
664 }
665 if (i < adev->usec_timeout) {
666 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
667 ib.fence->ring->idx, i);
668 } else {
669 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
670 r = -EINVAL;
671 }
672 amdgpu_ib_free(adev, &ib);
673 amdgpu_wb_free(adev, index);
674 return r;
675}
676
677/**
678 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
679 *
680 * @ib: indirect buffer to fill with commands
681 * @pe: addr of the page entry
682 * @src: src addr to copy from
683 * @count: number of page entries to update
684 *
685 * Update PTEs by copying them from the GART using sDMA (CIK).
686 */
687static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
688 uint64_t pe, uint64_t src,
689 unsigned count)
690{
691 while (count) {
692 unsigned bytes = count * 8;
693 if (bytes > 0x1FFFF8)
694 bytes = 0x1FFFF8;
695
696 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
697 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
698 ib->ptr[ib->length_dw++] = bytes;
699 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
700 ib->ptr[ib->length_dw++] = lower_32_bits(src);
701 ib->ptr[ib->length_dw++] = upper_32_bits(src);
702 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
703 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
704
705 pe += bytes;
706 src += bytes;
707 count -= bytes / 8;
708 }
709}
710
711/**
712 * cik_sdma_vm_write_pages - update PTEs by writing them manually
713 *
714 * @ib: indirect buffer to fill with commands
715 * @pe: addr of the page entry
716 * @addr: dst addr to write into pe
717 * @count: number of page entries to update
718 * @incr: increase next addr by incr bytes
719 * @flags: access flags
720 *
721 * Update PTEs by writing them manually using sDMA (CIK).
722 */
723static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
724 uint64_t pe,
725 uint64_t addr, unsigned count,
726 uint32_t incr, uint32_t flags)
727{
728 uint64_t value;
729 unsigned ndw;
730
731 while (count) {
732 ndw = count * 2;
733 if (ndw > 0xFFFFE)
734 ndw = 0xFFFFE;
735
736 /* for non-physically contiguous pages (system) */
737 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
738 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
739 ib->ptr[ib->length_dw++] = pe;
740 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
741 ib->ptr[ib->length_dw++] = ndw;
742 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
743 if (flags & AMDGPU_PTE_SYSTEM) {
744 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
745 value &= 0xFFFFFFFFFFFFF000ULL;
746 } else if (flags & AMDGPU_PTE_VALID) {
747 value = addr;
748 } else {
749 value = 0;
750 }
751 addr += incr;
752 value |= flags;
753 ib->ptr[ib->length_dw++] = value;
754 ib->ptr[ib->length_dw++] = upper_32_bits(value);
755 }
756 }
757}
758
759/**
760 * cik_sdma_vm_set_pages - update the page tables using sDMA
761 *
762 * @ib: indirect buffer to fill with commands
763 * @pe: addr of the page entry
764 * @addr: dst addr to write into pe
765 * @count: number of page entries to update
766 * @incr: increase next addr by incr bytes
767 * @flags: access flags
768 *
769 * Update the page tables using sDMA (CIK).
770 */
771static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
772 uint64_t pe,
773 uint64_t addr, unsigned count,
774 uint32_t incr, uint32_t flags)
775{
776 uint64_t value;
777 unsigned ndw;
778
779 while (count) {
780 ndw = count;
781 if (ndw > 0x7FFFF)
782 ndw = 0x7FFFF;
783
784 if (flags & AMDGPU_PTE_VALID)
785 value = addr;
786 else
787 value = 0;
788
789 /* for physically contiguous pages (vram) */
790 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
791 ib->ptr[ib->length_dw++] = pe; /* dst addr */
792 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
793 ib->ptr[ib->length_dw++] = flags; /* mask */
794 ib->ptr[ib->length_dw++] = 0;
795 ib->ptr[ib->length_dw++] = value; /* value */
796 ib->ptr[ib->length_dw++] = upper_32_bits(value);
797 ib->ptr[ib->length_dw++] = incr; /* increment size */
798 ib->ptr[ib->length_dw++] = 0;
799 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
800
801 pe += ndw * 8;
802 addr += ndw * incr;
803 count -= ndw;
804 }
805}
806
807/**
808 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
809 *
810 * @ib: indirect buffer to fill with padding
811 *
812 */
813static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
814{
815 while (ib->length_dw & 0x7)
816 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
817}
818
819/**
820 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
821 *
822 * @ring: amdgpu_ring pointer
823 * @vm: amdgpu_vm pointer
824 *
825 * Update the page table base and flush the VM TLB
826 * using sDMA (CIK).
827 */
828static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
829 unsigned vm_id, uint64_t pd_addr)
830{
831 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
832 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
833
834 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
835 if (vm_id < 8) {
836 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
837 } else {
838 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
839 }
840 amdgpu_ring_write(ring, pd_addr >> 12);
841
a2e73f56
AD		 842 /* flush TLB */
843 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
844 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
845 amdgpu_ring_write(ring, 1 << vm_id);
846
847 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
848 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
849 amdgpu_ring_write(ring, 0);
850 amdgpu_ring_write(ring, 0); /* reference */
851 amdgpu_ring_write(ring, 0); /* mask */
852 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
853}
854
855static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
856 bool enable)
857{
858 u32 orig, data;
859
860 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
861 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
862 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
863 } else {
864 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
865 data |= 0xff000000;
866 if (data != orig)
867 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
868
869 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
870 data |= 0xff000000;
871 if (data != orig)
872 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
873 }
874}
875
876static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
877 bool enable)
878{
879 u32 orig, data;
880
881 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
882 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
883 data |= 0x100;
884 if (orig != data)
885 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
886
887 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
888 data |= 0x100;
889 if (orig != data)
890 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
891 } else {
892 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
893 data &= ~0x100;
894 if (orig != data)
895 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
896
897 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
898 data &= ~0x100;
899 if (orig != data)
900 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
901 }
902}
903
5fc3aeeb 904static int cik_sdma_early_init(void *handle)
a2e73f56 905{
5fc3aeeb 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
907
a2e73f56
AD		 908 cik_sdma_set_ring_funcs(adev);
909 cik_sdma_set_irq_funcs(adev);
910 cik_sdma_set_buffer_funcs(adev);
911 cik_sdma_set_vm_pte_funcs(adev);
912
913 return 0;
914}
915
5fc3aeeb 916static int cik_sdma_sw_init(void *handle)
a2e73f56
AD		 917{
918 struct amdgpu_ring *ring;
5fc3aeeb 919 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 920 int r;
921
922 r = cik_sdma_init_microcode(adev);
923 if (r) {
924 DRM_ERROR("Failed to load sdma firmware!\n");
925 return r;
926 }
927
928 /* SDMA trap event */
929 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
930 if (r)
931 return r;
932
933 /* SDMA Privileged inst */
934 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
935 if (r)
936 return r;
937
938 /* SDMA Privileged inst */
939 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
940 if (r)
941 return r;
942
943 ring = &adev->sdma[0].ring;
944 ring->ring_obj = NULL;
945
946 ring = &adev->sdma[1].ring;
947 ring->ring_obj = NULL;
948
949 ring = &adev->sdma[0].ring;
950 sprintf(ring->name, "sdma0");
951 r = amdgpu_ring_init(adev, ring, 256 * 1024,
952 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
953 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
954 AMDGPU_RING_TYPE_SDMA);
955 if (r)
956 return r;
957
958 ring = &adev->sdma[1].ring;
959 sprintf(ring->name, "sdma1");
960 r = amdgpu_ring_init(adev, ring, 256 * 1024,
961 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
962 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
963 AMDGPU_RING_TYPE_SDMA);
964 if (r)
965 return r;
966
967 return r;
968}
969
5fc3aeeb 970static int cik_sdma_sw_fini(void *handle)
a2e73f56 971{
5fc3aeeb 972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
973
a2e73f56
AD		 974 amdgpu_ring_fini(&adev->sdma[0].ring);
975 amdgpu_ring_fini(&adev->sdma[1].ring);
976
977 return 0;
978}
979
5fc3aeeb 980static int cik_sdma_hw_init(void *handle)
a2e73f56
AD		 981{
982 int r;
5fc3aeeb 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 984
985 r = cik_sdma_start(adev);
986 if (r)
987 return r;
988
989 return r;
990}
991
5fc3aeeb 992static int cik_sdma_hw_fini(void *handle)
a2e73f56 993{
5fc3aeeb 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
995
a2e73f56
AD		 996 cik_sdma_enable(adev, false);
997
998 return 0;
999}
1000
5fc3aeeb 1001static int cik_sdma_suspend(void *handle)
a2e73f56 1002{
5fc3aeeb 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1004
1005 return cik_sdma_hw_fini(adev);
1006}
1007
5fc3aeeb 1008static int cik_sdma_resume(void *handle)
a2e73f56 1009{
5fc3aeeb 1010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1011
1012 return cik_sdma_hw_init(adev);
1013}
1014
5fc3aeeb 1015static bool cik_sdma_is_idle(void *handle)
a2e73f56 1016{
5fc3aeeb 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1018 u32 tmp = RREG32(mmSRBM_STATUS2);
1019
1020 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1021 SRBM_STATUS2__SDMA1_BUSY_MASK))
1022 return false;
1023
1024 return true;
1025}
1026
5fc3aeeb 1027static int cik_sdma_wait_for_idle(void *handle)
a2e73f56
AD		 1028{
1029 unsigned i;
1030 u32 tmp;
5fc3aeeb 1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1032
1033 for (i = 0; i < adev->usec_timeout; i++) {
1034 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1035 SRBM_STATUS2__SDMA1_BUSY_MASK);
1036
1037 if (!tmp)
1038 return 0;
1039 udelay(1);
1040 }
1041 return -ETIMEDOUT;
1042}
1043
5fc3aeeb 1044static void cik_sdma_print_status(void *handle)
a2e73f56
AD		 1045{
1046 int i, j;
5fc3aeeb 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1048
1049 dev_info(adev->dev, "CIK SDMA registers\n");
1050 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1051 RREG32(mmSRBM_STATUS2));
1052 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1053 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1054 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1055 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1056 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1057 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1058 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1059 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1060 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1061 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1062 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1063 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1064 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1065 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1066 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1067 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1068 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1069 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1070 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1071 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1072 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1073 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1074 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1075 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1076 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1077 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1078 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1079 mutex_lock(&adev->srbm_mutex);
1080 for (j = 0; j < 16; j++) {
1081 cik_srbm_select(adev, 0, 0, 0, j);
1082 dev_info(adev->dev, " VM %d:\n", j);
1083 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1084 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1085 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1086 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1087 }
1088 cik_srbm_select(adev, 0, 0, 0, 0);
1089 mutex_unlock(&adev->srbm_mutex);
1090 }
1091}
1092
5fc3aeeb 1093static int cik_sdma_soft_reset(void *handle)
a2e73f56
AD		 1094{
1095 u32 srbm_soft_reset = 0;
5fc3aeeb 1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 1097 u32 tmp = RREG32(mmSRBM_STATUS2);
1098
1099 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1100 /* sdma0 */
1101 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1102 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1103 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1104 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1105 }
1106 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1107 /* sdma1 */
1108 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1109 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1110 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1111 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1112 }
1113
1114 if (srbm_soft_reset) {
5fc3aeeb 1115 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1116
1117 tmp = RREG32(mmSRBM_SOFT_RESET);
1118 tmp |= srbm_soft_reset;
1119 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1120 WREG32(mmSRBM_SOFT_RESET, tmp);
1121 tmp = RREG32(mmSRBM_SOFT_RESET);
1122
1123 udelay(50);
1124
1125 tmp &= ~srbm_soft_reset;
1126 WREG32(mmSRBM_SOFT_RESET, tmp);
1127 tmp = RREG32(mmSRBM_SOFT_RESET);
1128
1129 /* Wait a little for things to settle down */
1130 udelay(50);
1131
5fc3aeeb 1132 cik_sdma_print_status((void *)adev);
a2e73f56
AD		 1133 }
1134
1135 return 0;
1136}
1137
1138static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1139 struct amdgpu_irq_src *src,
1140 unsigned type,
1141 enum amdgpu_interrupt_state state)
1142{
1143 u32 sdma_cntl;
1144
1145 switch (type) {
1146 case AMDGPU_SDMA_IRQ_TRAP0:
1147 switch (state) {
1148 case AMDGPU_IRQ_STATE_DISABLE:
1149 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1150 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1151 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1152 break;
1153 case AMDGPU_IRQ_STATE_ENABLE:
1154 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1155 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1156 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1157 break;
1158 default:
1159 break;
1160 }
1161 break;
1162 case AMDGPU_SDMA_IRQ_TRAP1:
1163 switch (state) {
1164 case AMDGPU_IRQ_STATE_DISABLE:
1165 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1166 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1167 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1168 break;
1169 case AMDGPU_IRQ_STATE_ENABLE:
1170 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1171 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1172 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1173 break;
1174 default:
1175 break;
1176 }
1177 break;
1178 default:
1179 break;
1180 }
1181 return 0;
1182}
1183
1184static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1185 struct amdgpu_irq_src *source,
1186 struct amdgpu_iv_entry *entry)
1187{
1188 u8 instance_id, queue_id;
1189
1190 instance_id = (entry->ring_id & 0x3) >> 0;
1191 queue_id = (entry->ring_id & 0xc) >> 2;
1192 DRM_DEBUG("IH: SDMA trap\n");
1193 switch (instance_id) {
1194 case 0:
1195 switch (queue_id) {
1196 case 0:
1197 amdgpu_fence_process(&adev->sdma[0].ring);
1198 break;
1199 case 1:
1200 /* XXX compute */
1201 break;
1202 case 2:
1203 /* XXX compute */
1204 break;
1205 }
1206 break;
1207 case 1:
1208 switch (queue_id) {
1209 case 0:
1210 amdgpu_fence_process(&adev->sdma[1].ring);
1211 break;
1212 case 1:
1213 /* XXX compute */
1214 break;
1215 case 2:
1216 /* XXX compute */
1217 break;
1218 }
1219 break;
1220 }
1221
1222 return 0;
1223}
1224
1225static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1226 struct amdgpu_irq_src *source,
1227 struct amdgpu_iv_entry *entry)
1228{
1229 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1230 schedule_work(&adev->reset_work);
1231 return 0;
1232}
1233
5fc3aeeb 1234static int cik_sdma_set_clockgating_state(void *handle,
1235 enum amd_clockgating_state state)
a2e73f56
AD		 1236{
1237 bool gate = false;
5fc3aeeb 1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 1239
5fc3aeeb 1240 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 1241 gate = true;
1242
1243 cik_enable_sdma_mgcg(adev, gate);
1244 cik_enable_sdma_mgls(adev, gate);
1245
1246 return 0;
1247}
1248
5fc3aeeb 1249static int cik_sdma_set_powergating_state(void *handle,
1250 enum amd_powergating_state state)
a2e73f56
AD		 1251{
1252 return 0;
1253}
1254
5fc3aeeb 1255const struct amd_ip_funcs cik_sdma_ip_funcs = {
a2e73f56
AD		 1256 .early_init = cik_sdma_early_init,
1257 .late_init = NULL,
1258 .sw_init = cik_sdma_sw_init,
1259 .sw_fini = cik_sdma_sw_fini,
1260 .hw_init = cik_sdma_hw_init,
1261 .hw_fini = cik_sdma_hw_fini,
1262 .suspend = cik_sdma_suspend,
1263 .resume = cik_sdma_resume,
1264 .is_idle = cik_sdma_is_idle,
1265 .wait_for_idle = cik_sdma_wait_for_idle,
1266 .soft_reset = cik_sdma_soft_reset,
1267 .print_status = cik_sdma_print_status,
1268 .set_clockgating_state = cik_sdma_set_clockgating_state,
1269 .set_powergating_state = cik_sdma_set_powergating_state,
1270};
1271
1272/**
1273 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1274 *
1275 * @ring: amdgpu_ring structure holding ring information
1276 *
1277 * Check if the async DMA engine is locked up (CIK).
1278 * Returns true if the engine appears to be locked up, false if not.
1279 */
1280static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
1281{
1282
1283 if (cik_sdma_is_idle(ring->adev)) {
1284 amdgpu_ring_lockup_update(ring);
1285 return false;
1286 }
1287 return amdgpu_ring_test_lockup(ring);
1288}
1289
1290static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1291 .get_rptr = cik_sdma_ring_get_rptr,
1292 .get_wptr = cik_sdma_ring_get_wptr,
1293 .set_wptr = cik_sdma_ring_set_wptr,
1294 .parse_cs = NULL,
1295 .emit_ib = cik_sdma_ring_emit_ib,
1296 .emit_fence = cik_sdma_ring_emit_fence,
1297 .emit_semaphore = cik_sdma_ring_emit_semaphore,
1298 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
d2edb07b 1299 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
a2e73f56
AD		 1300 .test_ring = cik_sdma_ring_test_ring,
1301 .test_ib = cik_sdma_ring_test_ib,
1302 .is_lockup = cik_sdma_ring_is_lockup,
1303};
1304
1305static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1306{
1307 adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
1308 adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
1309}
1310
1311static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1312 .set = cik_sdma_set_trap_irq_state,
1313 .process = cik_sdma_process_trap_irq,
1314};
1315
1316static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1317 .process = cik_sdma_process_illegal_inst_irq,
1318};
1319
1320static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1321{
1322 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1323 adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1324 adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1325}
1326
1327/**
1328 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1329 *
1330 * @ring: amdgpu_ring structure holding ring information
1331 * @src_offset: src GPU address
1332 * @dst_offset: dst GPU address
1333 * @byte_count: number of bytes to xfer
1334 *
1335 * Copy GPU buffers using the DMA engine (CIK).
1336 * Used by the amdgpu ttm implementation to move pages if
1337 * registered as the asic copy callback.
1338 */
1339static void cik_sdma_emit_copy_buffer(struct amdgpu_ring *ring,
1340 uint64_t src_offset,
1341 uint64_t dst_offset,
1342 uint32_t byte_count)
1343{
1344 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
1345 amdgpu_ring_write(ring, byte_count);
1346 amdgpu_ring_write(ring, 0); /* src/dst endian swap */
1347 amdgpu_ring_write(ring, lower_32_bits(src_offset));
1348 amdgpu_ring_write(ring, upper_32_bits(src_offset));
1349 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1350 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1351}
1352
1353/**
1354 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1355 *
1356 * @ring: amdgpu_ring structure holding ring information
1357 * @src_data: value to write to buffer
1358 * @dst_offset: dst GPU address
1359 * @byte_count: number of bytes to xfer
1360 *
1361 * Fill GPU buffers using the DMA engine (CIK).
1362 */
1363static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring,
1364 uint32_t src_data,
1365 uint64_t dst_offset,
1366 uint32_t byte_count)
1367{
1368 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0));
1369 amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1370 amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1371 amdgpu_ring_write(ring, src_data);
1372 amdgpu_ring_write(ring, byte_count);
1373}
1374
1375static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1376 .copy_max_bytes = 0x1fffff,
1377 .copy_num_dw = 7,
1378 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1379
1380 .fill_max_bytes = 0x1fffff,
1381 .fill_num_dw = 5,
1382 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1383};
1384
1385static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1386{
1387 if (adev->mman.buffer_funcs == NULL) {
1388 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1389 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1390 }
1391}
1392
1393static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1394 .copy_pte = cik_sdma_vm_copy_pte,
1395 .write_pte = cik_sdma_vm_write_pte,
1396 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1397 .pad_ib = cik_sdma_vm_pad_ib,
1398};
1399
1400static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1401{
1402 if (adev->vm_manager.vm_pte_funcs == NULL) {
1403 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1404 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1405 }
1406}
Linux kernel - Deliverables
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